aasmcpu.pas 81 KB

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  1. {
  2. Copyright (c) 2003 by Florian Klaempfl
  3. Contains the assembler object for the ARM
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit aasmcpu;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. cclasses,globtype,globals,verbose,
  22. aasmbase,aasmtai,aasmdata,aasmsym,
  23. ogbase,
  24. symtype,
  25. cpubase,cpuinfo,cgbase,cgutils;
  26. const
  27. { "mov reg,reg" source operand number }
  28. O_MOV_SOURCE = 1;
  29. { "mov reg,reg" source operand number }
  30. O_MOV_DEST = 0;
  31. { Operand types }
  32. OT_NONE = $00000000;
  33. OT_BITS8 = $00000001; { size, and other attributes, of the operand }
  34. OT_BITS16 = $00000002;
  35. OT_BITS32 = $00000004;
  36. OT_BITS64 = $00000008; { FPU only }
  37. OT_BITS80 = $00000010;
  38. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  39. OT_NEAR = $00000040;
  40. OT_SHORT = $00000080;
  41. OT_BITSTINY = $00000100; { fpu constant }
  42. OT_BITSSHIFTER =
  43. $00000200;
  44. OT_SIZE_MASK = $000003FF; { all the size attributes }
  45. OT_NON_SIZE = longint(not OT_SIZE_MASK);
  46. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  47. OT_TO = $00000200; { operand is followed by a colon }
  48. { reverse effect in FADD, FSUB &c }
  49. OT_COLON = $00000400;
  50. OT_SHIFTEROP = $00000800;
  51. OT_REGISTER = $00001000;
  52. OT_IMMEDIATE = $00002000;
  53. OT_REGLIST = $00008000;
  54. OT_IMM8 = $00002001;
  55. OT_IMM24 = $00002002;
  56. OT_IMM32 = $00002004;
  57. OT_IMM64 = $00002008;
  58. OT_IMM80 = $00002010;
  59. OT_IMMTINY = $00002100;
  60. OT_IMMSHIFTER= $00002200;
  61. OT_IMMEDIATE24 = OT_IMM24;
  62. OT_SHIFTIMM = OT_SHIFTEROP or OT_IMMSHIFTER;
  63. OT_SHIFTIMMEDIATE = OT_SHIFTIMM;
  64. OT_IMMEDIATESHIFTER = OT_IMMSHIFTER;
  65. OT_IMMEDIATEFPU = OT_IMMTINY;
  66. OT_REGMEM = $00200000; { for r/m, ie EA, operands }
  67. OT_REGNORM = $00201000; { 'normal' reg, qualifies as EA }
  68. OT_REG8 = $00201001;
  69. OT_REG16 = $00201002;
  70. OT_REG32 = $00201004;
  71. OT_REG64 = $00201008;
  72. OT_VREG = $00201010; { vector register }
  73. OT_REGF = $00201020; { coproc register }
  74. OT_MEMORY = $00204000; { register number in 'basereg' }
  75. OT_MEM8 = $00204001;
  76. OT_MEM16 = $00204002;
  77. OT_MEM32 = $00204004;
  78. OT_MEM64 = $00204008;
  79. OT_MEM80 = $00204010;
  80. { word/byte load/store }
  81. OT_AM2 = $00010000;
  82. { misc ld/st operations }
  83. OT_AM3 = $00020000;
  84. { multiple ld/st operations }
  85. OT_AM4 = $00040000;
  86. { co proc. ld/st operations }
  87. OT_AM5 = $00080000;
  88. OT_AMMASK = $000f0000;
  89. { IT instruction }
  90. OT_CONDITION = $00100000;
  91. OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
  92. OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
  93. OT_MEMORYAM4 = OT_MEMORY or OT_AM4;
  94. OT_MEMORYAM5 = OT_MEMORY or OT_AM5;
  95. OT_FPUREG = $01000000; { floating point stack registers }
  96. OT_REG_SMASK = $00070000; { special register operands: these may be treated differently }
  97. { a mask for the following }
  98. OT_MEM_OFFS = $00604000; { special type of EA }
  99. { simple [address] offset }
  100. OT_ONENESS = $00800000; { special type of immediate operand }
  101. { so UNITY == IMMEDIATE | ONENESS }
  102. OT_UNITY = $00802000; { for shift/rotate instructions }
  103. instabentries = {$i armnop.inc}
  104. maxinfolen = 5;
  105. IF_NONE = $00000000;
  106. IF_ARMMASK = $000F0000;
  107. IF_ARM7 = $00070000;
  108. IF_FPMASK = $00F00000;
  109. IF_FPA = $00100000;
  110. { if the instruction can change in a second pass }
  111. IF_PASS2 = longint($80000000);
  112. type
  113. TInsTabCache=array[TasmOp] of longint;
  114. PInsTabCache=^TInsTabCache;
  115. tinsentry = record
  116. opcode : tasmop;
  117. ops : byte;
  118. optypes : array[0..3] of longint;
  119. code : array[0..maxinfolen] of char;
  120. flags : longint;
  121. end;
  122. pinsentry=^tinsentry;
  123. const
  124. InsTab : array[0..instabentries-1] of TInsEntry={$i armtab.inc}
  125. var
  126. InsTabCache : PInsTabCache;
  127. type
  128. taicpu = class(tai_cpu_abstract_sym)
  129. oppostfix : TOpPostfix;
  130. roundingmode : troundingmode;
  131. procedure loadshifterop(opidx:longint;const so:tshifterop);
  132. procedure loadregset(opidx:longint; regsetregtype: tregistertype; regsetsubregtype: tsubregister; const s:tcpuregisterset);
  133. procedure loadconditioncode(opidx:longint;const cond:tasmcond);
  134. constructor op_none(op : tasmop);
  135. constructor op_reg(op : tasmop;_op1 : tregister);
  136. constructor op_ref(op : tasmop;const _op1 : treference);
  137. constructor op_const(op : tasmop;_op1 : longint);
  138. constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  139. constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  140. constructor op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  141. constructor op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
  142. constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  143. constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  144. constructor op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  145. constructor op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  146. constructor op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  147. constructor op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
  148. { SFM/LFM }
  149. constructor op_reg_const_ref(op : tasmop;_op1 : tregister;_op2 : aint;_op3 : treference);
  150. { ITxxx }
  151. constructor op_cond(op: tasmop; cond: tasmcond);
  152. { *M*LL }
  153. constructor op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  154. { this is for Jmp instructions }
  155. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  156. constructor op_sym(op : tasmop;_op1 : tasmsymbol);
  157. constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  158. constructor op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  159. constructor op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  160. function is_same_reg_move(regtype: Tregistertype):boolean; override;
  161. function spilling_get_operation_type(opnr: longint): topertype;override;
  162. { assembler }
  163. public
  164. { the next will reset all instructions that can change in pass 2 }
  165. procedure ResetPass1;override;
  166. procedure ResetPass2;override;
  167. function CheckIfValid:boolean;
  168. function GetString:string;
  169. function Pass1(objdata:TObjData):longint;override;
  170. procedure Pass2(objdata:TObjData);override;
  171. protected
  172. procedure ppuloadoper(ppufile:tcompilerppufile;var o:toper);override;
  173. procedure ppuwriteoper(ppufile:tcompilerppufile;const o:toper);override;
  174. procedure ppubuildderefimploper(var o:toper);override;
  175. procedure ppuderefoper(var o:toper);override;
  176. private
  177. { next fields are filled in pass1, so pass2 is faster }
  178. inssize : shortint;
  179. insoffset : longint;
  180. LastInsOffset : longint; { need to be public to be reset }
  181. insentry : PInsEntry;
  182. function InsEnd:longint;
  183. procedure create_ot(objdata:TObjData);
  184. function Matches(p:PInsEntry):longint;
  185. function calcsize(p:PInsEntry):shortint;
  186. procedure gencode(objdata:TObjData);
  187. function NeedAddrPrefix(opidx:byte):boolean;
  188. procedure Swapoperands;
  189. function FindInsentry(objdata:TObjData):boolean;
  190. end;
  191. tai_align = class(tai_align_abstract)
  192. { nothing to add }
  193. end;
  194. tai_thumb_func = class(tai)
  195. constructor create;
  196. end;
  197. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  198. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  199. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  200. function setroundingmode(i : taicpu;rm : troundingmode) : taicpu;
  201. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  202. { inserts pc relative symbols at places where they are reachable }
  203. procedure insertpcrelativedata(list,listtoinsert : TAsmList);
  204. { inserts .pdata section and dummy function prolog needed for arm-wince exception handling }
  205. procedure InsertPData;
  206. procedure InitAsm;
  207. procedure DoneAsm;
  208. implementation
  209. uses
  210. cutils,rgobj,itcpugas;
  211. procedure taicpu.loadshifterop(opidx:longint;const so:tshifterop);
  212. begin
  213. allocate_oper(opidx+1);
  214. with oper[opidx]^ do
  215. begin
  216. if typ<>top_shifterop then
  217. begin
  218. clearop(opidx);
  219. new(shifterop);
  220. end;
  221. shifterop^:=so;
  222. typ:=top_shifterop;
  223. if assigned(add_reg_instruction_hook) then
  224. add_reg_instruction_hook(self,shifterop^.rs);
  225. end;
  226. end;
  227. procedure taicpu.loadregset(opidx:longint; regsetregtype: tregistertype; regsetsubregtype: tsubregister; const s:tcpuregisterset);
  228. var
  229. i : byte;
  230. begin
  231. allocate_oper(opidx+1);
  232. with oper[opidx]^ do
  233. begin
  234. if typ<>top_regset then
  235. begin
  236. clearop(opidx);
  237. new(regset);
  238. end;
  239. regset^:=s;
  240. regtyp:=regsetregtype;
  241. subreg:=regsetsubregtype;
  242. typ:=top_regset;
  243. case regsetregtype of
  244. R_INTREGISTER:
  245. for i:=RS_R0 to RS_R15 do
  246. begin
  247. if assigned(add_reg_instruction_hook) and (i in regset^) then
  248. add_reg_instruction_hook(self,newreg(R_INTREGISTER,i,regsetsubregtype));
  249. end;
  250. R_MMREGISTER:
  251. { both RS_S0 and RS_D0 range from 0 to 31 }
  252. for i:=RS_D0 to RS_D31 do
  253. begin
  254. if assigned(add_reg_instruction_hook) and (i in regset^) then
  255. add_reg_instruction_hook(self,newreg(R_MMREGISTER,i,regsetsubregtype));
  256. end;
  257. end;
  258. end;
  259. end;
  260. procedure taicpu.loadconditioncode(opidx:longint;const cond:tasmcond);
  261. begin
  262. allocate_oper(opidx+1);
  263. with oper[opidx]^ do
  264. begin
  265. if typ<>top_conditioncode then
  266. clearop(opidx);
  267. cc:=cond;
  268. typ:=top_conditioncode;
  269. end;
  270. end;
  271. {*****************************************************************************
  272. taicpu Constructors
  273. *****************************************************************************}
  274. constructor taicpu.op_none(op : tasmop);
  275. begin
  276. inherited create(op);
  277. end;
  278. { for pld }
  279. constructor taicpu.op_ref(op : tasmop;const _op1 : treference);
  280. begin
  281. inherited create(op);
  282. ops:=1;
  283. loadref(0,_op1);
  284. end;
  285. constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
  286. begin
  287. inherited create(op);
  288. ops:=1;
  289. loadreg(0,_op1);
  290. end;
  291. constructor taicpu.op_const(op : tasmop;_op1 : longint);
  292. begin
  293. inherited create(op);
  294. ops:=1;
  295. loadconst(0,aint(_op1));
  296. end;
  297. constructor taicpu.op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  298. begin
  299. inherited create(op);
  300. ops:=2;
  301. loadreg(0,_op1);
  302. loadreg(1,_op2);
  303. end;
  304. constructor taicpu.op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  305. begin
  306. inherited create(op);
  307. ops:=2;
  308. loadreg(0,_op1);
  309. loadconst(1,aint(_op2));
  310. end;
  311. constructor taicpu.op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
  312. begin
  313. inherited create(op);
  314. ops:=2;
  315. loadref(0,_op1);
  316. loadregset(1,regtype,subreg,_op2);
  317. end;
  318. constructor taicpu.op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  319. begin
  320. inherited create(op);
  321. ops:=2;
  322. loadreg(0,_op1);
  323. loadref(1,_op2);
  324. end;
  325. constructor taicpu.op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  326. begin
  327. inherited create(op);
  328. ops:=3;
  329. loadreg(0,_op1);
  330. loadreg(1,_op2);
  331. loadreg(2,_op3);
  332. end;
  333. constructor taicpu.op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  334. begin
  335. inherited create(op);
  336. ops:=4;
  337. loadreg(0,_op1);
  338. loadreg(1,_op2);
  339. loadreg(2,_op3);
  340. loadreg(3,_op4);
  341. end;
  342. constructor taicpu.op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  343. begin
  344. inherited create(op);
  345. ops:=3;
  346. loadreg(0,_op1);
  347. loadreg(1,_op2);
  348. loadconst(2,aint(_op3));
  349. end;
  350. constructor taicpu.op_reg_const_ref(op : tasmop;_op1 : tregister;_op2 : aint;_op3 : treference);
  351. begin
  352. inherited create(op);
  353. ops:=3;
  354. loadreg(0,_op1);
  355. loadconst(1,_op2);
  356. loadref(2,_op3);
  357. end;
  358. constructor taicpu.op_cond(op: tasmop; cond: tasmcond);
  359. begin
  360. inherited create(op);
  361. ops:=0;
  362. condition := cond;
  363. end;
  364. constructor taicpu.op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  365. begin
  366. inherited create(op);
  367. ops:=3;
  368. loadreg(0,_op1);
  369. loadreg(1,_op2);
  370. loadsymbol(0,_op3,_op3ofs);
  371. end;
  372. constructor taicpu.op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  373. begin
  374. inherited create(op);
  375. ops:=3;
  376. loadreg(0,_op1);
  377. loadreg(1,_op2);
  378. loadref(2,_op3);
  379. end;
  380. constructor taicpu.op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  381. begin
  382. inherited create(op);
  383. ops:=3;
  384. loadreg(0,_op1);
  385. loadreg(1,_op2);
  386. loadshifterop(2,_op3);
  387. end;
  388. constructor taicpu.op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
  389. begin
  390. inherited create(op);
  391. ops:=4;
  392. loadreg(0,_op1);
  393. loadreg(1,_op2);
  394. loadreg(2,_op3);
  395. loadshifterop(3,_op4);
  396. end;
  397. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  398. begin
  399. inherited create(op);
  400. condition:=cond;
  401. ops:=1;
  402. loadsymbol(0,_op1,0);
  403. end;
  404. constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
  405. begin
  406. inherited create(op);
  407. ops:=1;
  408. loadsymbol(0,_op1,0);
  409. end;
  410. constructor taicpu.op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  411. begin
  412. inherited create(op);
  413. ops:=1;
  414. loadsymbol(0,_op1,_op1ofs);
  415. end;
  416. constructor taicpu.op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  417. begin
  418. inherited create(op);
  419. ops:=2;
  420. loadreg(0,_op1);
  421. loadsymbol(1,_op2,_op2ofs);
  422. end;
  423. constructor taicpu.op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  424. begin
  425. inherited create(op);
  426. ops:=2;
  427. loadsymbol(0,_op1,_op1ofs);
  428. loadref(1,_op2);
  429. end;
  430. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  431. begin
  432. { allow the register allocator to remove unnecessary moves }
  433. result:=(((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
  434. ((opcode=A_MVF) and (regtype = R_FPUREGISTER) and (oppostfix in [PF_None,PF_D])) or
  435. (((opcode=A_FCPYS) or (opcode=A_FCPYD)) and (regtype = R_MMREGISTER))
  436. ) and
  437. (condition=C_None) and
  438. (ops=2) and
  439. (oper[0]^.typ=top_reg) and
  440. (oper[1]^.typ=top_reg) and
  441. (oper[0]^.reg=oper[1]^.reg);
  442. end;
  443. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  444. var
  445. op: tasmop;
  446. begin
  447. case getregtype(r) of
  448. R_INTREGISTER :
  449. result:=taicpu.op_reg_ref(A_LDR,r,ref);
  450. R_FPUREGISTER :
  451. { use lfm because we don't know the current internal format
  452. and avoid exceptions
  453. }
  454. result:=taicpu.op_reg_const_ref(A_LFM,r,1,ref);
  455. R_MMREGISTER :
  456. begin
  457. case getsubreg(r) of
  458. R_SUBFD:
  459. op:=A_FLDD;
  460. R_SUBFS:
  461. op:=A_FLDS;
  462. else
  463. internalerror(2009112905);
  464. end;
  465. result:=taicpu.op_reg_ref(op,r,ref);
  466. end;
  467. else
  468. internalerror(200401041);
  469. end;
  470. end;
  471. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  472. var
  473. op: tasmop;
  474. begin
  475. case getregtype(r) of
  476. R_INTREGISTER :
  477. result:=taicpu.op_reg_ref(A_STR,r,ref);
  478. R_FPUREGISTER :
  479. { use sfm because we don't know the current internal format
  480. and avoid exceptions
  481. }
  482. result:=taicpu.op_reg_const_ref(A_SFM,r,1,ref);
  483. R_MMREGISTER :
  484. begin
  485. case getsubreg(r) of
  486. R_SUBFD:
  487. op:=A_FSTD;
  488. R_SUBFS:
  489. op:=A_FSTS;
  490. else
  491. internalerror(2009112904);
  492. end;
  493. result:=taicpu.op_reg_ref(op,r,ref);
  494. end;
  495. else
  496. internalerror(200401041);
  497. end;
  498. end;
  499. function taicpu.spilling_get_operation_type(opnr: longint): topertype;
  500. begin
  501. case opcode of
  502. A_ADC,A_ADD,A_AND,
  503. A_EOR,A_CLZ,
  504. A_LDR,A_LDRB,A_LDRBT,A_LDRH,A_LDRSB,
  505. A_LDRSH,A_LDRT,
  506. A_MOV,A_MVN,A_MLA,A_MUL,
  507. A_ORR,A_RSB,A_RSC,A_SBC,A_SUB,
  508. A_SWP,A_SWPB,
  509. A_LDF,A_FLT,A_FIX,
  510. A_ADF,A_DVF,A_FDV,A_FML,
  511. A_RFS,A_RFC,A_RDF,
  512. A_RMF,A_RPW,A_RSF,A_SUF,A_ABS,A_ACS,A_ASN,A_ATN,A_COS,
  513. A_EXP,A_LOG,A_LGN,A_MVF,A_MNF,A_FRD,A_MUF,A_POL,A_RND,A_SIN,A_SQT,A_TAN,
  514. A_LFM,
  515. A_FLDS,A_FLDD,
  516. A_FMRX,A_FMXR,A_FMSTAT,
  517. A_FMSR,A_FMRS,A_FMDRR,
  518. A_FCPYS,A_FCPYD,A_FCVTSD,A_FCVTDS,
  519. A_FABSS,A_FABSD,A_FSQRTS,A_FSQRTD,A_FMULS,A_FMULD,
  520. A_FADDS,A_FADDD,A_FSUBS,A_FSUBD,A_FDIVS,A_FDIVD,
  521. A_FMACS,A_FMACD,A_FMSCS,A_FMSCD,A_FNMACS,A_FNMACD,
  522. A_FNMSCS,A_FNMSCD,A_FNMULS,A_FNMULD,
  523. A_FMDHR,A_FMRDH,A_FMDLR,A_FMRDL,
  524. A_FNEGS,A_FNEGD,
  525. A_FSITOS,A_FSITOD,A_FTOSIS,A_FTOSID,
  526. A_FTOUIS,A_FTOUID,A_FUITOS,A_FUITOD:
  527. if opnr=0 then
  528. result:=operand_write
  529. else
  530. result:=operand_read;
  531. A_BIC,A_BKPT,A_B,A_BL,A_BLX,A_BX,
  532. A_CMN,A_CMP,A_TEQ,A_TST,
  533. A_CMF,A_CMFE,A_WFS,A_CNF,
  534. A_FCMPS,A_FCMPD,A_FCMPES,A_FCMPED,A_FCMPEZS,A_FCMPEZD,
  535. A_FCMPZS,A_FCMPZD:
  536. result:=operand_read;
  537. A_SMLAL,A_UMLAL:
  538. if opnr in [0,1] then
  539. result:=operand_readwrite
  540. else
  541. result:=operand_read;
  542. A_SMULL,A_UMULL,
  543. A_FMRRD:
  544. if opnr in [0,1] then
  545. result:=operand_write
  546. else
  547. result:=operand_read;
  548. A_STR,A_STRB,A_STRBT,
  549. A_STRH,A_STRT,A_STF,A_SFM,
  550. A_FSTS,A_FSTD:
  551. { important is what happens with the involved registers }
  552. if opnr=0 then
  553. result := operand_read
  554. else
  555. { check for pre/post indexed }
  556. result := operand_read;
  557. //Thumb2
  558. A_LSL, A_LSR, A_ROR, A_ASR, A_SDIV, A_UDIV,A_MOVT:
  559. if opnr in [0] then
  560. result:=operand_write
  561. else
  562. result:=operand_read;
  563. A_LDREX:
  564. if opnr in [0] then
  565. result:=operand_write
  566. else
  567. result:=operand_read;
  568. A_STREX:
  569. if opnr in [0,1,2] then
  570. result:=operand_write;
  571. else
  572. internalerror(200403151);
  573. end;
  574. end;
  575. procedure BuildInsTabCache;
  576. var
  577. i : longint;
  578. begin
  579. new(instabcache);
  580. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  581. i:=0;
  582. while (i<InsTabEntries) do
  583. begin
  584. if InsTabCache^[InsTab[i].Opcode]=-1 then
  585. InsTabCache^[InsTab[i].Opcode]:=i;
  586. inc(i);
  587. end;
  588. end;
  589. procedure InitAsm;
  590. begin
  591. if not assigned(instabcache) then
  592. BuildInsTabCache;
  593. end;
  594. procedure DoneAsm;
  595. begin
  596. if assigned(instabcache) then
  597. begin
  598. dispose(instabcache);
  599. instabcache:=nil;
  600. end;
  601. end;
  602. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  603. begin
  604. i.oppostfix:=pf;
  605. result:=i;
  606. end;
  607. function setroundingmode(i : taicpu;rm : troundingmode) : taicpu;
  608. begin
  609. i.roundingmode:=rm;
  610. result:=i;
  611. end;
  612. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  613. begin
  614. i.condition:=c;
  615. result:=i;
  616. end;
  617. Function SimpleGetNextInstruction(Current: tai; Var Next: tai): Boolean;
  618. Begin
  619. Current:=tai(Current.Next);
  620. While Assigned(Current) And (Current.typ In SkipInstr) Do
  621. Current:=tai(Current.Next);
  622. Next:=Current;
  623. If Assigned(Next) And Not(Next.typ In SkipInstr) Then
  624. Result:=True
  625. Else
  626. Begin
  627. Next:=Nil;
  628. Result:=False;
  629. End;
  630. End;
  631. (*
  632. function armconstequal(hp1,hp2: tai): boolean;
  633. begin
  634. result:=false;
  635. if hp1.typ<>hp2.typ then
  636. exit;
  637. case hp1.typ of
  638. tai_const:
  639. result:=
  640. (tai_const(hp2).sym=tai_const(hp).sym) and
  641. (tai_const(hp2).value=tai_const(hp).value) and
  642. (tai(hp2.previous).typ=ait_label);
  643. tai_const:
  644. result:=
  645. (tai_const(hp2).sym=tai_const(hp).sym) and
  646. (tai_const(hp2).value=tai_const(hp).value) and
  647. (tai(hp2.previous).typ=ait_label);
  648. end;
  649. end;
  650. *)
  651. procedure insertpcrelativedata(list,listtoinsert : TAsmList);
  652. var
  653. curinspos,
  654. penalty,
  655. lastinspos,
  656. { increased for every data element > 4 bytes inserted }
  657. extradataoffset,
  658. limit: longint;
  659. curop : longint;
  660. curtai : tai;
  661. curdatatai,hp,hp2 : tai;
  662. curdata : TAsmList;
  663. l : tasmlabel;
  664. doinsert,
  665. removeref : boolean;
  666. begin
  667. curdata:=TAsmList.create;
  668. lastinspos:=-1;
  669. curinspos:=0;
  670. extradataoffset:=0;
  671. limit:=1016;
  672. curtai:=tai(list.first);
  673. doinsert:=false;
  674. while assigned(curtai) do
  675. begin
  676. { instruction? }
  677. case curtai.typ of
  678. ait_instruction:
  679. begin
  680. { walk through all operand of the instruction }
  681. for curop:=0 to taicpu(curtai).ops-1 do
  682. begin
  683. { reference? }
  684. if (taicpu(curtai).oper[curop]^.typ=top_ref) then
  685. begin
  686. { pc relative symbol? }
  687. curdatatai:=tai(taicpu(curtai).oper[curop]^.ref^.symboldata);
  688. if assigned(curdatatai) and
  689. { move only if we're at the first reference of a label }
  690. (taicpu(curtai).oper[curop]^.ref^.offset=0) then
  691. begin
  692. { check if symbol already used. }
  693. { if yes, reuse the symbol }
  694. hp:=tai(curdatatai.next);
  695. removeref:=false;
  696. if assigned(hp) then
  697. begin
  698. case hp.typ of
  699. ait_const:
  700. begin
  701. if (tai_const(hp).consttype=aitconst_64bit) then
  702. inc(extradataoffset);
  703. end;
  704. ait_comp_64bit,
  705. ait_real_64bit:
  706. begin
  707. inc(extradataoffset);
  708. end;
  709. ait_real_80bit:
  710. begin
  711. inc(extradataoffset,2);
  712. end;
  713. end;
  714. if (hp.typ=ait_const) then
  715. begin
  716. hp2:=tai(curdata.first);
  717. while assigned(hp2) do
  718. begin
  719. { if armconstequal(hp2,hp) then }
  720. if (hp2.typ=ait_const) and (tai_const(hp2).sym=tai_const(hp).sym)
  721. and (tai_const(hp2).value=tai_const(hp).value) and (tai(hp2.previous).typ=ait_label)
  722. then
  723. begin
  724. with taicpu(curtai).oper[curop]^.ref^ do
  725. begin
  726. symboldata:=hp2.previous;
  727. symbol:=tai_label(hp2.previous).labsym;
  728. end;
  729. removeref:=true;
  730. break;
  731. end;
  732. hp2:=tai(hp2.next);
  733. end;
  734. end;
  735. end;
  736. { move or remove symbol reference }
  737. repeat
  738. hp:=tai(curdatatai.next);
  739. listtoinsert.remove(curdatatai);
  740. if removeref then
  741. curdatatai.free
  742. else
  743. curdata.concat(curdatatai);
  744. curdatatai:=hp;
  745. until (curdatatai=nil) or (curdatatai.typ=ait_label);
  746. if lastinspos=-1 then
  747. lastinspos:=curinspos;
  748. end;
  749. end;
  750. end;
  751. inc(curinspos);
  752. end;
  753. ait_const:
  754. begin
  755. inc(curinspos);
  756. if (tai_const(curtai).consttype=aitconst_64bit) then
  757. inc(curinspos);
  758. end;
  759. ait_real_32bit:
  760. begin
  761. inc(curinspos);
  762. end;
  763. ait_comp_64bit,
  764. ait_real_64bit:
  765. begin
  766. inc(curinspos,2);
  767. end;
  768. ait_real_80bit:
  769. begin
  770. inc(curinspos,3);
  771. end;
  772. end;
  773. { special case for case jump tables }
  774. if SimpleGetNextInstruction(curtai,hp) and
  775. (tai(hp).typ=ait_instruction) and
  776. (taicpu(hp).opcode=A_LDR) and
  777. (taicpu(hp).oper[0]^.typ=top_reg) and
  778. (taicpu(hp).oper[0]^.reg=NR_PC) then
  779. begin
  780. penalty:=1;
  781. hp:=tai(hp.next);
  782. while assigned(hp) and (hp.typ=ait_const) do
  783. begin
  784. inc(penalty);
  785. hp:=tai(hp.next);
  786. end;
  787. end
  788. else
  789. penalty:=0;
  790. { FLD/FST VFP instructions have a limit of +/- 1024, not 4096 }
  791. if SimpleGetNextInstruction(curtai,hp) and
  792. (tai(hp).typ=ait_instruction) and
  793. ((taicpu(hp).opcode=A_FLDS) or
  794. (taicpu(hp).opcode=A_FLDD)) then
  795. limit:=254;
  796. { don't miss an insert }
  797. doinsert:=doinsert or
  798. (not(curdata.empty) and
  799. (curinspos-lastinspos+penalty+extradataoffset>limit));
  800. { split only at real instructions else the test below fails }
  801. if doinsert and (curtai.typ=ait_instruction) and
  802. (
  803. { don't split loads of pc to lr and the following move }
  804. not(
  805. (taicpu(curtai).opcode=A_MOV) and
  806. (taicpu(curtai).oper[0]^.typ=top_reg) and
  807. (taicpu(curtai).oper[0]^.reg=NR_R14) and
  808. (taicpu(curtai).oper[1]^.typ=top_reg) and
  809. (taicpu(curtai).oper[1]^.reg=NR_PC)
  810. )
  811. ) then
  812. begin
  813. lastinspos:=-1;
  814. extradataoffset:=0;
  815. limit:=1016;
  816. doinsert:=false;
  817. hp:=tai(curtai.next);
  818. current_asmdata.getjumplabel(l);
  819. curdata.insert(taicpu.op_sym(A_B,l));
  820. curdata.concat(tai_label.create(l));
  821. list.insertlistafter(curtai,curdata);
  822. curtai:=hp;
  823. end
  824. else
  825. curtai:=tai(curtai.next);
  826. end;
  827. list.concatlist(curdata);
  828. curdata.free;
  829. end;
  830. procedure InsertPData;
  831. var
  832. prolog: TAsmList;
  833. begin
  834. prolog:=TAsmList.create;
  835. new_section(prolog,sec_code,'FPC_EH_PROLOG',sizeof(pint),secorder_begin);
  836. prolog.concat(Tai_const.Createname('_ARM_ExceptionHandler', 0));
  837. prolog.concat(Tai_const.Create_32bit(0));
  838. prolog.concat(Tai_symbol.Createname_global('FPC_EH_CODE_START',AT_DATA,0));
  839. { dummy function }
  840. prolog.concat(taicpu.op_reg_reg(A_MOV,NR_R15,NR_R14));
  841. current_asmdata.asmlists[al_start].insertList(prolog);
  842. prolog.Free;
  843. new_section(current_asmdata.asmlists[al_end],sec_pdata,'',sizeof(pint));
  844. current_asmdata.asmlists[al_end].concat(Tai_const.Createname('FPC_EH_CODE_START', 0));
  845. current_asmdata.asmlists[al_end].concat(Tai_const.Create_32bit(longint($ffffff01)));
  846. end;
  847. (*
  848. Floating point instruction format information, taken from the linux kernel
  849. ARM Floating Point Instruction Classes
  850. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  851. |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
  852. |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
  853. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  854. |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
  855. |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
  856. |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
  857. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  858. CPDT data transfer instructions
  859. LDF, STF, LFM (copro 2), SFM (copro 2)
  860. CPDO dyadic arithmetic instructions
  861. ADF, MUF, SUF, RSF, DVF, RDF,
  862. POW, RPW, RMF, FML, FDV, FRD, POL
  863. CPDO monadic arithmetic instructions
  864. MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
  865. SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
  866. CPRT joint arithmetic/data transfer instructions
  867. FIX (arithmetic followed by load/store)
  868. FLT (load/store followed by arithmetic)
  869. CMF, CNF CMFE, CNFE (comparisons)
  870. WFS, RFS (write/read floating point status register)
  871. WFC, RFC (write/read floating point control register)
  872. cond condition codes
  873. P pre/post index bit: 0 = postindex, 1 = preindex
  874. U up/down bit: 0 = stack grows down, 1 = stack grows up
  875. W write back bit: 1 = update base register (Rn)
  876. L load/store bit: 0 = store, 1 = load
  877. Rn base register
  878. Rd destination/source register
  879. Fd floating point destination register
  880. Fn floating point source register
  881. Fm floating point source register or floating point constant
  882. uv transfer length (TABLE 1)
  883. wx register count (TABLE 2)
  884. abcd arithmetic opcode (TABLES 3 & 4)
  885. ef destination size (rounding precision) (TABLE 5)
  886. gh rounding mode (TABLE 6)
  887. j dyadic/monadic bit: 0 = dyadic, 1 = monadic
  888. i constant bit: 1 = constant (TABLE 6)
  889. */
  890. /*
  891. TABLE 1
  892. +-------------------------+---+---+---------+---------+
  893. | Precision | u | v | FPSR.EP | length |
  894. +-------------------------+---+---+---------+---------+
  895. | Single | 0 | 0 | x | 1 words |
  896. | Double | 1 | 1 | x | 2 words |
  897. | Extended | 1 | 1 | x | 3 words |
  898. | Packed decimal | 1 | 1 | 0 | 3 words |
  899. | Expanded packed decimal | 1 | 1 | 1 | 4 words |
  900. +-------------------------+---+---+---------+---------+
  901. Note: x = don't care
  902. */
  903. /*
  904. TABLE 2
  905. +---+---+---------------------------------+
  906. | w | x | Number of registers to transfer |
  907. +---+---+---------------------------------+
  908. | 0 | 1 | 1 |
  909. | 1 | 0 | 2 |
  910. | 1 | 1 | 3 |
  911. | 0 | 0 | 4 |
  912. +---+---+---------------------------------+
  913. */
  914. /*
  915. TABLE 3: Dyadic Floating Point Opcodes
  916. +---+---+---+---+----------+-----------------------+-----------------------+
  917. | a | b | c | d | Mnemonic | Description | Operation |
  918. +---+---+---+---+----------+-----------------------+-----------------------+
  919. | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
  920. | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
  921. | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
  922. | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
  923. | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
  924. | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
  925. | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
  926. | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
  927. | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
  928. | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
  929. | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
  930. | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
  931. | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
  932. | 1 | 1 | 0 | 1 | | undefined instruction | trap |
  933. | 1 | 1 | 1 | 0 | | undefined instruction | trap |
  934. | 1 | 1 | 1 | 1 | | undefined instruction | trap |
  935. +---+---+---+---+----------+-----------------------+-----------------------+
  936. Note: POW, RPW, POL are deprecated, and are available for backwards
  937. compatibility only.
  938. */
  939. /*
  940. TABLE 4: Monadic Floating Point Opcodes
  941. +---+---+---+---+----------+-----------------------+-----------------------+
  942. | a | b | c | d | Mnemonic | Description | Operation |
  943. +---+---+---+---+----------+-----------------------+-----------------------+
  944. | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
  945. | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
  946. | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
  947. | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
  948. | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
  949. | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
  950. | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
  951. | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
  952. | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
  953. | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
  954. | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
  955. | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
  956. | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
  957. | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
  958. | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
  959. | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
  960. +---+---+---+---+----------+-----------------------+-----------------------+
  961. Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
  962. available for backwards compatibility only.
  963. */
  964. /*
  965. TABLE 5
  966. +-------------------------+---+---+
  967. | Rounding Precision | e | f |
  968. +-------------------------+---+---+
  969. | IEEE Single precision | 0 | 0 |
  970. | IEEE Double precision | 0 | 1 |
  971. | IEEE Extended precision | 1 | 0 |
  972. | undefined (trap) | 1 | 1 |
  973. +-------------------------+---+---+
  974. */
  975. /*
  976. TABLE 5
  977. +---------------------------------+---+---+
  978. | Rounding Mode | g | h |
  979. +---------------------------------+---+---+
  980. | Round to nearest (default) | 0 | 0 |
  981. | Round toward plus infinity | 0 | 1 |
  982. | Round toward negative infinity | 1 | 0 |
  983. | Round toward zero | 1 | 1 |
  984. +---------------------------------+---+---+
  985. *)
  986. function taicpu.GetString:string;
  987. var
  988. i : longint;
  989. s : string;
  990. addsize : boolean;
  991. begin
  992. s:='['+gas_op2str[opcode];
  993. for i:=0 to ops-1 do
  994. begin
  995. with oper[i]^ do
  996. begin
  997. if i=0 then
  998. s:=s+' '
  999. else
  1000. s:=s+',';
  1001. { type }
  1002. addsize:=false;
  1003. if (ot and OT_VREG)=OT_VREG then
  1004. s:=s+'vreg'
  1005. else
  1006. if (ot and OT_FPUREG)=OT_FPUREG then
  1007. s:=s+'fpureg'
  1008. else
  1009. if (ot and OT_REGISTER)=OT_REGISTER then
  1010. begin
  1011. s:=s+'reg';
  1012. addsize:=true;
  1013. end
  1014. else
  1015. if (ot and OT_REGLIST)=OT_REGLIST then
  1016. begin
  1017. s:=s+'reglist';
  1018. addsize:=false;
  1019. end
  1020. else
  1021. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  1022. begin
  1023. s:=s+'imm';
  1024. addsize:=true;
  1025. end
  1026. else
  1027. if (ot and OT_MEMORY)=OT_MEMORY then
  1028. begin
  1029. s:=s+'mem';
  1030. addsize:=true;
  1031. if (ot and OT_AM2)<>0 then
  1032. s:=s+' am2 ';
  1033. end
  1034. else
  1035. s:=s+'???';
  1036. { size }
  1037. if addsize then
  1038. begin
  1039. if (ot and OT_BITS8)<>0 then
  1040. s:=s+'8'
  1041. else
  1042. if (ot and OT_BITS16)<>0 then
  1043. s:=s+'24'
  1044. else
  1045. if (ot and OT_BITS32)<>0 then
  1046. s:=s+'32'
  1047. else
  1048. if (ot and OT_BITSSHIFTER)<>0 then
  1049. s:=s+'shifter'
  1050. else
  1051. s:=s+'??';
  1052. { signed }
  1053. if (ot and OT_SIGNED)<>0 then
  1054. s:=s+'s';
  1055. end;
  1056. end;
  1057. end;
  1058. GetString:=s+']';
  1059. end;
  1060. procedure taicpu.ResetPass1;
  1061. begin
  1062. { we need to reset everything here, because the choosen insentry
  1063. can be invalid for a new situation where the previously optimized
  1064. insentry is not correct }
  1065. InsEntry:=nil;
  1066. InsSize:=0;
  1067. LastInsOffset:=-1;
  1068. end;
  1069. procedure taicpu.ResetPass2;
  1070. begin
  1071. { we are here in a second pass, check if the instruction can be optimized }
  1072. if assigned(InsEntry) and
  1073. ((InsEntry^.flags and IF_PASS2)<>0) then
  1074. begin
  1075. InsEntry:=nil;
  1076. InsSize:=0;
  1077. end;
  1078. LastInsOffset:=-1;
  1079. end;
  1080. function taicpu.CheckIfValid:boolean;
  1081. begin
  1082. Result:=False; { unimplemented }
  1083. end;
  1084. function taicpu.Pass1(objdata:TObjData):longint;
  1085. var
  1086. ldr2op : array[PF_B..PF_T] of tasmop = (
  1087. A_LDRB,A_LDRSB,A_LDRBT,A_LDRH,A_LDRSH,A_LDRT);
  1088. str2op : array[PF_B..PF_T] of tasmop = (
  1089. A_STRB,A_None,A_STRBT,A_STRH,A_None,A_STRT);
  1090. begin
  1091. Pass1:=0;
  1092. { Save the old offset and set the new offset }
  1093. InsOffset:=ObjData.CurrObjSec.Size;
  1094. { Error? }
  1095. if (Insentry=nil) and (InsSize=-1) then
  1096. exit;
  1097. { set the file postion }
  1098. current_filepos:=fileinfo;
  1099. { tranlate LDR+postfix to complete opcode }
  1100. if (opcode=A_LDR) and (oppostfix<>PF_None) then
  1101. begin
  1102. if (oppostfix in [low(ldr2op)..high(ldr2op)]) then
  1103. opcode:=ldr2op[oppostfix]
  1104. else
  1105. internalerror(2005091001);
  1106. if opcode=A_None then
  1107. internalerror(2005091004);
  1108. { postfix has been added to opcode }
  1109. oppostfix:=PF_None;
  1110. end
  1111. else if (opcode=A_STR) and (oppostfix<>PF_None) then
  1112. begin
  1113. if (oppostfix in [low(str2op)..high(str2op)]) then
  1114. opcode:=str2op[oppostfix]
  1115. else
  1116. internalerror(2005091002);
  1117. if opcode=A_None then
  1118. internalerror(2005091003);
  1119. { postfix has been added to opcode }
  1120. oppostfix:=PF_None;
  1121. end;
  1122. { Get InsEntry }
  1123. if FindInsEntry(objdata) then
  1124. begin
  1125. InsSize:=4;
  1126. LastInsOffset:=InsOffset;
  1127. Pass1:=InsSize;
  1128. exit;
  1129. end;
  1130. LastInsOffset:=-1;
  1131. end;
  1132. procedure taicpu.Pass2(objdata:TObjData);
  1133. begin
  1134. { error in pass1 ? }
  1135. if insentry=nil then
  1136. exit;
  1137. current_filepos:=fileinfo;
  1138. { Generate the instruction }
  1139. GenCode(objdata);
  1140. end;
  1141. procedure taicpu.ppuloadoper(ppufile:tcompilerppufile;var o:toper);
  1142. begin
  1143. end;
  1144. procedure taicpu.ppuwriteoper(ppufile:tcompilerppufile;const o:toper);
  1145. begin
  1146. end;
  1147. procedure taicpu.ppubuildderefimploper(var o:toper);
  1148. begin
  1149. end;
  1150. procedure taicpu.ppuderefoper(var o:toper);
  1151. begin
  1152. end;
  1153. function taicpu.InsEnd:longint;
  1154. begin
  1155. Result:=0; { unimplemented }
  1156. end;
  1157. procedure taicpu.create_ot(objdata:TObjData);
  1158. var
  1159. i,l,relsize : longint;
  1160. dummy : byte;
  1161. currsym : TObjSymbol;
  1162. begin
  1163. if ops=0 then
  1164. exit;
  1165. { update oper[].ot field }
  1166. for i:=0 to ops-1 do
  1167. with oper[i]^ do
  1168. begin
  1169. case typ of
  1170. top_regset:
  1171. begin
  1172. ot:=OT_REGLIST;
  1173. end;
  1174. top_reg :
  1175. begin
  1176. case getregtype(reg) of
  1177. R_INTREGISTER:
  1178. ot:=OT_REG32 or OT_SHIFTEROP;
  1179. R_FPUREGISTER:
  1180. ot:=OT_FPUREG;
  1181. else
  1182. internalerror(2005090901);
  1183. end;
  1184. end;
  1185. top_ref :
  1186. begin
  1187. if ref^.refaddr=addr_no then
  1188. begin
  1189. { create ot field }
  1190. { we should get the size here dependend on the
  1191. instruction }
  1192. if (ot and OT_SIZE_MASK)=0 then
  1193. ot:=OT_MEMORY or OT_BITS32
  1194. else
  1195. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  1196. if (ref^.base=NR_NO) and (ref^.index=NR_NO) then
  1197. ot:=ot or OT_MEM_OFFS;
  1198. { if we need to fix a reference, we do it here }
  1199. { pc relative addressing }
  1200. if (ref^.base=NR_NO) and
  1201. (ref^.index=NR_NO) and
  1202. (ref^.shiftmode=SM_None)
  1203. { at least we should check if the destination symbol
  1204. is in a text section }
  1205. { and
  1206. (ref^.symbol^.owner="text") } then
  1207. ref^.base:=NR_PC;
  1208. { determine possible address modes }
  1209. if (ref^.base<>NR_NO) and
  1210. (
  1211. (
  1212. (ref^.index=NR_NO) and
  1213. (ref^.shiftmode=SM_None) and
  1214. (ref^.offset>=-4097) and
  1215. (ref^.offset<=4097)
  1216. ) or
  1217. (
  1218. (ref^.shiftmode=SM_None) and
  1219. (ref^.offset=0)
  1220. ) or
  1221. (
  1222. (ref^.index<>NR_NO) and
  1223. (ref^.shiftmode<>SM_None) and
  1224. (ref^.shiftimm<=31) and
  1225. (ref^.offset=0)
  1226. )
  1227. ) then
  1228. ot:=ot or OT_AM2;
  1229. if (ref^.index<>NR_NO) and
  1230. (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
  1231. (
  1232. (ref^.base=NR_NO) and
  1233. (ref^.shiftmode=SM_None) and
  1234. (ref^.offset=0)
  1235. ) then
  1236. ot:=ot or OT_AM4;
  1237. end
  1238. else
  1239. begin
  1240. l:=ref^.offset;
  1241. currsym:=ObjData.symbolref(ref^.symbol);
  1242. if assigned(currsym) then
  1243. inc(l,currsym.address);
  1244. relsize:=(InsOffset+2)-l;
  1245. if (relsize<-33554428) or (relsize>33554428) then
  1246. ot:=OT_IMM32
  1247. else
  1248. ot:=OT_IMM24;
  1249. end;
  1250. end;
  1251. top_local :
  1252. begin
  1253. { we should get the size here dependend on the
  1254. instruction }
  1255. if (ot and OT_SIZE_MASK)=0 then
  1256. ot:=OT_MEMORY or OT_BITS32
  1257. else
  1258. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  1259. end;
  1260. top_const :
  1261. begin
  1262. ot:=OT_IMMEDIATE;
  1263. if is_shifter_const(val,dummy) then
  1264. ot:=OT_IMMSHIFTER
  1265. else
  1266. ot:=OT_IMM32
  1267. end;
  1268. top_none :
  1269. begin
  1270. { generated when there was an error in the
  1271. assembler reader. It never happends when generating
  1272. assembler }
  1273. end;
  1274. top_shifterop:
  1275. begin
  1276. ot:=OT_SHIFTEROP;
  1277. end;
  1278. else
  1279. internalerror(200402261);
  1280. end;
  1281. end;
  1282. end;
  1283. function taicpu.Matches(p:PInsEntry):longint;
  1284. { * IF_SM stands for Size Match: any operand whose size is not
  1285. * explicitly specified by the template is `really' intended to be
  1286. * the same size as the first size-specified operand.
  1287. * Non-specification is tolerated in the input instruction, but
  1288. * _wrong_ specification is not.
  1289. *
  1290. * IF_SM2 invokes Size Match on only the first _two_ operands, for
  1291. * three-operand instructions such as SHLD: it implies that the
  1292. * first two operands must match in size, but that the third is
  1293. * required to be _unspecified_.
  1294. *
  1295. * IF_SB invokes Size Byte: operands with unspecified size in the
  1296. * template are really bytes, and so no non-byte specification in
  1297. * the input instruction will be tolerated. IF_SW similarly invokes
  1298. * Size Word, and IF_SD invokes Size Doubleword.
  1299. *
  1300. * (The default state if neither IF_SM nor IF_SM2 is specified is
  1301. * that any operand with unspecified size in the template is
  1302. * required to have unspecified size in the instruction too...)
  1303. }
  1304. var
  1305. i{,j,asize,oprs} : longint;
  1306. {siz : array[0..3] of longint;}
  1307. begin
  1308. Matches:=100;
  1309. writeln(getstring,'---');
  1310. { Check the opcode and operands }
  1311. if (p^.opcode<>opcode) or (p^.ops<>ops) then
  1312. begin
  1313. Matches:=0;
  1314. exit;
  1315. end;
  1316. { Check that no spurious colons or TOs are present }
  1317. for i:=0 to p^.ops-1 do
  1318. if (oper[i]^.ot and (not p^.optypes[i]) and (OT_COLON or OT_TO))<>0 then
  1319. begin
  1320. Matches:=0;
  1321. exit;
  1322. end;
  1323. { Check that the operand flags all match up }
  1324. for i:=0 to p^.ops-1 do
  1325. begin
  1326. if ((p^.optypes[i] and (not oper[i]^.ot)) or
  1327. ((p^.optypes[i] and OT_SIZE_MASK) and
  1328. ((p^.optypes[i] xor oper[i]^.ot) and OT_SIZE_MASK)))<>0 then
  1329. begin
  1330. if ((p^.optypes[i] and (not oper[i]^.ot) and OT_NON_SIZE) or
  1331. (oper[i]^.ot and OT_SIZE_MASK))<>0 then
  1332. begin
  1333. Matches:=0;
  1334. exit;
  1335. end
  1336. else
  1337. Matches:=1;
  1338. end;
  1339. end;
  1340. { check postfixes:
  1341. the existance of a certain postfix requires a
  1342. particular code }
  1343. { update condition flags
  1344. or floating point single }
  1345. if (oppostfix=PF_S) and
  1346. not(p^.code[0] in [#$04]) then
  1347. begin
  1348. Matches:=0;
  1349. exit;
  1350. end;
  1351. { floating point size }
  1352. if (oppostfix in [PF_D,PF_E,PF_P,PF_EP]) and
  1353. not(p^.code[0] in []) then
  1354. begin
  1355. Matches:=0;
  1356. exit;
  1357. end;
  1358. { multiple load/store address modes }
  1359. if (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
  1360. not(p^.code[0] in [
  1361. // ldr,str,ldrb,strb
  1362. #$17,
  1363. // stm,ldm
  1364. #$26
  1365. ]) then
  1366. begin
  1367. Matches:=0;
  1368. exit;
  1369. end;
  1370. { we shouldn't see any opsize prefixes here }
  1371. if (oppostfix in [PF_B,PF_SB,PF_BT,PF_H,PF_SH,PF_T]) then
  1372. begin
  1373. Matches:=0;
  1374. exit;
  1375. end;
  1376. if (roundingmode<>RM_None) and not(p^.code[0] in []) then
  1377. begin
  1378. Matches:=0;
  1379. exit;
  1380. end;
  1381. { Check operand sizes }
  1382. { as default an untyped size can get all the sizes, this is different
  1383. from nasm, but else we need to do a lot checking which opcodes want
  1384. size or not with the automatic size generation }
  1385. (*
  1386. asize:=longint($ffffffff);
  1387. if (p^.flags and IF_SB)<>0 then
  1388. asize:=OT_BITS8
  1389. else if (p^.flags and IF_SW)<>0 then
  1390. asize:=OT_BITS16
  1391. else if (p^.flags and IF_SD)<>0 then
  1392. asize:=OT_BITS32;
  1393. if (p^.flags and IF_ARMASK)<>0 then
  1394. begin
  1395. siz[0]:=0;
  1396. siz[1]:=0;
  1397. siz[2]:=0;
  1398. if (p^.flags and IF_AR0)<>0 then
  1399. siz[0]:=asize
  1400. else if (p^.flags and IF_AR1)<>0 then
  1401. siz[1]:=asize
  1402. else if (p^.flags and IF_AR2)<>0 then
  1403. siz[2]:=asize;
  1404. end
  1405. else
  1406. begin
  1407. { we can leave because the size for all operands is forced to be
  1408. the same
  1409. but not if IF_SB IF_SW or IF_SD is set PM }
  1410. if asize=-1 then
  1411. exit;
  1412. siz[0]:=asize;
  1413. siz[1]:=asize;
  1414. siz[2]:=asize;
  1415. end;
  1416. if (p^.flags and (IF_SM or IF_SM2))<>0 then
  1417. begin
  1418. if (p^.flags and IF_SM2)<>0 then
  1419. oprs:=2
  1420. else
  1421. oprs:=p^.ops;
  1422. for i:=0 to oprs-1 do
  1423. if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
  1424. begin
  1425. for j:=0 to oprs-1 do
  1426. siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
  1427. break;
  1428. end;
  1429. end
  1430. else
  1431. oprs:=2;
  1432. { Check operand sizes }
  1433. for i:=0 to p^.ops-1 do
  1434. begin
  1435. if ((p^.optypes[i] and OT_SIZE_MASK)=0) and
  1436. ((oper[i]^.ot and OT_SIZE_MASK and (not siz[i]))<>0) and
  1437. { Immediates can always include smaller size }
  1438. ((oper[i]^.ot and OT_IMMEDIATE)=0) and
  1439. (((p^.optypes[i] and OT_SIZE_MASK) or siz[i])<(oper[i]^.ot and OT_SIZE_MASK)) then
  1440. Matches:=2;
  1441. end;
  1442. *)
  1443. end;
  1444. function taicpu.calcsize(p:PInsEntry):shortint;
  1445. begin
  1446. result:=4;
  1447. end;
  1448. function taicpu.NeedAddrPrefix(opidx:byte):boolean;
  1449. begin
  1450. Result:=False; { unimplemented }
  1451. end;
  1452. procedure taicpu.Swapoperands;
  1453. begin
  1454. end;
  1455. function taicpu.FindInsentry(objdata:TObjData):boolean;
  1456. var
  1457. i : longint;
  1458. begin
  1459. result:=false;
  1460. { Things which may only be done once, not when a second pass is done to
  1461. optimize }
  1462. if (Insentry=nil) or ((InsEntry^.flags and IF_PASS2)<>0) then
  1463. begin
  1464. { create the .ot fields }
  1465. create_ot(objdata);
  1466. { set the file postion }
  1467. current_filepos:=fileinfo;
  1468. end
  1469. else
  1470. begin
  1471. { we've already an insentry so it's valid }
  1472. result:=true;
  1473. exit;
  1474. end;
  1475. { Lookup opcode in the table }
  1476. InsSize:=-1;
  1477. i:=instabcache^[opcode];
  1478. if i=-1 then
  1479. begin
  1480. Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
  1481. exit;
  1482. end;
  1483. insentry:=@instab[i];
  1484. while (insentry^.opcode=opcode) do
  1485. begin
  1486. if matches(insentry)=100 then
  1487. begin
  1488. result:=true;
  1489. exit;
  1490. end;
  1491. inc(i);
  1492. insentry:=@instab[i];
  1493. end;
  1494. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1495. { No instruction found, set insentry to nil and inssize to -1 }
  1496. insentry:=nil;
  1497. inssize:=-1;
  1498. end;
  1499. procedure taicpu.gencode(objdata:TObjData);
  1500. var
  1501. bytes : dword;
  1502. i_field : byte;
  1503. procedure setshifterop(op : byte);
  1504. begin
  1505. case oper[op]^.typ of
  1506. top_const:
  1507. begin
  1508. i_field:=1;
  1509. bytes:=bytes or dword(oper[op]^.val and $fff);
  1510. end;
  1511. top_reg:
  1512. begin
  1513. i_field:=0;
  1514. bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16);
  1515. { does a real shifter op follow? }
  1516. if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then
  1517. begin
  1518. end;
  1519. end;
  1520. else
  1521. internalerror(2005091103);
  1522. end;
  1523. end;
  1524. begin
  1525. bytes:=$0;
  1526. { evaluate and set condition code }
  1527. { condition code allowed? }
  1528. { setup rest of the instruction }
  1529. case insentry^.code[0] of
  1530. #$08:
  1531. begin
  1532. { set instruction code }
  1533. bytes:=bytes or (ord(insentry^.code[1]) shl 26);
  1534. bytes:=bytes or (ord(insentry^.code[2]) shl 21);
  1535. { set destination }
  1536. bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
  1537. { create shifter op }
  1538. setshifterop(1);
  1539. { set i field }
  1540. bytes:=bytes or (i_field shl 25);
  1541. { set s if necessary }
  1542. if oppostfix=PF_S then
  1543. bytes:=bytes or (1 shl 20);
  1544. end;
  1545. #$ff:
  1546. internalerror(2005091101);
  1547. else
  1548. internalerror(2005091102);
  1549. end;
  1550. { we're finished, write code }
  1551. objdata.writebytes(bytes,sizeof(bytes));
  1552. end;
  1553. {$ifdef dummy}
  1554. (*
  1555. static void gencode (long segment, long offset, int bits,
  1556. insn *ins, char *codes, long insn_end)
  1557. {
  1558. int has_S_code; /* S - setflag */
  1559. int has_B_code; /* B - setflag */
  1560. int has_T_code; /* T - setflag */
  1561. int has_W_code; /* ! => W flag */
  1562. int has_F_code; /* ^ => S flag */
  1563. int keep;
  1564. unsigned char c;
  1565. unsigned char bytes[4];
  1566. long data, size;
  1567. static int cc_code[] = /* bit pattern of cc */
  1568. { /* order as enum in */
  1569. 0x0E, 0x03, 0x02, 0x00, /* nasm.h */
  1570. 0x0A, 0x0C, 0x08, 0x0D,
  1571. 0x09, 0x0B, 0x04, 0x01,
  1572. 0x05, 0x07, 0x06,
  1573. };
  1574. #ifdef DEBUG
  1575. static char *CC[] =
  1576. { /* condition code names */
  1577. "AL", "CC", "CS", "EQ",
  1578. "GE", "GT", "HI", "LE",
  1579. "LS", "LT", "MI", "NE",
  1580. "PL", "VC", "VS", "",
  1581. "S"
  1582. };
  1583. has_S_code = (ins->condition & C_SSETFLAG);
  1584. has_B_code = (ins->condition & C_BSETFLAG);
  1585. has_T_code = (ins->condition & C_TSETFLAG);
  1586. has_W_code = (ins->condition & C_EXSETFLAG);
  1587. has_F_code = (ins->condition & C_FSETFLAG);
  1588. ins->condition = (ins->condition & 0x0F);
  1589. if (rt_debug)
  1590. {
  1591. printf ("gencode: instruction: %s%s", insn_names[ins->opcode],
  1592. CC[ins->condition & 0x0F]);
  1593. if (has_S_code)
  1594. printf ("S");
  1595. if (has_B_code)
  1596. printf ("B");
  1597. if (has_T_code)
  1598. printf ("T");
  1599. if (has_W_code)
  1600. printf ("!");
  1601. if (has_F_code)
  1602. printf ("^");
  1603. printf ("\n");
  1604. c = *codes;
  1605. printf (" (%d) decode - '0x%02X'\n", ins->operands, c);
  1606. bytes[0] = 0xB;
  1607. bytes[1] = 0xE;
  1608. bytes[2] = 0xE;
  1609. bytes[3] = 0xF;
  1610. }
  1611. // First condition code in upper nibble
  1612. if (ins->condition < C_NONE)
  1613. {
  1614. c = cc_code[ins->condition] << 4;
  1615. }
  1616. else
  1617. {
  1618. c = cc_code[C_AL] << 4; // is often ALWAYS but not always
  1619. }
  1620. switch (keep = *codes)
  1621. {
  1622. case 1:
  1623. // B, BL
  1624. ++codes;
  1625. c |= *codes++;
  1626. bytes[0] = c;
  1627. if (ins->oprs[0].segment != segment)
  1628. {
  1629. // fais une relocation
  1630. c = 1;
  1631. data = 0; // Let the linker locate ??
  1632. }
  1633. else
  1634. {
  1635. c = 0;
  1636. data = ins->oprs[0].offset - (offset + 8);
  1637. if (data % 4)
  1638. {
  1639. errfunc (ERR_NONFATAL, "offset not aligned on 4 bytes");
  1640. }
  1641. }
  1642. if (data >= 0x1000)
  1643. {
  1644. errfunc (ERR_NONFATAL, "too long offset");
  1645. }
  1646. data = data >> 2;
  1647. bytes[1] = (data >> 16) & 0xFF;
  1648. bytes[2] = (data >> 8) & 0xFF;
  1649. bytes[3] = (data ) & 0xFF;
  1650. if (c == 1)
  1651. {
  1652. // out (offset, segment, &bytes[0], OUT_RAWDATA+1, NO_SEG, NO_SEG);
  1653. out (offset, segment, &bytes[0], OUT_REL3ADR+4, ins->oprs[0].segment, NO_SEG);
  1654. }
  1655. else
  1656. {
  1657. out (offset, segment, &bytes[0], OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1658. }
  1659. return;
  1660. case 2:
  1661. // SWI
  1662. ++codes;
  1663. c |= *codes++;
  1664. bytes[0] = c;
  1665. data = ins->oprs[0].offset;
  1666. bytes[1] = (data >> 16) & 0xFF;
  1667. bytes[2] = (data >> 8) & 0xFF;
  1668. bytes[3] = (data) & 0xFF;
  1669. out (offset, segment, &bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1670. return;
  1671. case 3:
  1672. // BX
  1673. ++codes;
  1674. c |= *codes++;
  1675. bytes[0] = c;
  1676. bytes[1] = *codes++;
  1677. bytes[2] = *codes++;
  1678. bytes[3] = *codes++;
  1679. c = regval (&ins->oprs[0],1);
  1680. if (c == 15) // PC
  1681. {
  1682. errfunc (ERR_WARNING, "'BX' with R15 has undefined behaviour");
  1683. }
  1684. else if (c > 15)
  1685. {
  1686. errfunc (ERR_NONFATAL, "Illegal register specified for 'BX'");
  1687. }
  1688. bytes[3] |= (c & 0x0F);
  1689. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1690. return;
  1691. case 4: // AND Rd,Rn,Rm
  1692. case 5: // AND Rd,Rn,Rm,<shift>Rs
  1693. case 6: // AND Rd,Rn,Rm,<shift>imm
  1694. case 7: // AND Rd,Rn,<shift>imm
  1695. ++codes;
  1696. #ifdef DEBUG
  1697. if (rt_debug)
  1698. {
  1699. printf (" decode - '0x%02X'\n", keep);
  1700. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  1701. }
  1702. #endif
  1703. bytes[0] = c | *codes;
  1704. ++codes;
  1705. bytes[1] = *codes;
  1706. if (has_S_code)
  1707. bytes[1] |= 0x10;
  1708. c = regval (&ins->oprs[1],1);
  1709. // Rn in low nibble
  1710. bytes[1] |= c;
  1711. // Rd in high nibble
  1712. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1713. if (keep != 7)
  1714. {
  1715. // Rm in low nibble
  1716. bytes[3] = regval (&ins->oprs[2],1);
  1717. }
  1718. // Shifts if any
  1719. if (keep == 5 || keep == 6)
  1720. {
  1721. // Shift in bytes 2 and 3
  1722. if (keep == 5)
  1723. {
  1724. // Rs
  1725. c = regval (&ins->oprs[3],1);
  1726. bytes[2] |= c;
  1727. c = 0x10; // Set bit 4 in byte[3]
  1728. }
  1729. if (keep == 6)
  1730. {
  1731. c = (ins->oprs[3].offset) & 0x1F;
  1732. // #imm
  1733. bytes[2] |= c >> 1;
  1734. if (c & 0x01)
  1735. {
  1736. bytes[3] |= 0x80;
  1737. }
  1738. c = 0; // Clr bit 4 in byte[3]
  1739. }
  1740. // <shift>
  1741. c |= shiftval (&ins->oprs[3]) << 5;
  1742. bytes[3] |= c;
  1743. }
  1744. // reg,reg,imm
  1745. if (keep == 7)
  1746. {
  1747. int shimm;
  1748. shimm = imm_shift (ins->oprs[2].offset);
  1749. if (shimm == -1)
  1750. {
  1751. errfunc (ERR_NONFATAL, "cannot create that constant");
  1752. }
  1753. bytes[3] = shimm & 0xFF;
  1754. bytes[2] |= (shimm & 0xF00) >> 8;
  1755. }
  1756. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1757. return;
  1758. case 8: // MOV Rd,Rm
  1759. case 9: // MOV Rd,Rm,<shift>Rs
  1760. case 0xA: // MOV Rd,Rm,<shift>imm
  1761. case 0xB: // MOV Rd,<shift>imm
  1762. ++codes;
  1763. #ifdef DEBUG
  1764. if (rt_debug)
  1765. {
  1766. printf (" decode - '0x%02X'\n", keep);
  1767. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  1768. }
  1769. #endif
  1770. bytes[0] = c | *codes;
  1771. ++codes;
  1772. bytes[1] = *codes;
  1773. if (has_S_code)
  1774. bytes[1] |= 0x10;
  1775. // Rd in high nibble
  1776. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1777. if (keep != 0x0B)
  1778. {
  1779. // Rm in low nibble
  1780. bytes[3] = regval (&ins->oprs[1],1);
  1781. }
  1782. // Shifts if any
  1783. if (keep == 0x09 || keep == 0x0A)
  1784. {
  1785. // Shift in bytes 2 and 3
  1786. if (keep == 0x09)
  1787. {
  1788. // Rs
  1789. c = regval (&ins->oprs[2],1);
  1790. bytes[2] |= c;
  1791. c = 0x10; // Set bit 4 in byte[3]
  1792. }
  1793. if (keep == 0x0A)
  1794. {
  1795. c = (ins->oprs[2].offset) & 0x1F;
  1796. // #imm
  1797. bytes[2] |= c >> 1;
  1798. if (c & 0x01)
  1799. {
  1800. bytes[3] |= 0x80;
  1801. }
  1802. c = 0; // Clr bit 4 in byte[3]
  1803. }
  1804. // <shift>
  1805. c |= shiftval (&ins->oprs[2]) << 5;
  1806. bytes[3] |= c;
  1807. }
  1808. // reg,imm
  1809. if (keep == 0x0B)
  1810. {
  1811. int shimm;
  1812. shimm = imm_shift (ins->oprs[1].offset);
  1813. if (shimm == -1)
  1814. {
  1815. errfunc (ERR_NONFATAL, "cannot create that constant");
  1816. }
  1817. bytes[3] = shimm & 0xFF;
  1818. bytes[2] |= (shimm & 0xF00) >> 8;
  1819. }
  1820. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1821. return;
  1822. case 0xC: // CMP Rn,Rm
  1823. case 0xD: // CMP Rn,Rm,<shift>Rs
  1824. case 0xE: // CMP Rn,Rm,<shift>imm
  1825. case 0xF: // CMP Rn,<shift>imm
  1826. ++codes;
  1827. bytes[0] = c | *codes++;
  1828. bytes[1] = *codes;
  1829. // Implicit S code
  1830. bytes[1] |= 0x10;
  1831. c = regval (&ins->oprs[0],1);
  1832. // Rn in low nibble
  1833. bytes[1] |= c;
  1834. // No destination
  1835. bytes[2] = 0;
  1836. if (keep != 0x0B)
  1837. {
  1838. // Rm in low nibble
  1839. bytes[3] = regval (&ins->oprs[1],1);
  1840. }
  1841. // Shifts if any
  1842. if (keep == 0x0D || keep == 0x0E)
  1843. {
  1844. // Shift in bytes 2 and 3
  1845. if (keep == 0x0D)
  1846. {
  1847. // Rs
  1848. c = regval (&ins->oprs[2],1);
  1849. bytes[2] |= c;
  1850. c = 0x10; // Set bit 4 in byte[3]
  1851. }
  1852. if (keep == 0x0E)
  1853. {
  1854. c = (ins->oprs[2].offset) & 0x1F;
  1855. // #imm
  1856. bytes[2] |= c >> 1;
  1857. if (c & 0x01)
  1858. {
  1859. bytes[3] |= 0x80;
  1860. }
  1861. c = 0; // Clr bit 4 in byte[3]
  1862. }
  1863. // <shift>
  1864. c |= shiftval (&ins->oprs[2]) << 5;
  1865. bytes[3] |= c;
  1866. }
  1867. // reg,imm
  1868. if (keep == 0x0F)
  1869. {
  1870. int shimm;
  1871. shimm = imm_shift (ins->oprs[1].offset);
  1872. if (shimm == -1)
  1873. {
  1874. errfunc (ERR_NONFATAL, "cannot create that constant");
  1875. }
  1876. bytes[3] = shimm & 0xFF;
  1877. bytes[2] |= (shimm & 0xF00) >> 8;
  1878. }
  1879. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1880. return;
  1881. case 0x10: // MRS Rd,<psr>
  1882. ++codes;
  1883. bytes[0] = c | *codes++;
  1884. bytes[1] = *codes++;
  1885. // Rd
  1886. c = regval (&ins->oprs[0],1);
  1887. bytes[2] = c << 4;
  1888. bytes[3] = 0;
  1889. c = ins->oprs[1].basereg;
  1890. if (c == R_CPSR || c == R_SPSR)
  1891. {
  1892. if (c == R_SPSR)
  1893. {
  1894. bytes[1] |= 0x40;
  1895. }
  1896. }
  1897. else
  1898. {
  1899. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  1900. }
  1901. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1902. return;
  1903. case 0x11: // MSR <psr>,Rm
  1904. case 0x12: // MSR <psrf>,Rm
  1905. case 0x13: // MSR <psrf>,#expression
  1906. ++codes;
  1907. bytes[0] = c | *codes++;
  1908. bytes[1] = *codes++;
  1909. bytes[2] = *codes;
  1910. if (keep == 0x11 || keep == 0x12)
  1911. {
  1912. // Rm
  1913. c = regval (&ins->oprs[1],1);
  1914. bytes[3] = c;
  1915. }
  1916. else
  1917. {
  1918. int shimm;
  1919. shimm = imm_shift (ins->oprs[1].offset);
  1920. if (shimm == -1)
  1921. {
  1922. errfunc (ERR_NONFATAL, "cannot create that constant");
  1923. }
  1924. bytes[3] = shimm & 0xFF;
  1925. bytes[2] |= (shimm & 0xF00) >> 8;
  1926. }
  1927. c = ins->oprs[0].basereg;
  1928. if ( keep == 0x11)
  1929. {
  1930. if ( c == R_CPSR || c == R_SPSR)
  1931. {
  1932. if ( c== R_SPSR)
  1933. {
  1934. bytes[1] |= 0x40;
  1935. }
  1936. }
  1937. else
  1938. {
  1939. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  1940. }
  1941. }
  1942. else
  1943. {
  1944. if ( c == R_CPSR_FLG || c == R_SPSR_FLG)
  1945. {
  1946. if ( c== R_SPSR_FLG)
  1947. {
  1948. bytes[1] |= 0x40;
  1949. }
  1950. }
  1951. else
  1952. {
  1953. errfunc (ERR_NONFATAL, "CPSR_flg or SPSR_flg expected");
  1954. }
  1955. }
  1956. break;
  1957. case 0x14: // MUL Rd,Rm,Rs
  1958. case 0x15: // MULA Rd,Rm,Rs,Rn
  1959. ++codes;
  1960. bytes[0] = c | *codes++;
  1961. bytes[1] = *codes++;
  1962. bytes[3] = *codes;
  1963. // Rd
  1964. bytes[1] |= regval (&ins->oprs[0],1);
  1965. if (has_S_code)
  1966. bytes[1] |= 0x10;
  1967. // Rm
  1968. bytes[3] |= regval (&ins->oprs[1],1);
  1969. // Rs
  1970. bytes[2] = regval (&ins->oprs[2],1);
  1971. if (keep == 0x15)
  1972. {
  1973. bytes[2] |= regval (&ins->oprs[3],1) << 4;
  1974. }
  1975. break;
  1976. case 0x16: // SMLAL RdHi,RdLo,Rm,Rs
  1977. ++codes;
  1978. bytes[0] = c | *codes++;
  1979. bytes[1] = *codes++;
  1980. bytes[3] = *codes;
  1981. // RdHi
  1982. bytes[1] |= regval (&ins->oprs[1],1);
  1983. if (has_S_code)
  1984. bytes[1] |= 0x10;
  1985. // RdLo
  1986. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1987. // Rm
  1988. bytes[3] |= regval (&ins->oprs[2],1);
  1989. // Rs
  1990. bytes[2] |= regval (&ins->oprs[3],1);
  1991. break;
  1992. case 0x17: // LDR Rd, expression
  1993. ++codes;
  1994. bytes[0] = c | *codes++;
  1995. bytes[1] = *codes++;
  1996. // Rd
  1997. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1998. if (has_B_code)
  1999. bytes[1] |= 0x40;
  2000. if (has_T_code)
  2001. {
  2002. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  2003. }
  2004. if (has_W_code)
  2005. {
  2006. errfunc (ERR_NONFATAL, "'!' not allowed");
  2007. }
  2008. // Rn - implicit R15
  2009. bytes[1] |= 0xF;
  2010. if (ins->oprs[1].segment != segment)
  2011. {
  2012. errfunc (ERR_NONFATAL, "label not in same segment");
  2013. }
  2014. data = ins->oprs[1].offset - (offset + 8);
  2015. if (data < 0)
  2016. {
  2017. data = -data;
  2018. }
  2019. else
  2020. {
  2021. bytes[1] |= 0x80;
  2022. }
  2023. if (data >= 0x1000)
  2024. {
  2025. errfunc (ERR_NONFATAL, "too long offset");
  2026. }
  2027. bytes[2] |= ((data & 0xF00) >> 8);
  2028. bytes[3] = data & 0xFF;
  2029. break;
  2030. case 0x18: // LDR Rd, [Rn]
  2031. ++codes;
  2032. bytes[0] = c | *codes++;
  2033. bytes[1] = *codes++;
  2034. // Rd
  2035. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2036. if (has_B_code)
  2037. bytes[1] |= 0x40;
  2038. if (has_T_code)
  2039. {
  2040. bytes[1] |= 0x20; // write-back
  2041. }
  2042. else
  2043. {
  2044. bytes[0] |= 0x01; // implicit pre-index mode
  2045. }
  2046. if (has_W_code)
  2047. {
  2048. bytes[1] |= 0x20; // write-back
  2049. }
  2050. // Rn
  2051. c = regval (&ins->oprs[1],1);
  2052. bytes[1] |= c;
  2053. if (c == 0x15) // R15
  2054. data = -8;
  2055. else
  2056. data = 0;
  2057. if (data < 0)
  2058. {
  2059. data = -data;
  2060. }
  2061. else
  2062. {
  2063. bytes[1] |= 0x80;
  2064. }
  2065. bytes[2] |= ((data & 0xF00) >> 8);
  2066. bytes[3] = data & 0xFF;
  2067. break;
  2068. case 0x19: // LDR Rd, [Rn,#expression]
  2069. case 0x20: // LDR Rd, [Rn,Rm]
  2070. case 0x21: // LDR Rd, [Rn,Rm,shift]
  2071. ++codes;
  2072. bytes[0] = c | *codes++;
  2073. bytes[1] = *codes++;
  2074. // Rd
  2075. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2076. if (has_B_code)
  2077. bytes[1] |= 0x40;
  2078. // Rn
  2079. c = regval (&ins->oprs[1],1);
  2080. bytes[1] |= c;
  2081. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  2082. {
  2083. bytes[0] |= 0x01; // pre-index mode
  2084. if (has_W_code)
  2085. {
  2086. bytes[1] |= 0x20;
  2087. }
  2088. if (has_T_code)
  2089. {
  2090. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  2091. }
  2092. }
  2093. else
  2094. {
  2095. if (has_T_code) // Forced write-back in post-index mode
  2096. {
  2097. bytes[1] |= 0x20;
  2098. }
  2099. if (has_W_code)
  2100. {
  2101. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  2102. }
  2103. }
  2104. if (keep == 0x19)
  2105. {
  2106. data = ins->oprs[2].offset;
  2107. if (data < 0)
  2108. {
  2109. data = -data;
  2110. }
  2111. else
  2112. {
  2113. bytes[1] |= 0x80;
  2114. }
  2115. if (data >= 0x1000)
  2116. {
  2117. errfunc (ERR_NONFATAL, "too long offset");
  2118. }
  2119. bytes[2] |= ((data & 0xF00) >> 8);
  2120. bytes[3] = data & 0xFF;
  2121. }
  2122. else
  2123. {
  2124. if (ins->oprs[2].minus == 0)
  2125. {
  2126. bytes[1] |= 0x80;
  2127. }
  2128. c = regval (&ins->oprs[2],1);
  2129. bytes[3] = c;
  2130. if (keep == 0x21)
  2131. {
  2132. c = ins->oprs[3].offset;
  2133. if (c > 0x1F)
  2134. {
  2135. errfunc (ERR_NONFATAL, "too large shiftvalue");
  2136. c = c & 0x1F;
  2137. }
  2138. bytes[2] |= c >> 1;
  2139. if (c & 0x01)
  2140. {
  2141. bytes[3] |= 0x80;
  2142. }
  2143. bytes[3] |= shiftval (&ins->oprs[3]) << 5;
  2144. }
  2145. }
  2146. break;
  2147. case 0x22: // LDRH Rd, expression
  2148. ++codes;
  2149. bytes[0] = c | 0x01; // Implicit pre-index
  2150. bytes[1] = *codes++;
  2151. // Rd
  2152. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2153. // Rn - implicit R15
  2154. bytes[1] |= 0xF;
  2155. if (ins->oprs[1].segment != segment)
  2156. {
  2157. errfunc (ERR_NONFATAL, "label not in same segment");
  2158. }
  2159. data = ins->oprs[1].offset - (offset + 8);
  2160. if (data < 0)
  2161. {
  2162. data = -data;
  2163. }
  2164. else
  2165. {
  2166. bytes[1] |= 0x80;
  2167. }
  2168. if (data >= 0x100)
  2169. {
  2170. errfunc (ERR_NONFATAL, "too long offset");
  2171. }
  2172. bytes[3] = *codes++;
  2173. bytes[2] |= ((data & 0xF0) >> 4);
  2174. bytes[3] |= data & 0xF;
  2175. break;
  2176. case 0x23: // LDRH Rd, Rn
  2177. ++codes;
  2178. bytes[0] = c | 0x01; // Implicit pre-index
  2179. bytes[1] = *codes++;
  2180. // Rd
  2181. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2182. // Rn
  2183. c = regval (&ins->oprs[1],1);
  2184. bytes[1] |= c;
  2185. if (c == 0x15) // R15
  2186. data = -8;
  2187. else
  2188. data = 0;
  2189. if (data < 0)
  2190. {
  2191. data = -data;
  2192. }
  2193. else
  2194. {
  2195. bytes[1] |= 0x80;
  2196. }
  2197. if (data >= 0x100)
  2198. {
  2199. errfunc (ERR_NONFATAL, "too long offset");
  2200. }
  2201. bytes[3] = *codes++;
  2202. bytes[2] |= ((data & 0xF0) >> 4);
  2203. bytes[3] |= data & 0xF;
  2204. break;
  2205. case 0x24: // LDRH Rd, Rn, expression
  2206. case 0x25: // LDRH Rd, Rn, Rm
  2207. ++codes;
  2208. bytes[0] = c;
  2209. bytes[1] = *codes++;
  2210. // Rd
  2211. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2212. // Rn
  2213. c = regval (&ins->oprs[1],1);
  2214. bytes[1] |= c;
  2215. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  2216. {
  2217. bytes[0] |= 0x01; // pre-index mode
  2218. if (has_W_code)
  2219. {
  2220. bytes[1] |= 0x20;
  2221. }
  2222. }
  2223. else
  2224. {
  2225. if (has_W_code)
  2226. {
  2227. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  2228. }
  2229. }
  2230. bytes[3] = *codes++;
  2231. if (keep == 0x24)
  2232. {
  2233. data = ins->oprs[2].offset;
  2234. if (data < 0)
  2235. {
  2236. data = -data;
  2237. }
  2238. else
  2239. {
  2240. bytes[1] |= 0x80;
  2241. }
  2242. if (data >= 0x100)
  2243. {
  2244. errfunc (ERR_NONFATAL, "too long offset");
  2245. }
  2246. bytes[2] |= ((data & 0xF0) >> 4);
  2247. bytes[3] |= data & 0xF;
  2248. }
  2249. else
  2250. {
  2251. if (ins->oprs[2].minus == 0)
  2252. {
  2253. bytes[1] |= 0x80;
  2254. }
  2255. c = regval (&ins->oprs[2],1);
  2256. bytes[3] |= c;
  2257. }
  2258. break;
  2259. case 0x26: // LDM/STM Rn, {reg-list}
  2260. ++codes;
  2261. bytes[0] = c;
  2262. bytes[0] |= ( *codes >> 4) & 0xF;
  2263. bytes[1] = ( *codes << 4) & 0xF0;
  2264. ++codes;
  2265. if (has_W_code)
  2266. {
  2267. bytes[1] |= 0x20;
  2268. }
  2269. if (has_F_code)
  2270. {
  2271. bytes[1] |= 0x40;
  2272. }
  2273. // Rn
  2274. bytes[1] |= regval (&ins->oprs[0],1);
  2275. data = ins->oprs[1].basereg;
  2276. bytes[2] = ((data >> 8) & 0xFF);
  2277. bytes[3] = (data & 0xFF);
  2278. break;
  2279. case 0x27: // SWP Rd, Rm, [Rn]
  2280. ++codes;
  2281. bytes[0] = c;
  2282. bytes[0] |= *codes++;
  2283. bytes[1] = regval (&ins->oprs[2],1);
  2284. if (has_B_code)
  2285. {
  2286. bytes[1] |= 0x40;
  2287. }
  2288. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2289. bytes[3] = *codes++;
  2290. bytes[3] |= regval (&ins->oprs[1],1);
  2291. break;
  2292. default:
  2293. errfunc (ERR_FATAL, "unknown decoding of instruction");
  2294. bytes[0] = c;
  2295. // And a fix nibble
  2296. ++codes;
  2297. bytes[0] |= *codes++;
  2298. if ( *codes == 0x01) // An I bit
  2299. {
  2300. }
  2301. if ( *codes == 0x02) // An I bit
  2302. {
  2303. }
  2304. ++codes;
  2305. }
  2306. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2307. }
  2308. *)
  2309. {$endif dummy}
  2310. constructor tai_thumb_func.create;
  2311. begin
  2312. inherited create;
  2313. typ:=ait_thumb_func;
  2314. end;
  2315. begin
  2316. cai_align:=tai_align;
  2317. end.