popt386.pas 100 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2000 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. {$ifdef newOptimizations}
  20. {$define foropt}
  21. {$define replacereg}
  22. {$define arithopt}
  23. {$define foldarithops}
  24. {$endif newOptimizations}
  25. Interface
  26. Uses Aasm;
  27. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  28. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  29. Implementation
  30. Uses
  31. globtype,systems,
  32. globals,verbose,hcodegen,
  33. {$ifdef finaldestdebug}
  34. cobjects,
  35. {$endif finaldestdebug}
  36. cpubase,cpuasm,DAOpt386,tgeni386;
  37. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  38. Begin
  39. reg := reg32(reg);
  40. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  41. RegUsedAfterInstruction :=
  42. (Reg in UsedRegs) and
  43. (not(getNextInstruction(p,p)) or
  44. not(regLoadedWithNewValue(reg,false,p)));
  45. End;
  46. function doFpuLoadStoreOpt(asmL: paasmoutput; var p: pai): boolean;
  47. { returns true if a "continue" should be done after this optimization }
  48. var hp1, hp2: pai;
  49. begin
  50. doFpuLoadStoreOpt := false;
  51. if (paicpu(p)^.oper[0].typ = top_ref) and
  52. getNextInstruction(p, hp1) and
  53. (hp1^.typ = ait_instruction) and
  54. (((paicpu(hp1)^.opcode = A_FLD) and
  55. (paicpu(p)^.opcode = A_FSTP)) or
  56. ((paicpu(p)^.opcode = A_FISTP) and
  57. (paicpu(hp1)^.opcode = A_FILD))) and
  58. (paicpu(hp1)^.oper[0].typ = top_ref) and
  59. (paicpu(hp1)^.opsize = Paicpu(p)^.opsize) and
  60. refsEqual(paicpu(p)^.oper[0].ref^, paicpu(hp1)^.oper[0].ref^) then
  61. begin
  62. if getNextInstruction(hp1, hp2) and
  63. (hp2^.typ = ait_instruction) and
  64. ((paicpu(hp2)^.opcode = A_LEAVE) or
  65. (paicpu(hp2)^.opcode = A_RET)) and
  66. (paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) and
  67. (paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) and
  68. (paicpu(p)^.oper[0].ref^.Index = R_NO) then
  69. begin
  70. asmL^.remove(p);
  71. asmL^.remove(hp1);
  72. dispose(p, done);
  73. dispose(hp1, done);
  74. p := hp2;
  75. removeLastDeallocForFuncRes(asmL, p);
  76. doFPULoadStoreOpt := true;
  77. end
  78. else
  79. { fst can't store an extended value! }
  80. if (paicpu(p)^.opsize <> S_FX) and
  81. (paicpu(p)^.opsize <> S_IQ) then
  82. begin
  83. if (paicpu(p)^.opcode = A_FSTP) then
  84. paicpu(p)^.opcode := A_FST
  85. else Paicpu(p)^.opcode := A_FIST;
  86. asmL^.remove(hp1);
  87. dispose(hp1, done)
  88. end
  89. end;
  90. end;
  91. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  92. {First pass of peepholeoptimizations}
  93. Var
  94. l : longint;
  95. p,hp1,hp2 : pai;
  96. {$ifdef foropt}
  97. hp3,hp4: pai;
  98. {$endif foropt}
  99. TmpBool1, TmpBool2: Boolean;
  100. TmpRef: TReference;
  101. UsedRegs, TmpUsedRegs: TRegSet;
  102. Function SkipLabels(hp: Pai; var hp2: pai): boolean;
  103. {skips all labels and returns the next "real" instruction}
  104. Begin
  105. While assigned(hp^.next) and
  106. (pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
  107. hp := pai(hp^.next);
  108. If assigned(hp^.next) Then
  109. Begin
  110. SkipLabels := True;
  111. hp2 := pai(hp^.next)
  112. End
  113. Else
  114. Begin
  115. hp2 := hp;
  116. SkipLabels := False
  117. End;
  118. End;
  119. Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
  120. {traces sucessive jumps to their final destination and sets it, e.g.
  121. je l1 je l3
  122. <code> <code>
  123. l1: becomes l1:
  124. je l2 je l3
  125. <code> <code>
  126. l2: l2:
  127. jmp l3 jmp l3}
  128. Var p1, p2: pai;
  129. l: pasmlabel;
  130. Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
  131. Begin
  132. FindAnyLabel := false;
  133. While assigned(hp^.next) and
  134. (pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
  135. hp := pai(hp^.next);
  136. If assigned(hp^.next) and
  137. (pai(hp^.next)^.typ = ait_label) Then
  138. Begin
  139. FindAnyLabel := true;
  140. l := pai_label(hp^.next)^.l;
  141. End
  142. End;
  143. Begin
  144. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  145. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  146. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  147. Begin
  148. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  149. SkipLabels(p1,p1);
  150. If (pai(p1)^.typ = ait_instruction) and
  151. (paicpu(p1)^.is_jmp) Then
  152. If { the next instruction after the label where the jump hp arrives}
  153. { is unconditional or of the same type as hp, so continue }
  154. (paicpu(p1)^.condition in [C_None,hp^.condition]) or
  155. { the next instruction after the label where the jump hp arrives}
  156. { is the opposite of hp (so this one is never taken), but after }
  157. { that one there is a branch that will be taken, so perform a }
  158. { little hack: set p1 equal to this instruction (that's what the}
  159. { last SkipLabels is for, only works with short bool evaluation)}
  160. ((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
  161. SkipLabels(p1,p2) and
  162. (p2^.typ = ait_instruction) and
  163. (paicpu(p2)^.is_jmp) and
  164. (paicpu(p2)^.condition in [C_None,hp^.condition]) and
  165. SkipLabels(p1,p1)) Then
  166. Begin
  167. GetFinalDestination(asml, paicpu(p1));
  168. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  169. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  170. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  171. End
  172. Else
  173. If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
  174. if not FindAnyLabel(p1,l) then
  175. begin
  176. {$ifdef finaldestdebug}
  177. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  178. strpnew('previous label inserted'))));
  179. {$endif finaldestdebug}
  180. getlabel(l);
  181. insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
  182. dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
  183. hp^.oper[0].sym := l;
  184. inc(l^.refs);
  185. { this won't work, since the new label isn't in the labeltable }
  186. { so it will fail the rangecheck. Labeltable should become a }
  187. { hashtable to support this: }
  188. { GetFinalDestination(asml, hp); }
  189. end
  190. else
  191. begin
  192. {$ifdef finaldestdebug}
  193. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  194. strpnew('next label reused'))));
  195. {$endif finaldestdebug}
  196. inc(l^.refs);
  197. hp^.oper[0].sym := l;
  198. GetFinalDestination(asml, hp);
  199. end;
  200. End;
  201. End;
  202. Function DoSubAddOpt(var p: Pai): Boolean;
  203. Begin
  204. DoSubAddOpt := False;
  205. If GetLastInstruction(p, hp1) And
  206. (hp1^.typ = ait_instruction) And
  207. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  208. Case Paicpu(hp1)^.opcode Of
  209. A_DEC:
  210. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  211. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  212. Begin
  213. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  214. AsmL^.Remove(hp1);
  215. Dispose(hp1, Done)
  216. End;
  217. A_SUB:
  218. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  219. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  220. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  221. Begin
  222. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  223. AsmL^.Remove(hp1);
  224. Dispose(hp1, Done)
  225. End;
  226. A_ADD:
  227. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  228. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  229. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  230. Begin
  231. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  232. AsmL^.Remove(hp1);
  233. Dispose(hp1, Done);
  234. If (Paicpu(p)^.oper[0].val = 0) Then
  235. Begin
  236. hp1 := Pai(p^.next);
  237. AsmL^.Remove(p);
  238. Dispose(p, Done);
  239. If Not GetLastInstruction(hp1, p) Then
  240. p := hp1;
  241. DoSubAddOpt := True;
  242. End
  243. End;
  244. End;
  245. End;
  246. Begin
  247. P := BlockStart;
  248. UsedRegs := [];
  249. While (P <> BlockEnd) Do
  250. Begin
  251. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  252. Case P^.Typ Of
  253. ait_instruction:
  254. Begin
  255. { Handle Jmp Optimizations }
  256. if Paicpu(p)^.is_jmp then
  257. begin
  258. {the following if-block removes all code between a jmp and the next label,
  259. because it can never be executed}
  260. If (paicpu(p)^.opcode = A_JMP) Then
  261. Begin
  262. While GetNextInstruction(p, hp1) and
  263. ((hp1^.typ <> ait_label) or
  264. { skip unused labels, they're not referenced anywhere }
  265. Not(Pai_Label(hp1)^.l^.is_used)) Do
  266. If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
  267. Begin
  268. AsmL^.Remove(hp1);
  269. Dispose(hp1, done);
  270. End;
  271. End;
  272. If GetNextInstruction(p, hp1) then
  273. Begin
  274. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  275. Begin
  276. hp2:=pai(hp1^.next);
  277. asml^.remove(p);
  278. dispose(p,done);
  279. p:=hp2;
  280. continue;
  281. end
  282. Else
  283. Begin
  284. if hp1^.typ = ait_label then
  285. SkipLabels(hp1,hp1);
  286. If (pai(hp1)^.typ=ait_instruction) and
  287. (paicpu(hp1)^.opcode=A_JMP) and
  288. GetNextInstruction(hp1, hp2) And
  289. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  290. Then
  291. Begin
  292. if paicpu(p)^.opcode=A_Jcc then
  293. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  294. else
  295. begin
  296. If (LabDif <> 0) Then
  297. GetFinalDestination(asml, paicpu(p));
  298. p:=pai(p^.next);
  299. continue;
  300. end;
  301. Dec(pai_label(hp2)^.l^.refs);
  302. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  303. Inc(paicpu(p)^.oper[0].sym^.refs);
  304. asml^.remove(hp1);
  305. dispose(hp1,done);
  306. If (LabDif <> 0) Then
  307. GetFinalDestination(asml, paicpu(p));
  308. end
  309. else
  310. If (LabDif <> 0) Then
  311. GetFinalDestination(asml, paicpu(p));
  312. end;
  313. end;
  314. end
  315. else
  316. { All other optimizes }
  317. begin
  318. For l := 0 to 2 Do
  319. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  320. With Paicpu(p)^.oper[l].ref^ Do
  321. Begin
  322. If (base = R_NO) And
  323. (index <> R_NO) And
  324. (scalefactor in [0,1])
  325. Then
  326. Begin
  327. base := index;
  328. index := R_NO
  329. End
  330. End;
  331. Case Paicpu(p)^.opcode Of
  332. A_AND:
  333. Begin
  334. If (Paicpu(p)^.oper[0].typ = top_const) And
  335. (Paicpu(p)^.oper[1].typ = top_reg) And
  336. GetNextInstruction(p, hp1) And
  337. (Pai(hp1)^.typ = ait_instruction) And
  338. (Paicpu(hp1)^.opcode = A_AND) And
  339. (Paicpu(hp1)^.oper[0].typ = top_const) And
  340. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  341. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  342. Then
  343. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  344. Begin
  345. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  346. AsmL^.Remove(hp1);
  347. Dispose(hp1, Done)
  348. End
  349. Else
  350. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  351. jump, but only if it's a conditional jump (PFV) }
  352. If (Paicpu(p)^.oper[1].typ = top_reg) And
  353. GetNextInstruction(p, hp1) And
  354. (hp1^.typ = ait_instruction) And
  355. (Paicpu(hp1)^.is_jmp) and
  356. (Paicpu(hp1)^.opcode<>A_JMP) and
  357. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  358. Paicpu(p)^.opcode := A_TEST;
  359. End;
  360. A_CMP:
  361. Begin
  362. If (Paicpu(p)^.oper[0].typ = top_const) And
  363. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  364. (Paicpu(p)^.oper[0].val = 0) Then
  365. {$ifdef foropt}
  366. If GetNextInstruction(p, hp1) And
  367. (hp1^.typ = ait_instruction) And
  368. (Paicpu(hp1)^.is_jmp) and
  369. (paicpu(hp1)^.opcode=A_Jcc) and
  370. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  371. GetNextInstruction(hp1,hp2) and
  372. (hp2^.typ = ait_instruction) and
  373. (Paicpu(hp2)^.opcode = A_DEC) And
  374. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  375. GetNextInstruction(hp2, hp3) And
  376. (hp3^.typ = ait_instruction) and
  377. (Paicpu(hp3)^.is_jmp) and
  378. (Paicpu(hp3)^.opcode = A_JMP) And
  379. GetNextInstruction(hp3, hp4) And
  380. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  381. Then
  382. Begin
  383. Paicpu(hp2)^.Opcode := A_SUB;
  384. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  385. Paicpu(hp2)^.LoadConst(0,1);
  386. Paicpu(hp2)^.ops:=2;
  387. Paicpu(hp3)^.Opcode := A_Jcc;
  388. Case paicpu(hp1)^.condition of
  389. C_LE: Paicpu(hp3)^.condition := C_GE;
  390. C_BE: Paicpu(hp3)^.condition := C_AE;
  391. End;
  392. AsmL^.Remove(p);
  393. AsmL^.Remove(hp1);
  394. Dispose(p, Done);
  395. Dispose(hp1, Done);
  396. p := hp2;
  397. continue;
  398. End
  399. Else
  400. {$endif foropt}
  401. {change "cmp $0, %reg" to "test %reg, %reg"}
  402. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  403. Begin
  404. Paicpu(p)^.opcode := A_TEST;
  405. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  406. End;
  407. End;
  408. A_FLD:
  409. Begin
  410. If (Paicpu(p)^.oper[0].typ = top_reg) And
  411. GetNextInstruction(p, hp1) And
  412. (hp1^.typ = Ait_Instruction) And
  413. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  414. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  415. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  416. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  417. { change to
  418. fld reg fxxx reg,st
  419. fxxxp st, st1 (hp1)
  420. Remark: non commutative operations must be reversed!
  421. }
  422. begin
  423. Case Paicpu(hp1)^.opcode Of
  424. A_FMULP,A_FADDP,
  425. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  426. begin
  427. Case Paicpu(hp1)^.opcode Of
  428. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  429. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  430. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  431. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  432. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  433. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  434. End;
  435. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  436. Paicpu(hp1)^.oper[1].reg := R_ST;
  437. AsmL^.Remove(p);
  438. Dispose(p, Done);
  439. p := hp1;
  440. Continue;
  441. end;
  442. end;
  443. end
  444. else
  445. If (Paicpu(p)^.oper[0].typ = top_ref) And
  446. GetNextInstruction(p, hp2) And
  447. (hp2^.typ = Ait_Instruction) And
  448. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  449. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  450. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  451. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  452. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  453. If GetLastInstruction(p, hp1) And
  454. (hp1^.typ = Ait_Instruction) And
  455. ((Paicpu(hp1)^.opcode = A_FLD) Or
  456. (Paicpu(hp1)^.opcode = A_FST)) And
  457. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  458. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  459. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  460. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  461. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  462. { change to
  463. fld/fst mem1 (hp1) fld/fst mem1
  464. fld mem1 (p) fadd/
  465. faddp/ fmul st, st
  466. fmulp st, st1 (hp2) }
  467. Begin
  468. AsmL^.Remove(p);
  469. Dispose(p, Done);
  470. p := hp1;
  471. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  472. Paicpu(hp2)^.opcode := A_FADD
  473. Else
  474. Paicpu(hp2)^.opcode := A_FMUL;
  475. Paicpu(hp2)^.oper[1].reg := R_ST;
  476. End
  477. Else
  478. { change to
  479. fld/fst mem1 (hp1) fld/fst mem1
  480. fld mem1 (p) fld st}
  481. Begin
  482. Paicpu(p)^.changeopsize(S_FL);
  483. Paicpu(p)^.loadreg(0,R_ST);
  484. End
  485. Else
  486. Begin
  487. Case Paicpu(hp2)^.opcode Of
  488. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  489. { change to
  490. fld/fst mem1 (hp1) fld/fst mem1
  491. fld mem2 (p) fxxx mem2
  492. fxxxp st, st1 (hp2) }
  493. Begin
  494. Case Paicpu(hp2)^.opcode Of
  495. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  496. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  497. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  498. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  499. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  500. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  501. End;
  502. AsmL^.Remove(hp2);
  503. Dispose(hp2, Done)
  504. End
  505. End
  506. End
  507. End;
  508. A_FSTP,A_FISTP:
  509. if doFpuLoadStoreOpt(asmL,p) then
  510. continue;
  511. A_IMUL:
  512. {changes certain "imul const, %reg"'s to lea sequences}
  513. Begin
  514. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  515. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  516. (Paicpu(p)^.opsize = S_L) Then
  517. If (Paicpu(p)^.oper[0].val = 1) Then
  518. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  519. {remove "imul $1, reg"}
  520. Begin
  521. hp1 := Pai(p^.Next);
  522. AsmL^.Remove(p);
  523. Dispose(p, Done);
  524. p := hp1;
  525. Continue;
  526. End
  527. Else
  528. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  529. Begin
  530. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  531. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  532. Dispose(p, Done);
  533. p := hp1;
  534. End
  535. Else If
  536. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  537. (Paicpu(p)^.oper[2].typ = Top_None)) And
  538. (aktoptprocessor < ClassP6) And
  539. (Paicpu(p)^.oper[0].val <= 12) And
  540. Not(CS_LittleSize in aktglobalswitches) And
  541. (Not(GetNextInstruction(p, hp1)) Or
  542. {GetNextInstruction(p, hp1) And}
  543. Not((Pai(hp1)^.typ = ait_instruction) And
  544. ((paicpu(hp1)^.opcode=A_Jcc) and
  545. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  546. Then
  547. Begin
  548. Reset_reference(tmpref);
  549. Case Paicpu(p)^.oper[0].val Of
  550. 3: Begin
  551. {imul 3, reg1, reg2 to
  552. lea (reg1,reg1,2), reg2
  553. imul 3, reg1 to
  554. lea (reg1,reg1,2), reg1}
  555. TmpRef.base := Paicpu(p)^.oper[1].reg;
  556. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  557. TmpRef.ScaleFactor := 2;
  558. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  559. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  560. Else
  561. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  562. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  563. Dispose(p, Done);
  564. p := hp1;
  565. End;
  566. 5: Begin
  567. {imul 5, reg1, reg2 to
  568. lea (reg1,reg1,4), reg2
  569. imul 5, reg1 to
  570. lea (reg1,reg1,4), reg1}
  571. TmpRef.base := Paicpu(p)^.oper[1].reg;
  572. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  573. TmpRef.ScaleFactor := 4;
  574. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  575. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  576. Else
  577. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  578. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  579. Dispose(p, Done);
  580. p := hp1;
  581. End;
  582. 6: Begin
  583. {imul 6, reg1, reg2 to
  584. lea (,reg1,2), reg2
  585. lea (reg2,reg1,4), reg2
  586. imul 6, reg1 to
  587. lea (reg1,reg1,2), reg1
  588. add reg1, reg1}
  589. If (aktoptprocessor <= Class386)
  590. Then
  591. Begin
  592. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  593. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  594. Then
  595. Begin
  596. TmpRef.base := Paicpu(p)^.oper[2].reg;
  597. TmpRef.ScaleFactor := 4;
  598. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  599. End
  600. Else
  601. Begin
  602. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  603. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  604. End;
  605. InsertLLItem(AsmL,p, p^.next, hp1);
  606. Reset_reference(tmpref);
  607. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  608. TmpRef.ScaleFactor := 2;
  609. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  610. Then
  611. Begin
  612. TmpRef.base := R_NO;
  613. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  614. Paicpu(p)^.oper[2].reg));
  615. End
  616. Else
  617. Begin
  618. TmpRef.base := Paicpu(p)^.oper[1].reg;
  619. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  620. End;
  621. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  622. Dispose(p, Done);
  623. p := Pai(hp1^.next);
  624. End
  625. End;
  626. 9: Begin
  627. {imul 9, reg1, reg2 to
  628. lea (reg1,reg1,8), reg2
  629. imul 9, reg1 to
  630. lea (reg1,reg1,8), reg1}
  631. TmpRef.base := Paicpu(p)^.oper[1].reg;
  632. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  633. TmpRef.ScaleFactor := 8;
  634. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  635. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  636. Else
  637. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  638. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  639. Dispose(p, Done);
  640. p := hp1;
  641. End;
  642. 10: Begin
  643. {imul 10, reg1, reg2 to
  644. lea (reg1,reg1,4), reg2
  645. add reg2, reg2
  646. imul 10, reg1 to
  647. lea (reg1,reg1,4), reg1
  648. add reg1, reg1}
  649. If (aktoptprocessor <= Class386) Then
  650. Begin
  651. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  652. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  653. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  654. Else
  655. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  656. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  657. InsertLLItem(AsmL,p, p^.next, hp1);
  658. TmpRef.base := Paicpu(p)^.oper[1].reg;
  659. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  660. TmpRef.ScaleFactor := 4;
  661. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  662. Then
  663. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
  664. Else
  665. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  666. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  667. Dispose(p, Done);
  668. p := Pai(hp1^.next);
  669. End
  670. End;
  671. 12: Begin
  672. {imul 12, reg1, reg2 to
  673. lea (,reg1,4), reg2
  674. lea (,reg1,8) reg2
  675. imul 12, reg1 to
  676. lea (reg1,reg1,2), reg1
  677. lea (,reg1,4), reg1}
  678. If (aktoptprocessor <= Class386)
  679. Then
  680. Begin
  681. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  682. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  683. Begin
  684. TmpRef.base := Paicpu(p)^.oper[2].reg;
  685. TmpRef.ScaleFactor := 8;
  686. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  687. End
  688. Else
  689. Begin
  690. TmpRef.base := R_NO;
  691. TmpRef.ScaleFactor := 4;
  692. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  693. End;
  694. InsertLLItem(AsmL,p, p^.next, hp1);
  695. Reset_reference(tmpref);
  696. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  697. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  698. Begin
  699. TmpRef.base := R_NO;
  700. TmpRef.ScaleFactor := 4;
  701. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  702. End
  703. Else
  704. Begin
  705. TmpRef.base := Paicpu(p)^.oper[1].reg;
  706. TmpRef.ScaleFactor := 2;
  707. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  708. End;
  709. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  710. Dispose(p, Done);
  711. p := Pai(hp1^.next);
  712. End
  713. End
  714. End;
  715. End;
  716. End;
  717. A_LEA:
  718. Begin
  719. {removes seg register prefixes from LEA operations, as they
  720. don't do anything}
  721. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  722. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  723. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  724. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  725. {$ifndef newOptimizations}
  726. (Paicpu(p)^.oper[0].ref^.Offset = 0) And
  727. {$endif newOptimizations}
  728. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  729. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  730. {$ifdef newOptimizations}
  731. and (Paicpu(p)^.oper[0].ref^.Offset = 0)
  732. {$endif newOptimizations}
  733. Then
  734. Begin
  735. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  736. Paicpu(p)^.oper[1].reg));
  737. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  738. Dispose(p, Done);
  739. p := hp1;
  740. Continue;
  741. End
  742. Else
  743. {$ifdef newOptimizations}
  744. if (Paicpu(p)^.oper[0].ref^.Offset = 0) then
  745. {$endif newOptimizations}
  746. Begin
  747. hp1 := Pai(p^.Next);
  748. AsmL^.Remove(p);
  749. Dispose(p, Done);
  750. p := hp1;
  751. Continue;
  752. End
  753. {$ifdef newOptimizations}
  754. else
  755. with Paicpu(p)^.oper[0].ref^ do
  756. if (Base = Paicpu(p)^.oper[1].reg) then
  757. begin
  758. l := offset+offsetfixup;
  759. case l of
  760. 1,-1:
  761. begin
  762. if l = 1 then
  763. paicpu(p)^.opcode := A_INC
  764. else paicpu(p)^.opcode := A_DEC;
  765. paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  766. paicpu(p)^.ops := 1;
  767. end;
  768. else
  769. begin
  770. paicpu(p)^.opcode := A_ADD;
  771. paicpu(p)^.loadconst(0,offset+offsetfixup);
  772. end;
  773. end;
  774. end;
  775. {$endif newOptimizations}
  776. End;
  777. A_MOV:
  778. Begin
  779. TmpUsedRegs := UsedRegs;
  780. If (Paicpu(p)^.oper[1].typ = top_reg) And
  781. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  782. GetNextInstruction(p, hp1) And
  783. (Pai(hp1)^.typ = ait_instruction) And
  784. (Paicpu(hp1)^.opcode = A_MOV) And
  785. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  786. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  787. Then
  788. {we have "mov x, %treg; mov %treg, y}
  789. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  790. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  791. Case Paicpu(p)^.oper[0].typ Of
  792. top_reg:
  793. Begin
  794. { change "mov %reg, %treg; mov %treg, y"
  795. to "mov %reg, y" }
  796. Paicpu(p)^.LoadOper(1,Paicpu(hp1)^.oper[1]);
  797. AsmL^.Remove(hp1);
  798. Dispose(hp1, Done);
  799. continue;
  800. End;
  801. top_ref:
  802. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  803. Begin
  804. { change "mov mem, %treg; mov %treg, %reg"
  805. to "mov mem, %reg" }
  806. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  807. AsmL^.Remove(hp1);
  808. Dispose(hp1, Done);
  809. continue;
  810. End;
  811. End
  812. Else
  813. Else
  814. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  815. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  816. penalty}
  817. If (Paicpu(p)^.oper[0].typ = top_reg) And
  818. (Paicpu(p)^.oper[1].typ = top_reg) And
  819. GetNextInstruction(p,hp1) And
  820. (Pai(hp1)^.typ = ait_instruction) And
  821. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  822. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  823. Then
  824. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  825. Begin
  826. If ((Paicpu(hp1)^.opcode = A_OR) Or
  827. (Paicpu(hp1)^.opcode = A_TEST)) And
  828. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  829. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  830. Then
  831. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  832. Begin
  833. TmpUsedRegs := UsedRegs;
  834. { reg1 will be used after the first instruction, }
  835. { so update the allocation info }
  836. allocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  837. If GetNextInstruction(hp1, hp2) And
  838. (hp2^.typ = ait_instruction) And
  839. paicpu(hp2)^.is_jmp and
  840. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  841. Then
  842. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  843. "test %reg1, %reg1; jxx"}
  844. Begin
  845. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  846. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  847. AsmL^.Remove(p);
  848. Dispose(p, done);
  849. p := hp1;
  850. continue
  851. End
  852. Else
  853. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  854. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  855. Begin
  856. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  857. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  858. End;
  859. End
  860. { Else
  861. If (Paicpu(p^.next)^.opcode
  862. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  863. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  864. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  865. End
  866. Else
  867. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  868. x >= RetOffset) as it doesn't do anything (it writes either to a
  869. parameter or to the temporary storage room for the function
  870. result)}
  871. If GetNextInstruction(p, hp1) And
  872. (Pai(hp1)^.typ = ait_instruction)
  873. Then
  874. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  875. (Paicpu(hp1)^.opcode = A_RET)) And
  876. (Paicpu(p)^.oper[1].typ = top_ref) And
  877. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  878. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
  879. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  880. (Paicpu(p)^.oper[0].typ = top_reg)
  881. Then
  882. Begin
  883. AsmL^.Remove(p);
  884. Dispose(p, done);
  885. p := hp1;
  886. RemoveLastDeallocForFuncRes(asmL,p);
  887. End
  888. Else
  889. If (Paicpu(p)^.oper[0].typ = top_reg) And
  890. (Paicpu(p)^.oper[1].typ = top_ref) And
  891. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  892. (Paicpu(hp1)^.opcode = A_CMP) And
  893. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  894. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  895. {change "mov reg1, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  896. begin
  897. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  898. allocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  899. end;
  900. { Next instruction is also a MOV ? }
  901. If GetNextInstruction(p, hp1) And
  902. (pai(hp1)^.typ = ait_instruction) and
  903. (Paicpu(hp1)^.opcode = A_MOV) and
  904. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  905. Then
  906. Begin
  907. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  908. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  909. Then
  910. {mov reg1, mem1 or mov mem1, reg1
  911. mov mem2, reg2 mov reg2, mem2}
  912. Begin
  913. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  914. {mov reg1, mem1 or mov mem1, reg1
  915. mov mem2, reg1 mov reg2, mem1}
  916. Begin
  917. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  918. { Removes the second statement from
  919. mov reg1, mem1/reg2
  920. mov mem1/reg2, reg1 }
  921. Begin
  922. if (paicpu(p)^.oper[0].typ = top_reg) then
  923. AllocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  924. AsmL^.remove(hp1);
  925. Dispose(hp1,done);
  926. End
  927. Else
  928. Begin
  929. TmpUsedRegs := UsedRegs;
  930. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  931. If (Paicpu(p)^.oper[0].typ = top_reg) And
  932. { mov reg1, mem1
  933. mov mem2, reg1 }
  934. GetNextInstruction(hp1, hp2) And
  935. (hp2^.typ = ait_instruction) And
  936. (Paicpu(hp2)^.opcode = A_CMP) And
  937. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  938. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  939. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  940. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  941. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  942. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  943. { change to
  944. mov reg1, mem1 mov reg1, mem1
  945. mov mem2, reg1 cmp reg1, mem2
  946. cmp mem1, reg1 }
  947. Begin
  948. AsmL^.Remove(hp2);
  949. Dispose(hp2, Done);
  950. Paicpu(hp1)^.opcode := A_CMP;
  951. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  952. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  953. End;
  954. End;
  955. End
  956. Else
  957. Begin
  958. tmpUsedRegs := UsedRegs;
  959. If GetNextInstruction(hp1, hp2) And
  960. (Paicpu(p)^.oper[0].typ = top_ref) And
  961. (Paicpu(p)^.oper[1].typ = top_reg) And
  962. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  963. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  964. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  965. (Pai(hp2)^.typ = ait_instruction) And
  966. (Paicpu(hp2)^.opcode = A_MOV) And
  967. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  968. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  969. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  970. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  971. If (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI]) and
  972. not(RegUsedAfterInstruction(R_EDI,hp1,tmpUsedRegs)) Then
  973. { mov mem1, %edi
  974. mov %edi, mem2
  975. mov mem2, reg2
  976. to:
  977. mov mem1, reg2
  978. mov reg2, mem2}
  979. Begin
  980. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  981. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  982. AsmL^.Remove(hp2);
  983. Dispose(hp2,Done);
  984. End
  985. Else
  986. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  987. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  988. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  989. Then
  990. { mov mem1, reg1 mov mem1, reg1
  991. mov reg1, mem2 mov reg1, mem2
  992. mov mem2, reg2 mov mem2, reg1
  993. to: to:
  994. mov mem1, reg1 mov mem1, reg1
  995. mov mem1, reg2 mov reg1, mem2
  996. mov reg1, mem2
  997. or (if mem1 depends on reg1
  998. and/or if mem2 depends on reg2)
  999. to:
  1000. mov mem1, reg1
  1001. mov reg1, mem2
  1002. mov reg1, reg2
  1003. }
  1004. Begin
  1005. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  1006. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  1007. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  1008. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1009. allocRegBetween(asmL,paicpu(p)^.oper[1].reg,p,hp2);
  1010. if (paicpu(p)^.oper[0].ref^.base in (usableregs+[R_EDI])) then
  1011. allocRegBetween(asmL,paicpu(p)^.oper[0].ref^.base,p,hp2);
  1012. if (paicpu(p)^.oper[0].ref^.index in (usableregs+[R_EDI])) then
  1013. allocRegBetween(asmL,paicpu(p)^.oper[0].ref^.index,p,hp2);
  1014. End
  1015. Else
  1016. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  1017. begin
  1018. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg);
  1019. allocRegBetween(asmL,paicpu(p)^.oper[1].reg,p,hp2);
  1020. end
  1021. Else
  1022. Begin
  1023. AsmL^.Remove(hp2);
  1024. Dispose(hp2, Done);
  1025. End
  1026. End;
  1027. End
  1028. Else
  1029. (* {movl [mem1],reg1
  1030. movl [mem1],reg2
  1031. to:
  1032. movl [mem1],reg1
  1033. movl reg1,reg2 }
  1034. If (Paicpu(p)^.oper[0].typ = top_ref) and
  1035. (Paicpu(p)^.oper[1].typ = top_reg) and
  1036. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1037. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1038. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1039. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  1040. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  1041. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  1042. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  1043. Else*)
  1044. { movl const1,[mem1]
  1045. movl [mem1],reg1
  1046. to:
  1047. movl const1,reg1
  1048. movl reg1,[mem1] }
  1049. If (Paicpu(p)^.oper[0].typ = top_const) and
  1050. (Paicpu(p)^.oper[1].typ = top_ref) and
  1051. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1052. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1053. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1054. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  1055. Begin
  1056. allocregbetween(asml,Paicpu(hp1)^.oper[1].reg,p,hp1);
  1057. { allocregbetween doesn't insert this because at }
  1058. { this time, no regalloc info is available in }
  1059. { the optinfo field, so do it manually (JM) }
  1060. hp2 := new(paiRegalloc,alloc(Paicpu(hp1)^.oper[1].reg));
  1061. insertllitem(asml,p^.previous,p,hp2);
  1062. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1063. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  1064. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  1065. End
  1066. End;
  1067. End;
  1068. A_MOVZX:
  1069. Begin
  1070. {removes superfluous And's after movzx's}
  1071. If (Paicpu(p)^.oper[1].typ = top_reg) And
  1072. GetNextInstruction(p, hp1) And
  1073. (Pai(hp1)^.typ = ait_instruction) And
  1074. (Paicpu(hp1)^.opcode = A_AND) And
  1075. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1076. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1077. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1078. Then
  1079. Case Paicpu(p)^.opsize Of
  1080. S_BL, S_BW:
  1081. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  1082. Begin
  1083. AsmL^.Remove(hp1);
  1084. Dispose(hp1, Done);
  1085. End;
  1086. S_WL:
  1087. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  1088. Begin
  1089. AsmL^.Remove(hp1);
  1090. Dispose(hp1, Done);
  1091. End;
  1092. End;
  1093. {changes some movzx constructs to faster synonims (all examples
  1094. are given with eax/ax, but are also valid for other registers)}
  1095. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1096. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1097. Case Paicpu(p)^.opsize of
  1098. S_BW:
  1099. Begin
  1100. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1101. Not(CS_LittleSize In aktglobalswitches)
  1102. Then
  1103. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1104. Begin
  1105. Paicpu(p)^.opcode := A_AND;
  1106. Paicpu(p)^.changeopsize(S_W);
  1107. Paicpu(p)^.LoadConst(0,$ff);
  1108. End
  1109. Else
  1110. If GetNextInstruction(p, hp1) And
  1111. (Pai(hp1)^.typ = ait_instruction) And
  1112. (Paicpu(hp1)^.opcode = A_AND) And
  1113. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1114. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1115. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1116. Then
  1117. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1118. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1119. Begin
  1120. Paicpu(p)^.opcode := A_MOV;
  1121. Paicpu(p)^.changeopsize(S_W);
  1122. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1123. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1124. End;
  1125. End;
  1126. S_BL:
  1127. Begin
  1128. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1129. Not(CS_LittleSize in aktglobalswitches)
  1130. Then
  1131. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1132. Begin
  1133. Paicpu(p)^.opcode := A_AND;
  1134. Paicpu(p)^.changeopsize(S_L);
  1135. Paicpu(p)^.loadconst(0,$ff)
  1136. End
  1137. Else
  1138. If GetNextInstruction(p, hp1) And
  1139. (Pai(hp1)^.typ = ait_instruction) And
  1140. (Paicpu(hp1)^.opcode = A_AND) And
  1141. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1142. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1143. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1144. Then
  1145. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1146. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1147. Begin
  1148. Paicpu(p)^.opcode := A_MOV;
  1149. Paicpu(p)^.changeopsize(S_L);
  1150. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1151. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1152. End
  1153. End;
  1154. S_WL:
  1155. Begin
  1156. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1157. Not(CS_LittleSize In aktglobalswitches)
  1158. Then
  1159. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1160. Begin
  1161. Paicpu(p)^.opcode := A_AND;
  1162. Paicpu(p)^.changeopsize(S_L);
  1163. Paicpu(p)^.LoadConst(0,$ffff);
  1164. End
  1165. Else
  1166. If GetNextInstruction(p, hp1) And
  1167. (Pai(hp1)^.typ = ait_instruction) And
  1168. (Paicpu(hp1)^.opcode = A_AND) And
  1169. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1170. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1171. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1172. Then
  1173. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1174. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1175. Begin
  1176. Paicpu(p)^.opcode := A_MOV;
  1177. Paicpu(p)^.changeopsize(S_L);
  1178. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1179. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1180. End;
  1181. End;
  1182. End
  1183. Else
  1184. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1185. Begin
  1186. If GetNextInstruction(p, hp1) And
  1187. (Pai(hp1)^.typ = ait_instruction) And
  1188. (Paicpu(hp1)^.opcode = A_AND) And
  1189. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1190. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1191. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1192. Begin
  1193. Paicpu(p)^.opcode := A_MOV;
  1194. Case Paicpu(p)^.opsize Of
  1195. S_BL:
  1196. Begin
  1197. Paicpu(p)^.changeopsize(S_L);
  1198. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1199. End;
  1200. S_WL:
  1201. Begin
  1202. Paicpu(p)^.changeopsize(S_L);
  1203. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1204. End;
  1205. S_BW:
  1206. Begin
  1207. Paicpu(p)^.changeopsize(S_W);
  1208. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1209. End;
  1210. End;
  1211. End;
  1212. End;
  1213. End;
  1214. A_POP:
  1215. Begin
  1216. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1217. GetNextInstruction(p, hp1) And
  1218. (pai(hp1)^.typ=ait_instruction) and
  1219. (Paicpu(hp1)^.opcode=A_PUSH) and
  1220. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1221. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1222. { This can't be done, because the register which is popped
  1223. can still be used after the push (PFV)
  1224. If (Not(cs_regalloc in aktglobalswitches)) Then
  1225. Begin
  1226. hp2:=pai(hp1^.next);
  1227. asml^.remove(p);
  1228. asml^.remove(hp1);
  1229. dispose(p,done);
  1230. dispose(hp1,done);
  1231. p:=hp2;
  1232. continue
  1233. End
  1234. Else }
  1235. Begin
  1236. { change it to a two op operation }
  1237. Paicpu(p)^.oper[1].typ:=top_none;
  1238. Paicpu(p)^.ops:=2;
  1239. Paicpu(p)^.opcode := A_MOV;
  1240. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1241. Reset_reference(tmpref);
  1242. TmpRef.base := R_ESP;
  1243. Paicpu(p)^.LoadRef(0,newReference(TmpRef));
  1244. AsmL^.Remove(hp1);
  1245. Dispose(hp1, Done)
  1246. End;
  1247. end;
  1248. A_PUSH:
  1249. Begin
  1250. If (Paicpu(p)^.opsize = S_W) And
  1251. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1252. GetNextInstruction(p, hp1) And
  1253. (Pai(hp1)^.typ = ait_instruction) And
  1254. (Paicpu(hp1)^.opcode = A_PUSH) And
  1255. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1256. (Paicpu(hp1)^.opsize = S_W) Then
  1257. Begin
  1258. Paicpu(p)^.changeopsize(S_L);
  1259. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + word(Paicpu(hp1)^.oper[0].val));
  1260. AsmL^.Remove(hp1);
  1261. Dispose(hp1, Done)
  1262. End;
  1263. End;
  1264. A_SHL, A_SAL:
  1265. Begin
  1266. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1267. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1268. (Paicpu(p)^.opsize = S_L) And
  1269. (Paicpu(p)^.oper[0].val <= 3)
  1270. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1271. Then
  1272. Begin
  1273. TmpBool1 := True; {should we check the next instruction?}
  1274. TmpBool2 := False; {have we found an add/sub which could be
  1275. integrated in the lea?}
  1276. Reset_reference(tmpref);
  1277. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1278. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1279. While TmpBool1 And
  1280. GetNextInstruction(p, hp1) And
  1281. (Pai(hp1)^.typ = ait_instruction) And
  1282. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1283. (Paicpu(hp1)^.opcode = A_SUB)) And
  1284. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1285. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1286. Begin
  1287. TmpBool1 := False;
  1288. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1289. Then
  1290. Begin
  1291. TmpBool1 := True;
  1292. TmpBool2 := True;
  1293. If Paicpu(hp1)^.opcode = A_ADD Then
  1294. Inc(TmpRef.offset, Paicpu(hp1)^.oper[0].val)
  1295. Else
  1296. Dec(TmpRef.offset, Paicpu(hp1)^.oper[0].val);
  1297. AsmL^.Remove(hp1);
  1298. Dispose(hp1, Done);
  1299. End
  1300. Else
  1301. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1302. (Paicpu(hp1)^.opcode = A_ADD) And
  1303. (TmpRef.base = R_NO) Then
  1304. Begin
  1305. TmpBool1 := True;
  1306. TmpBool2 := True;
  1307. TmpRef.base := Paicpu(hp1)^.oper[0].reg;
  1308. AsmL^.Remove(hp1);
  1309. Dispose(hp1, Done);
  1310. End;
  1311. End;
  1312. If TmpBool2 Or
  1313. ((aktoptprocessor < ClassP6) And
  1314. (Paicpu(p)^.oper[0].val <= 3) And
  1315. Not(CS_LittleSize in aktglobalswitches))
  1316. Then
  1317. Begin
  1318. If Not(TmpBool2) And
  1319. (Paicpu(p)^.oper[0].val = 1)
  1320. Then
  1321. Begin
  1322. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1323. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1324. End
  1325. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  1326. Paicpu(p)^.oper[1].reg));
  1327. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1328. Dispose(p, Done);
  1329. p := hp1;
  1330. End;
  1331. End
  1332. Else
  1333. If (aktoptprocessor < ClassP6) And
  1334. (Paicpu(p)^.oper[0].typ = top_const) And
  1335. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1336. If (Paicpu(p)^.oper[0].val = 1)
  1337. Then
  1338. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1339. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1340. (unlike shl, which is only pairable in the U pipe)}
  1341. Begin
  1342. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1343. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1344. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1345. Dispose(p, done);
  1346. p := hp1;
  1347. End
  1348. Else If (Paicpu(p)^.opsize = S_L) and
  1349. (Paicpu(p)^.oper[0].val<= 3) Then
  1350. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1351. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1352. Begin
  1353. Reset_reference(tmpref);
  1354. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1355. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1356. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  1357. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1358. Dispose(p, done);
  1359. p := hp1;
  1360. End
  1361. End;
  1362. A_SAR, A_SHR:
  1363. {changes the code sequence
  1364. shr/sar const1, x
  1365. shl const2, x
  1366. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1367. Begin
  1368. If GetNextInstruction(p, hp1) And
  1369. (pai(hp1)^.typ = ait_instruction) and
  1370. (Paicpu(hp1)^.opcode = A_SHL) and
  1371. (Paicpu(p)^.oper[0].typ = top_const) and
  1372. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1373. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1374. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1375. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1376. Then
  1377. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1378. Not(CS_LittleSize In aktglobalswitches)
  1379. Then
  1380. { shr/sar const1, %reg
  1381. shl const2, %reg
  1382. with const1 > const2 }
  1383. Begin
  1384. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1385. Paicpu(hp1)^.opcode := A_AND;
  1386. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1387. Case Paicpu(p)^.opsize Of
  1388. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1389. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1390. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1391. End;
  1392. End
  1393. Else
  1394. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1395. Not(CS_LittleSize In aktglobalswitches)
  1396. Then
  1397. { shr/sar const1, %reg
  1398. shl const2, %reg
  1399. with const1 < const2 }
  1400. Begin
  1401. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1402. Paicpu(p)^.opcode := A_AND;
  1403. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1404. Case Paicpu(p)^.opsize Of
  1405. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1406. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1407. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1408. End;
  1409. End
  1410. Else
  1411. { shr/sar const1, %reg
  1412. shl const2, %reg
  1413. with const1 = const2 }
  1414. Begin
  1415. Paicpu(p)^.opcode := A_AND;
  1416. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1417. Case Paicpu(p)^.opsize Of
  1418. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1419. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1420. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1421. End;
  1422. AsmL^.remove(hp1);
  1423. dispose(hp1, done);
  1424. End;
  1425. End;
  1426. A_SETcc :
  1427. { changes
  1428. setcc (funcres) setcc reg
  1429. movb (funcres), reg to leave/ret
  1430. leave/ret }
  1431. Begin
  1432. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1433. GetNextInstruction(p, hp1) And
  1434. GetNextInstruction(hp1, hp2) And
  1435. (hp2^.typ = ait_instruction) And
  1436. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1437. (Paicpu(hp2)^.opcode = A_RET)) And
  1438. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1439. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1440. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  1441. (hp1^.typ = ait_instruction) And
  1442. (Paicpu(hp1)^.opcode = A_MOV) And
  1443. (Paicpu(hp1)^.opsize = S_B) And
  1444. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1445. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1446. Begin
  1447. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1448. AsmL^.Remove(hp1);
  1449. Dispose(hp1, Done)
  1450. End
  1451. End;
  1452. A_SUB:
  1453. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1454. { * change "sub/add const1, reg" or "dec reg" followed by
  1455. "sub const2, reg" to one "sub ..., reg" }
  1456. Begin
  1457. If (Paicpu(p)^.oper[0].typ = top_const) And
  1458. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1459. If (Paicpu(p)^.oper[0].val = 2) And
  1460. (Paicpu(p)^.oper[1].reg = R_ESP) and
  1461. { Don't do the sub/push optimization if the sub }
  1462. { comes from setting up the stack frame (JM) }
  1463. (not getLastInstruction(p,hp1) or
  1464. (hp1^.typ <> ait_instruction) or
  1465. (paicpu(hp1)^.opcode <> A_MOV) or
  1466. (paicpu(hp1)^.oper[0].typ <> top_reg) or
  1467. (paicpu(hp1)^.oper[0].reg <> R_ESP) or
  1468. (paicpu(hp1)^.oper[1].typ <> top_reg) or
  1469. (paicpu(hp1)^.oper[1].reg <> R_EBP)) then
  1470. Begin
  1471. hp1 := Pai(p^.next);
  1472. While Assigned(hp1) And
  1473. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1474. Not((Pai(hp1)^.typ = ait_instruction) And
  1475. ((Paicpu(hp1)^.opcode = A_CALL) or
  1476. (Paicpu(hp1)^.opcode = A_PUSH) or
  1477. ((Paicpu(hp1)^.opcode = A_MOV) And
  1478. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1479. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1480. hp1 := Pai(hp1^.next);
  1481. If Assigned(hp1) And
  1482. (Pai(hp1)^.typ = ait_instruction) And
  1483. (Paicpu(hp1)^.opcode = A_PUSH) And
  1484. (Paicpu(hp1)^.opsize = S_W)
  1485. Then
  1486. Begin
  1487. Paicpu(hp1)^.changeopsize(S_L);
  1488. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1489. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1490. hp1 := Pai(p^.next);
  1491. AsmL^.Remove(p);
  1492. Dispose(p, Done);
  1493. p := hp1;
  1494. Continue
  1495. End;
  1496. If DoSubAddOpt(p) Then continue;
  1497. End
  1498. Else If DoSubAddOpt(p) Then Continue
  1499. End;
  1500. A_TEST, A_OR:
  1501. {removes the line marked with (x) from the sequence
  1502. And/or/xor/add/sub/... $x, %y
  1503. test/or %y, %y (x)
  1504. j(n)z _Label
  1505. as the first instruction already adjusts the ZF}
  1506. Begin
  1507. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1508. If GetLastInstruction(p, hp1) And
  1509. (pai(hp1)^.typ = ait_instruction) Then
  1510. Case Paicpu(hp1)^.opcode Of
  1511. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1512. Begin
  1513. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1514. Begin
  1515. hp1 := pai(p^.next);
  1516. asml^.remove(p);
  1517. dispose(p, done);
  1518. p := pai(hp1);
  1519. continue
  1520. End;
  1521. End;
  1522. A_DEC, A_INC, A_NEG:
  1523. Begin
  1524. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1525. Begin
  1526. Case Paicpu(hp1)^.opcode Of
  1527. A_DEC, A_INC:
  1528. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1529. Begin
  1530. Case Paicpu(hp1)^.opcode Of
  1531. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1532. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1533. End;
  1534. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1535. Paicpu(hp1)^.LoadConst(0,1);
  1536. Paicpu(hp1)^.ops:=2;
  1537. End
  1538. End;
  1539. hp1 := pai(p^.next);
  1540. asml^.remove(p);
  1541. dispose(p, done);
  1542. p := pai(hp1);
  1543. continue
  1544. End;
  1545. End
  1546. End
  1547. Else
  1548. End;
  1549. A_XOR:
  1550. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1551. (Paicpu(p)^.oper[1].typ = top_reg) And
  1552. (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
  1553. { temporarily change this to 'mov reg,0' to make it easier }
  1554. { for the CSE. Will be changed back in pass 2 }
  1555. begin
  1556. paicpu(p)^.opcode := A_MOV;
  1557. paicpu(p)^.loadconst(0,0);
  1558. end;
  1559. End;
  1560. end; { if is_jmp }
  1561. End;
  1562. { ait_label:
  1563. Begin
  1564. If Not(Pai_Label(p)^.l^.is_used)
  1565. Then
  1566. Begin
  1567. hp1 := Pai(p^.next);
  1568. AsmL^.Remove(p);
  1569. Dispose(p, Done);
  1570. p := hp1;
  1571. Continue
  1572. End;
  1573. End;}
  1574. End;
  1575. p:=pai(p^.next);
  1576. end;
  1577. end;
  1578. {$ifdef foldArithOps}
  1579. Function IsArithOp(opcode: TAsmOp): Boolean;
  1580. Begin
  1581. IsArithOp := False;
  1582. Case opcode Of
  1583. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR: IsArithOp := True
  1584. End;
  1585. End;
  1586. {$endif foldArithOps}
  1587. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1588. function CanBeCMOV(p : pai) : boolean;
  1589. begin
  1590. CanBeCMOV:=assigned(p) and (p^.typ=ait_instruction) and
  1591. (paicpu(p)^.opcode=A_MOV) and
  1592. (paicpu(p)^.opsize in [S_L,S_W]) and
  1593. (paicpu(p)^.oper[0].typ in [top_reg,top_ref]) and
  1594. (paicpu(p)^.oper[1].typ in [top_reg,top_ref]);
  1595. end;
  1596. var
  1597. p,hp1,hp2: pai;
  1598. {$ifdef USECMOV}
  1599. l : longint;
  1600. condition : tasmcond;
  1601. hp3: pai;
  1602. {$endif USECMOV}
  1603. {$ifdef foldArithOps}
  1604. UsedRegs, TmpUsedRegs: TRegSet;
  1605. {$endif foldArithOps}
  1606. Begin
  1607. P := BlockStart;
  1608. {$ifdef foldArithOps}
  1609. UsedRegs := [];
  1610. {$endif foldArithOps}
  1611. While (P <> BlockEnd) Do
  1612. Begin
  1613. {$ifdef foldArithOps}
  1614. UpdateUsedRegs(UsedRegs, Pai(p^.next));
  1615. {$endif foldArithOps}
  1616. Case P^.Typ Of
  1617. Ait_Instruction:
  1618. Begin
  1619. Case Paicpu(p)^.opcode Of
  1620. A_CALL:
  1621. If (AktOptProcessor < ClassP6) And
  1622. GetNextInstruction(p, hp1) And
  1623. (hp1^.typ = ait_instruction) And
  1624. (paicpu(hp1)^.opcode = A_JMP) Then
  1625. Begin
  1626. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1627. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1628. InsertLLItem(AsmL, p^.previous, p, hp2);
  1629. Paicpu(p)^.opcode := A_JMP;
  1630. AsmL^.Remove(hp1);
  1631. Dispose(hp1, Done)
  1632. End;
  1633. {$ifdef USECMOV}
  1634. A_Jcc:
  1635. if (aktspecificoptprocessor=ClassP6) then
  1636. begin
  1637. { check for
  1638. jCC xxx
  1639. <several movs>
  1640. xxx:
  1641. }
  1642. l:=0;
  1643. GetNextInstruction(p, hp1);
  1644. while assigned(hp1) And
  1645. CanBeCMOV(hp1) do
  1646. begin
  1647. inc(l);
  1648. GetNextInstruction(hp1,hp1);
  1649. end;
  1650. if assigned(hp1) then
  1651. begin
  1652. if FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1653. begin
  1654. if (l<=4) and (l>0) then
  1655. begin
  1656. condition:=inverse_cond[paicpu(p)^.condition];
  1657. GetNextInstruction(p,hp1);
  1658. asml^.remove(p);
  1659. dispose(p,done);
  1660. p:=hp1;
  1661. repeat
  1662. paicpu(hp1)^.opcode:=A_CMOVcc;
  1663. paicpu(hp1)^.condition:=condition;
  1664. GetNextInstruction(hp1,hp1);
  1665. until not(assigned(hp1)) or
  1666. not(CanBeCMOV(hp1));
  1667. asml^.remove(hp1);
  1668. dispose(hp1,done);
  1669. continue;
  1670. end;
  1671. end
  1672. else
  1673. begin
  1674. { check further for
  1675. jCC xxx
  1676. <several movs>
  1677. jmp yyy
  1678. xxx:
  1679. <several movs>
  1680. yyy:
  1681. }
  1682. { hp2 points to jmp xxx }
  1683. hp2:=hp1;
  1684. { skip hp1 to xxx }
  1685. GetNextInstruction(hp1, hp1);
  1686. if assigned(hp2) and
  1687. assigned(hp1) and
  1688. (l<=3) and
  1689. (hp2^.typ=ait_instruction) and
  1690. (paicpu(hp2)^.is_jmp) and
  1691. (paicpu(hp2)^.condition=C_None) and
  1692. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1693. begin
  1694. l:=0;
  1695. while assigned(hp1) And
  1696. CanBeCMOV(hp1) do
  1697. begin
  1698. inc(l);
  1699. GetNextInstruction(hp1, hp1);
  1700. end;
  1701. end;
  1702. {
  1703. if assigned(hp1) and
  1704. FindLabel(PAsmLabel(paicpu(hp2)^.oper[0].sym),hp1) then
  1705. begin
  1706. condition:=inverse_cond[paicpu(p)^.condition];
  1707. GetNextInstruction(p,hp1);
  1708. asml^.remove(p);
  1709. dispose(p,done);
  1710. p:=hp1;
  1711. repeat
  1712. paicpu(hp1)^.opcode:=A_CMOVcc;
  1713. paicpu(hp1)^.condition:=condition;
  1714. GetNextInstruction(hp1,hp1);
  1715. until not(assigned(hp1)) or
  1716. not(CanBeCMOV(hp1));
  1717. hp2:=hp1^.next;
  1718. condition:=inverse_cond[condition];
  1719. asml^.remove(hp1^.next)
  1720. dispose(hp1^.next,done);
  1721. asml^.remove(hp1);
  1722. dispose(hp1,done);
  1723. continue;
  1724. end;
  1725. }
  1726. end;
  1727. end;
  1728. end;
  1729. {$endif USECMOV}
  1730. A_FSTP,A_FISTP:
  1731. if doFpuLoadStoreOpt(asmL,p) then
  1732. continue;
  1733. {$ifdef foldArithOps}
  1734. A_IMUL:
  1735. begin
  1736. if ((paicpu(p)^.oper[0].typ = top_const) or
  1737. (paicpu(p)^.oper[0].typ = top_symbol)) and
  1738. (paicpu(p)^.oper[1].typ = top_reg) and
  1739. ((paicpu(p)^.oper[2].typ = top_none) or
  1740. ((paicpu(p)^.oper[2].typ = top_reg) and
  1741. (paicpu(p)^.oper[2].reg = paicpu(p)^.oper[1].reg))) and
  1742. getLastInstruction(p,hp1) and
  1743. (hp1^.typ = ait_instruction) and
  1744. (paicpu(hp1)^.opcode = A_MOV) and
  1745. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1746. (paicpu(hp1)^.oper[1].typ = top_reg) and
  1747. (paicpu(hp1)^.oper[1].reg = paicpu(p)^.oper[1].reg) then
  1748. { change "mov reg1,reg2; imul y,reg2" to "imul y,reg1,reg2" }
  1749. begin
  1750. paicpu(p)^.ops := 3;
  1751. paicpu(p)^.loadreg(1,paicpu(hp1)^.oper[0].reg);
  1752. paicpu(p)^.loadreg(2,paicpu(hp1)^.oper[1].reg);
  1753. asmL^.remove(hp1);
  1754. dispose(hp1,done);
  1755. end;
  1756. end;
  1757. {$endif foldArithOps}
  1758. A_MOV:
  1759. Begin
  1760. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1761. (Paicpu(p)^.oper[1].typ = top_reg) And
  1762. GetNextInstruction(p, hp1) And
  1763. (hp1^.typ = ait_Instruction) And
  1764. ((Paicpu(hp1)^.opcode = A_MOV) or
  1765. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1766. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1767. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1768. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1769. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1770. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1771. (Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
  1772. {mov reg1, reg2
  1773. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1774. Begin
  1775. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1776. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1777. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1778. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1779. AsmL^.Remove(p);
  1780. Dispose(p, Done);
  1781. p := hp1;
  1782. Continue;
  1783. End
  1784. {$ifdef foldArithOps}
  1785. Else If (Paicpu(p)^.oper[0].typ = top_ref) And
  1786. GetNextInstruction(p,hp1) And
  1787. (hp1^.typ = ait_instruction) And
  1788. IsArithOp(Paicpu(hp1)^.opcode) And
  1789. (Paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) And
  1790. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1791. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) And
  1792. GetNextInstruction(hp1,hp2) And
  1793. (hp2^.typ = ait_instruction) And
  1794. (Paicpu(hp2)^.opcode = A_MOV) And
  1795. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  1796. (Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  1797. (Paicpu(hp2)^.oper[1].typ = top_ref) Then
  1798. Begin
  1799. TmpUsedRegs := UsedRegs;
  1800. UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
  1801. If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
  1802. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg,
  1803. hp2, TmpUsedRegs)))
  1804. Then
  1805. { change mov (ref), reg }
  1806. { add/sub/or/... reg2/$const, reg }
  1807. { mov (reg), ref }
  1808. { # release reg }
  1809. { to add/sub/or/... reg2/$const, (ref) }
  1810. Begin
  1811. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
  1812. AsmL^.Remove(p);
  1813. AsmL^.Remove(hp2);
  1814. Dispose(p,done);
  1815. Dispose(hp2,Done);
  1816. p := hp1
  1817. End;
  1818. End
  1819. {$endif foldArithOps}
  1820. else if (Paicpu(p)^.oper[0].typ = Top_Const) And
  1821. (Paicpu(p)^.oper[0].val = 0) And
  1822. (Paicpu(p)^.oper[1].typ = Top_Reg) Then
  1823. { change "mov $0, %reg" into "xor %reg, %reg" }
  1824. Begin
  1825. Paicpu(p)^.opcode := A_XOR;
  1826. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1827. End
  1828. End;
  1829. A_MOVZX:
  1830. Begin
  1831. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1832. If (Paicpu(p)^.oper[0].typ = top_reg)
  1833. Then
  1834. Case Paicpu(p)^.opsize of
  1835. S_BL:
  1836. Begin
  1837. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1838. Not(CS_LittleSize in aktglobalswitches) And
  1839. (aktoptprocessor = ClassP5)
  1840. Then
  1841. {Change "movzbl %reg1, %reg2" to
  1842. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1843. PentiumMMX}
  1844. Begin
  1845. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1846. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1847. InsertLLItem(AsmL,p^.previous, p, hp1);
  1848. Paicpu(p)^.opcode := A_MOV;
  1849. Paicpu(p)^.changeopsize(S_B);
  1850. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1851. End;
  1852. End;
  1853. End
  1854. Else
  1855. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1856. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1857. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1858. Not(CS_LittleSize in aktglobalswitches) And
  1859. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1860. (aktoptprocessor = ClassP5) And
  1861. (Paicpu(p)^.opsize = S_BL)
  1862. Then
  1863. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1864. Pentium and PentiumMMX}
  1865. Begin
  1866. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1867. Paicpu(p)^.oper[1].reg));
  1868. Paicpu(p)^.opcode := A_MOV;
  1869. Paicpu(p)^.changeopsize(S_B);
  1870. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1871. InsertLLItem(AsmL,p^.previous, p, hp1);
  1872. End;
  1873. End;
  1874. End;
  1875. End;
  1876. End;
  1877. p := Pai(p^.next)
  1878. End;
  1879. End;
  1880. End.
  1881. {
  1882. $Log$
  1883. Revision 1.93 2000-05-23 10:58:46 jonas
  1884. * fixed bug in "subl $2,%esp; .. ; pushw mem" optimization when the
  1885. sub comes from setting up the stack frame instead of from aligning
  1886. esp (I hope)
  1887. Revision 1.92 2000/04/23 14:56:36 jonas
  1888. * changed "mov reg1, reg2; mov reg2, y" optimization that caused
  1889. regalloc info to become invalid (it's still performed, but the
  1890. regalloc info stays valid now)
  1891. Revision 1.91 2000/04/16 16:46:43 jonas
  1892. * small regalloc fix
  1893. Revision 1.90 2000/03/26 10:58:47 jonas
  1894. * some more allocRegBetween fixes (-al didn't function previously
  1895. if the compiler was compiled with -OG2p3r)
  1896. Revision 1.89 2000/03/26 08:46:52 jonas
  1897. * fixed bug in regUsedAfterInstruction (it didn't convert the reg
  1898. to 32bit before checking)
  1899. * result: make cycle now works with -OG3p3r!!!!
  1900. Revision 1.88 2000/03/25 18:57:02 jonas
  1901. * remove dealloc/alloc of reg1 between "movl %reg1,%reg2;
  1902. movl %reg2,%reg1" when removing the second instruction (it
  1903. confused the CSE and caused errors with -Or)
  1904. Revision 1.87 2000/02/13 14:21:50 jonas
  1905. * modifications to make the compiler functional when compiled with
  1906. -Or
  1907. Revision 1.86 2000/02/12 19:28:56 jonas
  1908. * fix for imul optimization in popt386 (exclude top_ref as first
  1909. argument)
  1910. * in csopt386: change "mov reg1,reg2; <several operations on reg2>;
  1911. mov reg2,reg1" to "<several operations on reg1>" (-dnewopt...)
  1912. Revision 1.85 2000/02/12 14:10:15 jonas
  1913. + change "mov reg1,reg2;imul x,reg2" to "imul x,reg1,reg2" in popt386
  1914. (-dnewoptimizations)
  1915. * shl(d) and shr(d) are considered to have a hardcoded register if
  1916. they use cl as shift count (since you can't replace them with
  1917. another register) in csopt386 (also for -dnewoptimizations)
  1918. Revision 1.84 2000/02/09 13:22:58 peter
  1919. * log truncated
  1920. Revision 1.83 2000/02/04 13:53:04 jonas
  1921. * fpuloadstore optimizations are now done before and after the CSE
  1922. Revision 1.82 2000/01/24 12:17:24 florian
  1923. * some improvemenst to cmov support
  1924. * disabled excpetion frame generation in cosntructors temporarily
  1925. Revision 1.81 2000/01/23 21:29:17 florian
  1926. * CMOV support in optimizer (in define USECMOV)
  1927. + start of support of exceptions in constructors
  1928. Revision 1.80 2000/01/22 16:05:15 jonas
  1929. + change "lea x(reg),reg" to "add x,reg" (-dnewoptimizations)
  1930. * detection whether edi is used after instructions (since regalloc
  1931. info for it is now available)
  1932. * better regUsedAfterInstruction function
  1933. Revision 1.79 2000/01/21 11:26:19 pierre
  1934. * bug fix for bug 802
  1935. Revision 1.78 2000/01/11 17:14:49 jonas
  1936. * fixed a serious memory leak
  1937. Revision 1.77 2000/01/09 12:35:02 jonas
  1938. * changed edi allocation to use getexplicitregister32/ungetregister
  1939. (adapted tgeni386 a bit for this) and enabled it by default
  1940. * fixed very big and stupid bug of mine in cg386mat that broke the
  1941. include() code (and make cycle :( ) if you compiled without
  1942. -dnewoptimizations
  1943. Revision 1.76 2000/01/07 01:14:30 peter
  1944. * updated copyright to 2000
  1945. Revision 1.75 1999/12/30 17:56:44 peter
  1946. * fixed and;jmp being translated into test;jmp
  1947. Revision 1.74 1999/12/05 16:48:43 jonas
  1948. * CSE of constant loading in regs works properly again
  1949. + if a constant is stored into memory using "mov const, ref" and
  1950. there is a reg that contains this const, it is changed into
  1951. "mov reg, ref"
  1952. Revision 1.73 1999/12/02 11:26:41 peter
  1953. * newoptimizations define added
  1954. Revision 1.72 1999/11/30 10:40:45 peter
  1955. + ttype, tsymlist
  1956. Revision 1.71 1999/11/27 23:47:55 jonas
  1957. + change "mov var,reg; add/shr/... x,reg; mov reg,var" to
  1958. "add/shr/... x,var" (if x is a const or reg, suggestion from Peter)
  1959. Enable with -dfoldArithOps
  1960. Revision 1.70 1999/11/21 13:09:41 jonas
  1961. * fixed some missed optimizations because 8bit regs were not always
  1962. taken into account
  1963. Revision 1.69 1999/11/13 19:03:56 jonas
  1964. * don't remove align objects between JMP's and labels
  1965. Revision 1.68 1999/11/06 16:24:00 jonas
  1966. * getfinaldestination works completely again (a lot of functionality
  1967. got lost in the conversion resulting from the removal of
  1968. ait_labeled_instruction)
  1969. Revision 1.67 1999/11/06 14:34:23 peter
  1970. * truncated log to 20 revs
  1971. Revision 1.66 1999/09/27 23:44:55 peter
  1972. * procinfo is now a pointer
  1973. * support for result setting in sub procedure
  1974. Revision 1.65 1999/09/05 14:27:19 florian
  1975. + fld reg;fxxx to fxxxr reg optimization
  1976. Revision 1.64 1999/08/25 12:00:02 jonas
  1977. * changed pai386, paippc and paiapha (same for tai*) to paicpu (taicpu)
  1978. }