cpuinfo.pas 5.1 KB

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  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the Xtensa
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. {$i fpcdefs.inc}
  12. Interface
  13. uses
  14. globtype,
  15. systems;
  16. Type
  17. bestreal = double;
  18. bestrealrec = TDoubleRec;
  19. ts32real = single;
  20. ts64real = double;
  21. ts80real = type extended;
  22. ts128real = type extended;
  23. ts64comp = comp;
  24. pbestreal=^bestreal;
  25. { possible supported processors for this target }
  26. tcputype =
  27. (cpu_none,
  28. cpu_lx106,
  29. cpu_lx6
  30. );
  31. Type
  32. tfputype =
  33. (fpu_none,
  34. fpu_soft,
  35. fpu_libgcc
  36. );
  37. Type
  38. tcontrollertype =
  39. (ct_none,
  40. ct_esp8266,
  41. ct_esp32,
  42. ct_esp32_d0wd,
  43. ct_esp32_d2wd,
  44. ct_esp32_sOwd
  45. );
  46. tcontrollerdatatype = record
  47. controllertypestr, controllerunitstr: string[20];
  48. cputype: tcputype; fputype: tfputype; abi: tabi;
  49. flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
  50. end;
  51. Const
  52. { Is there support for dealing with multiple microcontrollers available }
  53. { for this platform? }
  54. ControllerSupport = true;
  55. {# Size of native extended floating point type }
  56. extended_size = 12;
  57. { target cpu string (used by compiler options) }
  58. target_cpu_string = 'xtensa';
  59. { calling conventions supported by the code generator }
  60. supported_calling_conventions : tproccalloptions = [
  61. pocall_internproc,
  62. pocall_safecall,
  63. pocall_stdcall,
  64. { same as stdcall only different name mangling }
  65. pocall_cdecl,
  66. { same as stdcall only different name mangling }
  67. pocall_cppdecl,
  68. { same as stdcall but floating point numbers are handled like equal sized integers }
  69. pocall_softfloat,
  70. { used for interrupt handling }
  71. pocall_interrupt
  72. ];
  73. cputypestr : array[tcputype] of string[8] = (
  74. '',
  75. 'LX106',
  76. 'LX6'
  77. );
  78. fputypestr : array[tfputype] of string[10] = (
  79. 'NONE',
  80. 'SOFT',
  81. 'LIBGCC'
  82. );
  83. { We know that there are fields after sramsize
  84. but we don't care about this warning }
  85. {$WARN 3177 OFF}
  86. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  87. (
  88. (controllertypestr:''; controllerunitstr:''; cputype:cpu_none; fputype:fpu_none; abi: abi_default; flashbase:0),
  89. (controllertypestr:'ESP8266'; controllerunitstr:'ESP8266'; cputype:cpu_lx106; fputype:fpu_none; abi: abi_xtensa_call0; { flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024 }),
  90. (controllertypestr:'ESP32'; controllerunitstr:'ESP32'; cputype:cpu_lx6; fputype:fpu_none; abi: abi_xtensa_windowed),
  91. (controllertypestr:'ESP32_D0WD'; controllerunitstr:'ESP32_D0WD'; cputype:cpu_lx6; fputype:fpu_none; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024),
  92. (controllertypestr:'ESP32_D2WD'; controllerunitstr:'ESP32_D2WD'; cputype:cpu_lx6; fputype:fpu_none; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024),
  93. (controllertypestr:'ESP32_S0WD'; controllerunitstr:'ESP32_S0WD'; cputype:cpu_lx6; fputype:fpu_none; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024)
  94. );
  95. { Supported optimizations, only used for information }
  96. supported_optimizerswitches = genericlevel1optimizerswitches+
  97. genericlevel2optimizerswitches+
  98. genericlevel3optimizerswitches-
  99. { no need to write info about those }
  100. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  101. [{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_loopunroll,cs_opt_tailrecursion,
  102. cs_opt_stackframe,cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath,cs_opt_forcenostackframe];
  103. level1optimizerswitches = genericlevel1optimizerswitches;
  104. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  105. [{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
  106. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{cs_opt_scheduler,}cs_opt_loopunroll];
  107. level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
  108. type
  109. tcpuflags =
  110. (
  111. CPUXTENSA_REGWINDOW
  112. );
  113. tfpuflags =
  114. (
  115. FPUXTENSA_DUMMY
  116. );
  117. const
  118. cpu_capabilities : array[tcputype] of set of tcpuflags =
  119. (
  120. { cpu_none } [],
  121. { cpu_lx106 } [],
  122. { cpu_lx6 } [CPUXTENSA_REGWINDOW]
  123. );
  124. fpu_capabilities : array[tfputype] of set of tfpuflags =
  125. (
  126. { fpu_none } [],
  127. { fpu_soft } [],
  128. { fpu_libgcc } []
  129. );
  130. Implementation
  131. end.