aoptcpu.pas 48 KB

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  1. {
  2. Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
  3. Development Team
  4. This unit implements the ARM optimizer object
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit aoptcpu;
  19. {$i fpcdefs.inc}
  20. { $define DEBUG_AOPTCPU}
  21. Interface
  22. uses cpubase,cgbase,aasmtai,aopt,AoptObj,aoptcpub;
  23. Type
  24. TCpuAsmOptimizer = class(TAsmOptimizer)
  25. { outputs a debug message into the assembler file }
  26. procedure DebugMsg(const s: string; p: tai);
  27. Function GetNextInstructionUsingReg(Current: tai; Var Next: tai;reg : TRegister): Boolean;
  28. function RegInInstruction(Reg: TRegister; p1: tai): Boolean; override;
  29. function RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean; override;
  30. function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; override;
  31. function InvertSkipInstruction(var p: tai): boolean;
  32. { uses the same constructor as TAopObj }
  33. function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
  34. procedure PeepHoleOptPass2;override;
  35. End;
  36. Implementation
  37. uses
  38. cutils,
  39. verbose,
  40. cpuinfo,
  41. aasmbase,aasmcpu,aasmdata,
  42. aoptutils,
  43. globals,globtype,
  44. cgutils;
  45. type
  46. TAsmOpSet = set of TAsmOp;
  47. function CanBeCond(p : tai) : boolean;
  48. begin
  49. result:=(p.typ=ait_instruction) and (taicpu(p).condition=C_None);
  50. end;
  51. function RefsEqual(const r1, r2: treference): boolean;
  52. begin
  53. refsequal :=
  54. (r1.offset = r2.offset) and
  55. (r1.base = r2.base) and
  56. (r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
  57. (r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
  58. (r1.relsymbol = r2.relsymbol) and
  59. (r1.addressmode = r2.addressmode) and
  60. (r1.volatility=[]) and
  61. (r2.volatility=[]);
  62. end;
  63. function MatchOperand(const oper1: TOper; const oper2: TOper): boolean; inline;
  64. begin
  65. result:=oper1.typ=oper2.typ;
  66. if result then
  67. case oper1.typ of
  68. top_const:
  69. Result:=oper1.val = oper2.val;
  70. top_reg:
  71. Result:=oper1.reg = oper2.reg;
  72. top_ref:
  73. Result:=RefsEqual(oper1.ref^, oper2.ref^);
  74. else Result:=false;
  75. end
  76. end;
  77. function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
  78. begin
  79. result := (oper.typ = top_reg) and (oper.reg = reg);
  80. end;
  81. function MatchInstruction(const instr: tai; const op: TAsmOp): boolean;
  82. begin
  83. result :=
  84. (instr.typ = ait_instruction) and
  85. (taicpu(instr).opcode = op);
  86. end;
  87. function MatchInstruction(const instr: tai; const ops: TAsmOpSet): boolean;
  88. begin
  89. result :=
  90. (instr.typ = ait_instruction) and
  91. (taicpu(instr).opcode in ops);
  92. end;
  93. function MatchInstruction(const instr: tai; const ops: TAsmOpSet;opcount : byte): boolean;
  94. begin
  95. result :=
  96. (instr.typ = ait_instruction) and
  97. (taicpu(instr).opcode in ops) and
  98. (taicpu(instr).ops=opcount);
  99. end;
  100. {$ifdef DEBUG_AOPTCPU}
  101. procedure TCpuAsmOptimizer.DebugMsg(const s: string;p : tai);
  102. begin
  103. asml.insertbefore(tai_comment.Create(strpnew(s)), p);
  104. end;
  105. {$else DEBUG_AOPTCPU}
  106. procedure TCpuAsmOptimizer.DebugMsg(const s: string;p : tai);inline;
  107. begin
  108. end;
  109. {$endif DEBUG_AOPTCPU}
  110. function TCpuAsmOptimizer.RegInInstruction(Reg: TRegister; p1: tai): Boolean;
  111. begin
  112. If (p1.typ = ait_instruction) and (taicpu(p1).opcode in [A_MUL,A_MULS,A_FMUL,A_FMULS,A_FMULSU]) and
  113. ((getsupreg(reg)=RS_R0) or (getsupreg(reg)=RS_R1)) then
  114. Result:=true
  115. else if (p1.typ = ait_instruction) and (taicpu(p1).opcode=A_MOVW) and
  116. ((TRegister(ord(taicpu(p1).oper[0]^.reg)+1)=reg) or (TRegister(ord(taicpu(p1).oper[1]^.reg)+1)=reg) or
  117. (taicpu(p1).oper[0]^.reg=reg) or (taicpu(p1).oper[1]^.reg=reg)) then
  118. Result:=true
  119. else
  120. Result:=inherited RegInInstruction(Reg, p1);
  121. end;
  122. function TCpuAsmOptimizer.GetNextInstructionUsingReg(Current: tai;
  123. var Next: tai; reg: TRegister): Boolean;
  124. begin
  125. Next:=Current;
  126. repeat
  127. Result:=GetNextInstruction(Next,Next);
  128. until not(cs_opt_level3 in current_settings.optimizerswitches) or not(Result) or (Next.typ<>ait_instruction) or (RegInInstruction(reg,Next)) or
  129. (is_calljmp(taicpu(Next).opcode));
  130. end;
  131. function TCpuAsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
  132. var
  133. p: taicpu;
  134. begin
  135. if not assigned(hp) or
  136. (hp.typ <> ait_instruction) then
  137. begin
  138. Result := false;
  139. exit;
  140. end;
  141. p := taicpu(hp);
  142. Result := ((p.opcode in [A_LDI,A_MOV,A_LDS]) and (reg=p.oper[0]^.reg) and ((p.oper[1]^.typ<>top_reg) or (reg<>p.oper[0]^.reg))) or
  143. ((p.opcode in [A_LD,A_LDD,A_LPM]) and (reg=p.oper[0]^.reg) and not(RegInRef(reg,p.oper[1]^.ref^))) or
  144. ((p.opcode in [A_MOVW]) and ((reg=p.oper[0]^.reg) or (TRegister(ord(reg)+1)=p.oper[0]^.reg)) and not(reg=p.oper[1]^.reg) and not(TRegister(ord(reg)+1)=p.oper[1]^.reg)) or
  145. ((p.opcode in [A_POP]) and (reg=p.oper[0]^.reg));
  146. end;
  147. function TCpuAsmOptimizer.InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
  148. var
  149. p: taicpu;
  150. i: longint;
  151. begin
  152. Result := false;
  153. if not (assigned(hp) and (hp.typ = ait_instruction)) then
  154. exit;
  155. p:=taicpu(hp);
  156. i:=0;
  157. { we do not care about the stack pointer }
  158. if p.opcode in [A_POP] then
  159. exit;
  160. { first operand only written?
  161. then skip it }
  162. if p.opcode in [A_MOV,A_LD,A_LDD,A_LDS,A_LPM,A_LDI,A_MOVW] then
  163. i:=1;
  164. while i<p.ops do
  165. begin
  166. case p.oper[i]^.typ of
  167. top_reg:
  168. Result := (p.oper[i]^.reg = reg) or
  169. { MOVW }
  170. ((i=1) and (p.opcode=A_MOVW) and (getsupreg(p.oper[0]^.reg)+1=getsupreg(reg)));
  171. top_ref:
  172. Result :=
  173. (p.oper[i]^.ref^.base = reg) or
  174. (p.oper[i]^.ref^.index = reg);
  175. end;
  176. { Bailout if we found something }
  177. if Result then
  178. exit;
  179. Inc(i);
  180. end;
  181. end;
  182. {
  183. Turns
  184. sbis ?
  185. jmp .Lx
  186. op
  187. .Lx:
  188. Into
  189. sbic ?
  190. op
  191. For all types of skip instructions
  192. }
  193. function TCpuAsmOptimizer.InvertSkipInstruction(var p: tai): boolean;
  194. function GetNextInstructionWithoutLabel(p: tai; var next: tai): boolean;
  195. begin
  196. repeat
  197. result:=GetNextInstruction(p,next);
  198. p:=next;
  199. until
  200. (not result) or
  201. (not assigned(next)) or
  202. (next.typ in [ait_instruction]);
  203. result:=assigned(next) and (next.typ in [ait_instruction]);
  204. end;
  205. var
  206. hp1, hp2, hp3: tai;
  207. s: string;
  208. begin
  209. result:=false;
  210. if GetNextInstruction(taicpu(p),hp1) and
  211. (hp1.typ=ait_instruction) and
  212. (taicpu(hp1).opcode in [A_RJMP,A_JMP]) and
  213. (taicpu(hp1).ops=1) and
  214. (taicpu(hp1).oper[0]^.typ=top_ref) and
  215. (taicpu(hp1).oper[0]^.ref^.offset=0) and
  216. (taicpu(hp1).oper[0]^.ref^.symbol is TAsmLabel) and
  217. GetNextInstructionWithoutLabel(hp1,hp2) and
  218. (hp2.typ=ait_instruction) and
  219. (not taicpu(hp2).is_jmp) and
  220. GetNextInstruction(hp2,hp3) and
  221. FindLabel(TAsmLabel(taicpu(hp1).oper[0]^.ref^.symbol),hp3) then
  222. begin
  223. DebugMsg('SkipJump2InvertedSkip', p);
  224. case taicpu(p).opcode of
  225. A_SBIS: taicpu(p).opcode:=A_SBIC;
  226. A_SBIC: taicpu(p).opcode:=A_SBIS;
  227. A_SBRS: taicpu(p).opcode:=A_SBRC;
  228. A_SBRC: taicpu(p).opcode:=A_SBRS;
  229. end;
  230. TAsmLabel(taicpu(hp1).oper[0]^.ref^.symbol).decrefs;
  231. asml.remove(hp1);
  232. hp1.free;
  233. end;
  234. end;
  235. function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
  236. var
  237. hp1,hp2,hp3,hp4,hp5: tai;
  238. alloc, dealloc: tai_regalloc;
  239. i: integer;
  240. l: TAsmLabel;
  241. begin
  242. result := false;
  243. case p.typ of
  244. ait_instruction:
  245. begin
  246. {
  247. change
  248. <op> reg,x,y
  249. cp reg,r1
  250. into
  251. <op>s reg,x,y
  252. }
  253. { this optimization can applied only to the currently enabled operations because
  254. the other operations do not update all flags and FPC does not track flag usage }
  255. if MatchInstruction(p, [A_ADC,A_ADD,A_AND,A_ANDI,A_ASR,A_COM,A_DEC,A_EOR,
  256. A_INC,A_LSL,A_LSR,
  257. A_OR,A_ORI,A_ROL,A_ROR,A_SBC,A_SBCI,A_SUB,A_SUBI]) and
  258. GetNextInstruction(p, hp1) and
  259. ((MatchInstruction(hp1, A_CP) and
  260. (((taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
  261. (taicpu(hp1).oper[1]^.reg = GetDefaultZeroReg)) or
  262. ((taicpu(p).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
  263. (taicpu(hp1).oper[0]^.reg = GetDefaultZeroReg) and
  264. (taicpu(p).opcode in [A_ADC,A_ADD,A_AND,A_ANDI,A_ASR,A_COM,A_EOR,
  265. A_LSL,A_LSR,
  266. A_OR,A_ORI,A_ROL,A_ROR,A_SUB,A_SBI])))) or
  267. (MatchInstruction(hp1, A_CPI) and
  268. (taicpu(p).opcode = A_ANDI) and
  269. (taicpu(p).oper[1]^.typ=top_const) and
  270. (taicpu(hp1).oper[1]^.typ=top_const) and
  271. (taicpu(p).oper[1]^.val=taicpu(hp1).oper[1]^.val))) and
  272. GetNextInstruction(hp1, hp2) and
  273. { be careful here, following instructions could use other flags
  274. however after a jump fpc never depends on the value of flags }
  275. { All above instructions set Z and N according to the following
  276. Z := result = 0;
  277. N := result[31];
  278. EQ = Z=1; NE = Z=0;
  279. MI = N=1; PL = N=0; }
  280. MatchInstruction(hp2, A_BRxx) and
  281. ((taicpu(hp2).condition in [C_EQ,C_NE,C_MI,C_PL]) or
  282. { sub/sbc set all flags }
  283. (taicpu(p).opcode in [A_SUB,A_SBI])){ and
  284. no flag allocation tracking implemented yet on avr
  285. assigned(FindRegDealloc(NR_DEFAULTFLAGS,tai(hp2.Next)))} then
  286. begin
  287. { move flag allocation if possible }
  288. { no flag allocation tracking implemented yet on avr
  289. GetLastInstruction(hp1, hp2);
  290. hp2:=FindRegAlloc(NR_DEFAULTFLAGS,tai(hp2.Next));
  291. if assigned(hp2) then
  292. begin
  293. asml.Remove(hp2);
  294. asml.insertbefore(hp2, p);
  295. end;
  296. }
  297. // If we compare to the same value we are masking then invert the comparison
  298. if (taicpu(hp1).opcode=A_CPI) or
  299. { sub/sbc with reverted? }
  300. ((taicpu(hp1).oper[0]^.reg = GetDefaultZeroReg) and (taicpu(p).opcode in [A_SUB,A_SBI])) then
  301. taicpu(hp2).condition:=inverse_cond(taicpu(hp2).condition);
  302. asml.InsertBefore(tai_regalloc.alloc(NR_DEFAULTFLAGS,p), p);
  303. asml.InsertAfter(tai_regalloc.dealloc(NR_DEFAULTFLAGS,hp2), hp2);
  304. IncludeRegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs);
  305. DebugMsg('Peephole OpCp2Op performed', p);
  306. asml.remove(hp1);
  307. hp1.free;
  308. Result:=true;
  309. end
  310. else
  311. case taicpu(p).opcode of
  312. A_LDI:
  313. begin
  314. { turn
  315. ldi reg0, imm
  316. <op> reg1, reg0
  317. dealloc reg0
  318. into
  319. <op>i reg1, imm
  320. }
  321. if MatchOpType(taicpu(p),top_reg,top_const) and
  322. GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
  323. MatchInstruction(hp1,[A_CP,A_MOV,A_AND,A_SUB],2) and
  324. (not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
  325. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  326. (getsupreg(taicpu(hp1).oper[0]^.reg) in [16..31]) and
  327. (taicpu(hp1).oper[1]^.reg=taicpu(p).oper[0]^.reg) and
  328. not(MatchOperand(taicpu(hp1).oper[0]^,taicpu(hp1).oper[1]^)) then
  329. begin
  330. TransferUsedRegs(TmpUsedRegs);
  331. UpdateUsedRegs(TmpUsedRegs,tai(p.next));
  332. UpdateUsedRegs(TmpUsedRegs,tai(hp1.next));
  333. if not(RegUsedAfterInstruction(taicpu(hp1).oper[1]^.reg, hp1, TmpUsedRegs)) then
  334. begin
  335. case taicpu(hp1).opcode of
  336. A_CP:
  337. taicpu(hp1).opcode:=A_CPI;
  338. A_MOV:
  339. taicpu(hp1).opcode:=A_LDI;
  340. A_AND:
  341. taicpu(hp1).opcode:=A_ANDI;
  342. A_SUB:
  343. taicpu(hp1).opcode:=A_SUBI;
  344. else
  345. internalerror(2016111901);
  346. end;
  347. taicpu(hp1).loadconst(1, taicpu(p).oper[1]^.val);
  348. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  349. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next));
  350. if assigned(alloc) and assigned(dealloc) then
  351. begin
  352. asml.Remove(alloc);
  353. alloc.Free;
  354. asml.Remove(dealloc);
  355. dealloc.Free;
  356. end;
  357. DebugMsg('Peephole LdiOp2Opi performed', p);
  358. RemoveCurrentP(p);
  359. end;
  360. end;
  361. end;
  362. A_STS:
  363. if (taicpu(p).oper[0]^.ref^.symbol=nil) and
  364. (taicpu(p).oper[0]^.ref^.relsymbol=nil) and
  365. (getsupreg(taicpu(p).oper[0]^.ref^.base)=RS_NO) and
  366. (getsupreg(taicpu(p).oper[0]^.ref^.index)=RS_NO) and
  367. (taicpu(p).oper[0]^.ref^.addressmode=AM_UNCHANGED) and
  368. (((CPUAVR_NOMEMMAPPED_REGS in cpu_capabilities[current_settings.cputype]) and
  369. (taicpu(p).oper[0]^.ref^.offset>=0) and
  370. (taicpu(p).oper[0]^.ref^.offset<=63)) or
  371. (not(CPUAVR_NOMEMMAPPED_REGS in cpu_capabilities[current_settings.cputype]) and
  372. (taicpu(p).oper[0]^.ref^.offset>=32) and
  373. (taicpu(p).oper[0]^.ref^.offset<=95))) then
  374. begin
  375. DebugMsg('Peephole Sts2Out performed', p);
  376. taicpu(p).opcode:=A_OUT;
  377. if CPUAVR_NOMEMMAPPED_REGS in cpu_capabilities[current_settings.cputype] then
  378. taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset)
  379. else
  380. taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset-32);
  381. end;
  382. A_LDS:
  383. if (taicpu(p).oper[1]^.ref^.symbol=nil) and
  384. (taicpu(p).oper[1]^.ref^.relsymbol=nil) and
  385. (getsupreg(taicpu(p).oper[1]^.ref^.base)=RS_NO) and
  386. (getsupreg(taicpu(p).oper[1]^.ref^.index)=RS_NO) and
  387. (taicpu(p).oper[1]^.ref^.addressmode=AM_UNCHANGED) and
  388. (((CPUAVR_NOMEMMAPPED_REGS in cpu_capabilities[current_settings.cputype]) and
  389. (taicpu(p).oper[1]^.ref^.offset>=0) and
  390. (taicpu(p).oper[1]^.ref^.offset<=63)) or
  391. (not(CPUAVR_NOMEMMAPPED_REGS in cpu_capabilities[current_settings.cputype]) and
  392. (taicpu(p).oper[1]^.ref^.offset>=32) and
  393. (taicpu(p).oper[1]^.ref^.offset<=95))) then
  394. begin
  395. DebugMsg('Peephole Lds2In performed', p);
  396. taicpu(p).opcode:=A_IN;
  397. if CPUAVR_NOMEMMAPPED_REGS in cpu_capabilities[current_settings.cputype] then
  398. taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset)
  399. else
  400. taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset-32);
  401. end;
  402. A_IN:
  403. if GetNextInstruction(p,hp1) then
  404. begin
  405. {
  406. in rX,Y
  407. ori rX,n
  408. out Y,rX
  409. into
  410. sbi rX,lg(n)
  411. }
  412. if (taicpu(p).oper[1]^.val<=31) and
  413. MatchInstruction(hp1,A_ORI) and
  414. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) and
  415. (PopCnt(byte(taicpu(hp1).oper[1]^.val))=1) and
  416. GetNextInstruction(hp1,hp2) and
  417. MatchInstruction(hp2,A_OUT) and
  418. MatchOperand(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) and
  419. MatchOperand(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) then
  420. begin
  421. DebugMsg('Peephole InOriOut2Sbi performed', p);
  422. taicpu(p).opcode:=A_SBI;
  423. taicpu(p).loadconst(0,taicpu(p).oper[1]^.val);
  424. taicpu(p).loadconst(1,BsrByte(taicpu(hp1).oper[1]^.val));
  425. asml.Remove(hp1);
  426. hp1.Free;
  427. asml.Remove(hp2);
  428. hp2.Free;
  429. result:=true;
  430. end
  431. {
  432. in rX,Y
  433. andi rX,not(n)
  434. out Y,rX
  435. into
  436. cbi rX,lg(n)
  437. }
  438. else if (taicpu(p).oper[1]^.val<=31) and
  439. MatchInstruction(hp1,A_ANDI) and
  440. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) and
  441. (PopCnt(byte(not(taicpu(hp1).oper[1]^.val)))=1) and
  442. GetNextInstruction(hp1,hp2) and
  443. MatchInstruction(hp2,A_OUT) and
  444. MatchOperand(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) and
  445. MatchOperand(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) then
  446. begin
  447. DebugMsg('Peephole InAndiOut2Cbi performed', p);
  448. taicpu(p).opcode:=A_CBI;
  449. taicpu(p).loadconst(0,taicpu(p).oper[1]^.val);
  450. taicpu(p).loadconst(1,BsrByte(not(taicpu(hp1).oper[1]^.val)));
  451. asml.Remove(hp1);
  452. hp1.Free;
  453. asml.Remove(hp2);
  454. hp2.Free;
  455. result:=true;
  456. end
  457. {
  458. in rX,Y
  459. andi rX,n
  460. breq/brne L1
  461. into
  462. sbis/sbic Y,lg(n)
  463. jmp L1
  464. .Ltemp:
  465. }
  466. else if (taicpu(p).oper[1]^.val<=31) and
  467. MatchInstruction(hp1,A_ANDI) and
  468. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) and
  469. (PopCnt(byte(taicpu(hp1).oper[1]^.val))=1) and
  470. GetNextInstruction(hp1,hp2) and
  471. MatchInstruction(hp2,A_BRxx) and
  472. (taicpu(hp2).condition in [C_EQ,C_NE]) then
  473. begin
  474. if taicpu(hp2).condition=C_EQ then
  475. taicpu(p).opcode:=A_SBIS
  476. else
  477. taicpu(p).opcode:=A_SBIC;
  478. DebugMsg('Peephole InAndiBrx2SbixJmp performed', p);
  479. taicpu(p).loadconst(0,taicpu(p).oper[1]^.val);
  480. taicpu(p).loadconst(1,BsrByte(taicpu(hp1).oper[1]^.val));
  481. asml.Remove(hp1);
  482. hp1.Free;
  483. taicpu(hp2).condition:=C_None;
  484. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  485. taicpu(hp2).opcode:=A_JMP
  486. else
  487. taicpu(hp2).opcode:=A_RJMP;
  488. current_asmdata.getjumplabel(l);
  489. l.increfs;
  490. asml.InsertAfter(tai_label.create(l), hp2);
  491. result:=true;
  492. end;
  493. end;
  494. A_SBRS,
  495. A_SBRC:
  496. begin
  497. {
  498. Turn
  499. in rx, y
  500. sbr* rx, z
  501. Into
  502. sbi* y, z
  503. }
  504. if (taicpu(p).ops=2) and
  505. (taicpu(p).oper[0]^.typ=top_reg) and
  506. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(p.next))) and
  507. GetLastInstruction(p,hp1) and
  508. (hp1.typ=ait_instruction) and
  509. (taicpu(hp1).opcode=A_IN) and
  510. (taicpu(hp1).ops=2) and
  511. (taicpu(hp1).oper[1]^.typ=top_const) and
  512. (taicpu(hp1).oper[1]^.val in [0..31]) and
  513. MatchOperand(taicpu(hp1).oper[0]^,taicpu(p).oper[0]^.reg) and
  514. (not RegModifiedBetween(taicpu(p).oper[0]^.reg, hp1, p)) then
  515. begin
  516. if taicpu(p).opcode=A_SBRS then
  517. taicpu(p).opcode:=A_SBIS
  518. else
  519. taicpu(p).opcode:=A_SBIC;
  520. taicpu(p).loadconst(0, taicpu(hp1).oper[1]^.val);
  521. DebugMsg('Peephole InSbrx2Sbix performed', p);
  522. asml.Remove(hp1);
  523. hp1.free;
  524. result:=true;
  525. end;
  526. if InvertSkipInstruction(p) then
  527. result:=true;
  528. end;
  529. A_ANDI:
  530. begin
  531. {
  532. Turn
  533. andi rx, #pow2
  534. brne l
  535. <op>
  536. l:
  537. Into
  538. sbrs rx, #(1 shl imm)
  539. <op>
  540. l:
  541. }
  542. if (taicpu(p).ops=2) and
  543. (taicpu(p).oper[1]^.typ=top_const) and
  544. ispowerof2(taicpu(p).oper[1]^.val,i) and
  545. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(p.next))) and
  546. GetNextInstruction(p,hp1) and
  547. (hp1.typ=ait_instruction) and
  548. (taicpu(hp1).opcode=A_BRxx) and
  549. (taicpu(hp1).condition in [C_EQ,C_NE]) and
  550. (taicpu(hp1).ops>0) and
  551. (taicpu(hp1).oper[0]^.typ = top_ref) and
  552. (taicpu(hp1).oper[0]^.ref^.symbol is TAsmLabel) and
  553. GetNextInstruction(hp1,hp2) and
  554. (hp2.typ=ait_instruction) and
  555. GetNextInstruction(hp2,hp3) and
  556. (hp3.typ=ait_label) and
  557. (taicpu(hp1).oper[0]^.ref^.symbol=tai_label(hp3).labsym) then
  558. begin
  559. DebugMsg('Peephole AndiBr2Sbr performed', p);
  560. taicpu(p).oper[1]^.val:=i;
  561. if taicpu(hp1).condition=C_NE then
  562. taicpu(p).opcode:=A_SBRS
  563. else
  564. taicpu(p).opcode:=A_SBRC;
  565. asml.Remove(hp1);
  566. hp1.free;
  567. result:=true;
  568. end
  569. {
  570. Remove
  571. andi rx, #y
  572. dealloc rx
  573. }
  574. else if (taicpu(p).ops=2) and
  575. (taicpu(p).oper[0]^.typ=top_reg) and
  576. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(p.next))) and
  577. (assigned(FindRegDeAlloc(NR_DEFAULTFLAGS,tai(p.Next))) or
  578. (not RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs))) then
  579. begin
  580. DebugMsg('Redundant Andi removed', p);
  581. result:=RemoveCurrentP(p);
  582. end;
  583. end;
  584. A_ADD:
  585. begin
  586. if (taicpu(p).oper[1]^.reg=GetDefaultZeroReg) and
  587. GetNextInstruction(p, hp1) and
  588. MatchInstruction(hp1,A_ADC) then
  589. begin
  590. DebugMsg('Peephole AddAdc2Add performed', p);
  591. result:=RemoveCurrentP(p);
  592. end;
  593. end;
  594. A_SUB:
  595. begin
  596. if (taicpu(p).oper[1]^.reg=GetDefaultZeroReg) and
  597. GetNextInstruction(p, hp1) and
  598. MatchInstruction(hp1,A_SBC) then
  599. begin
  600. DebugMsg('Peephole SubSbc2Sub performed', p);
  601. taicpu(hp1).opcode:=A_SUB;
  602. result:=RemoveCurrentP(p);
  603. end;
  604. end;
  605. A_CLR:
  606. begin
  607. { turn the common
  608. clr rX
  609. mov/ld rX, rY
  610. into
  611. mov/ld rX, rY
  612. }
  613. if (taicpu(p).ops=1) and
  614. (taicpu(p).oper[0]^.typ=top_reg) and
  615. GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
  616. (not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
  617. (hp1.typ=ait_instruction) and
  618. (taicpu(hp1).opcode in [A_MOV,A_LD]) and
  619. (taicpu(hp1).ops>0) and
  620. (taicpu(hp1).oper[0]^.typ=top_reg) and
  621. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) then
  622. begin
  623. DebugMsg('Peephole ClrMov2Mov performed', p);
  624. result:=RemoveCurrentP(p);
  625. end
  626. { turn
  627. clr rX
  628. ...
  629. adc rY, rX
  630. into
  631. ...
  632. adc rY, r1
  633. }
  634. else if (taicpu(p).ops=1) and
  635. (taicpu(p).oper[0]^.typ=top_reg) and
  636. GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
  637. (not RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp1)) and
  638. (hp1.typ=ait_instruction) and
  639. (taicpu(hp1).opcode in [A_ADC,A_SBC]) and
  640. (taicpu(hp1).ops=2) and
  641. (taicpu(hp1).oper[1]^.typ=top_reg) and
  642. (taicpu(hp1).oper[1]^.reg=taicpu(p).oper[0]^.reg) and
  643. (taicpu(hp1).oper[0]^.reg<>taicpu(p).oper[0]^.reg) and
  644. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) then
  645. begin
  646. DebugMsg('Peephole ClrAdc2Adc performed', p);
  647. taicpu(hp1).oper[1]^.reg:=GetDefaultZeroReg;
  648. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  649. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next));
  650. if assigned(alloc) and assigned(dealloc) then
  651. begin
  652. asml.Remove(alloc);
  653. alloc.Free;
  654. asml.Remove(dealloc);
  655. dealloc.Free;
  656. end;
  657. result:=RemoveCurrentP(p);
  658. end;
  659. end;
  660. A_PUSH:
  661. begin
  662. { turn
  663. push reg0
  664. push reg1
  665. pop reg3
  666. pop reg2
  667. into
  668. movw reg2,reg0
  669. or
  670. mov reg3,reg1
  671. mov reg2,reg0
  672. }
  673. if GetNextInstruction(p,hp1) and
  674. MatchInstruction(hp1,A_PUSH) and
  675. GetNextInstruction(hp1,hp2) and
  676. MatchInstruction(hp2,A_POP) and
  677. GetNextInstruction(hp2,hp3) and
  678. MatchInstruction(hp3,A_POP) then
  679. begin
  680. if (CPUAVR_HAS_MOVW in cpu_capabilities[current_settings.cputype]) and
  681. (getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(p).oper[0]^.reg)+1) and
  682. ((getsupreg(taicpu(p).oper[0]^.reg) mod 2)=0) and
  683. (getsupreg(taicpu(hp2).oper[0]^.reg)=getsupreg(taicpu(hp3).oper[0]^.reg)+1) and
  684. ((getsupreg(taicpu(hp3).oper[0]^.reg) mod 2)=0) then
  685. begin
  686. DebugMsg('Peephole PushPushPopPop2Movw performed', p);
  687. taicpu(hp3).ops:=2;
  688. taicpu(hp3).opcode:=A_MOVW;
  689. taicpu(hp3).loadreg(1, taicpu(p).oper[0]^.reg);
  690. RemoveCurrentP(p);
  691. RemoveCurrentP(p);
  692. result:=RemoveCurrentP(p);
  693. end
  694. else
  695. begin
  696. DebugMsg('Peephole PushPushPopPop2MovMov performed', p);
  697. taicpu(p).ops:=2;
  698. taicpu(p).opcode:=A_MOV;
  699. taicpu(hp1).ops:=2;
  700. taicpu(hp1).opcode:=A_MOV;
  701. taicpu(p).loadreg(1, taicpu(p).oper[0]^.reg);
  702. taicpu(p).loadreg(0, taicpu(hp3).oper[0]^.reg);
  703. taicpu(hp1).loadreg(1, taicpu(hp1).oper[0]^.reg);
  704. taicpu(hp1).loadreg(0, taicpu(hp2).oper[0]^.reg);
  705. { life range of reg2 and reg3 is increased, fix register allocation entries }
  706. TransferUsedRegs(TmpUsedRegs);
  707. UpdateUsedRegs(TmpUsedRegs,tai(p.Next));
  708. AllocRegBetween(taicpu(hp2).oper[0]^.reg,hp1,hp2,TmpUsedRegs);
  709. TransferUsedRegs(TmpUsedRegs);
  710. AllocRegBetween(taicpu(hp3).oper[0]^.reg,p,hp3,TmpUsedRegs);
  711. IncludeRegInUsedRegs(taicpu(hp3).oper[0]^.reg,UsedRegs);
  712. UpdateUsedRegs(tai(p.Next));
  713. asml.Remove(hp2);
  714. hp2.Free;
  715. asml.Remove(hp3);
  716. hp3.Free;
  717. result:=true;
  718. end
  719. end;
  720. end;
  721. A_CALL:
  722. if (cs_opt_level4 in current_settings.optimizerswitches) and
  723. GetNextInstruction(p,hp1) and
  724. MatchInstruction(hp1,A_RET) then
  725. begin
  726. DebugMsg('Peephole CallReg2Jmp performed', p);
  727. taicpu(p).opcode:=A_JMP;
  728. asml.Remove(hp1);
  729. hp1.Free;
  730. result:=true;
  731. end;
  732. A_RCALL:
  733. if (cs_opt_level4 in current_settings.optimizerswitches) and
  734. GetNextInstruction(p,hp1) and
  735. MatchInstruction(hp1,A_RET) then
  736. begin
  737. DebugMsg('Peephole RCallReg2RJmp performed', p);
  738. taicpu(p).opcode:=A_RJMP;
  739. asml.Remove(hp1);
  740. hp1.Free;
  741. result:=true;
  742. end;
  743. A_MOV:
  744. begin
  745. { change
  746. mov reg0, reg1
  747. dealloc reg0
  748. into
  749. dealloc reg0
  750. }
  751. if MatchOpType(taicpu(p),top_reg,top_reg) then
  752. begin
  753. TransferUsedRegs(TmpUsedRegs);
  754. UpdateUsedRegs(TmpUsedRegs,tai(p.Next));
  755. if not(RegInUsedRegs(taicpu(p).oper[0]^.reg,TmpUsedRegs)) and
  756. { reg. allocation information before calls is not perfect, so don't do this before
  757. calls/icalls }
  758. GetNextInstruction(p,hp1) and
  759. not(MatchInstruction(hp1,[A_CALL,A_RCALL])) then
  760. begin
  761. DebugMsg('Peephole Mov2Nop performed', p);
  762. result:=RemoveCurrentP(p);
  763. exit;
  764. end;
  765. end;
  766. { turn
  767. mov reg0, reg1
  768. <op> reg2,reg0
  769. dealloc reg0
  770. into
  771. <op> reg2,reg1
  772. }
  773. if MatchOpType(taicpu(p),top_reg,top_reg) and
  774. GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
  775. (not RegModifiedBetween(taicpu(p).oper[1]^.reg, p, hp1)) and
  776. (MatchInstruction(hp1,[A_PUSH,A_MOV,A_CP,A_CPC,A_ADD,A_SUB,A_ADC,A_SBC,A_EOR,A_AND,A_OR,
  777. A_OUT,A_IN]) or
  778. { the reference register of ST/STD cannot be replaced }
  779. (MatchInstruction(hp1,[A_STD,A_ST,A_STS]) and (MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^)))) and
  780. (not RegModifiedByInstruction(taicpu(p).oper[0]^.reg, hp1)) and
  781. {(taicpu(hp1).ops=1) and
  782. (taicpu(hp1).oper[0]^.typ = top_reg) and
  783. (taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg) and }
  784. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) then
  785. begin
  786. DebugMsg('Peephole MovOp2Op performed', p);
  787. for i := 0 to taicpu(hp1).ops-1 do
  788. if taicpu(hp1).oper[i]^.typ=top_reg then
  789. if taicpu(hp1).oper[i]^.reg=taicpu(p).oper[0]^.reg then
  790. taicpu(hp1).oper[i]^.reg:=taicpu(p).oper[1]^.reg;
  791. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  792. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp1.Next));
  793. if assigned(alloc) and assigned(dealloc) then
  794. begin
  795. asml.Remove(alloc);
  796. alloc.Free;
  797. asml.Remove(dealloc);
  798. dealloc.Free;
  799. end;
  800. { life range of reg1 is increased }
  801. AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp1,usedregs);
  802. { p will be removed, update used register as we continue
  803. with the next instruction after p }
  804. result:=RemoveCurrentP(p);
  805. end
  806. { remove
  807. mov reg0,reg0
  808. }
  809. else if (taicpu(p).ops=2) and
  810. (taicpu(p).oper[0]^.typ = top_reg) and
  811. (taicpu(p).oper[1]^.typ = top_reg) and
  812. (taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  813. begin
  814. DebugMsg('Peephole RedundantMov performed', p);
  815. result:=RemoveCurrentP(p);
  816. end
  817. {
  818. Turn
  819. mov rx,ry
  820. op rx,rz
  821. mov ry, rx
  822. Into
  823. op ry,rz
  824. }
  825. else if (taicpu(p).ops=2) and
  826. MatchOpType(taicpu(p),top_reg,top_reg) and
  827. GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
  828. (hp1.typ=ait_instruction) and
  829. (taicpu(hp1).ops >= 1) and
  830. (taicpu(hp1).oper[0]^.typ = top_reg) and
  831. GetNextInstructionUsingReg(hp1,hp2,taicpu(hp1).oper[0]^.reg) and
  832. MatchInstruction(hp2,A_MOV) and
  833. MatchOpType(taicpu(hp2),top_reg,top_reg) and
  834. (taicpu(hp2).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  835. (taicpu(hp2).oper[1]^.reg = taicpu(hp1).oper[0]^.reg) and
  836. (taicpu(hp2).oper[1]^.reg = taicpu(p).oper[0]^.reg) and
  837. (not RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp2)) and
  838. (taicpu(hp1).opcode in [A_ADD,A_ADC,A_SUB,A_SBC,A_AND,A_OR,A_EOR,
  839. A_INC,A_DEC,
  840. A_LSL,A_LSR,A_ASR,A_ROR,A_ROL]) and
  841. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg, tai(hp2.Next))) then
  842. begin
  843. DebugMsg('Peephole MovOpMov2Op performed', p);
  844. if (taicpu(hp1).ops=2) and
  845. (taicpu(hp1).oper[1]^.typ=top_reg) and
  846. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  847. taicpu(hp1).oper[1]^.reg:=taicpu(p).oper[1]^.reg;
  848. taicpu(hp1).oper[0]^.reg:=taicpu(p).oper[1]^.reg;
  849. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  850. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp2.Next));
  851. if assigned(alloc) and assigned(dealloc) then
  852. begin
  853. asml.Remove(alloc);
  854. alloc.Free;
  855. asml.Remove(dealloc);
  856. dealloc.Free;
  857. end;
  858. asml.remove(hp2);
  859. hp2.free;
  860. result:=RemoveCurrentP(p);
  861. end
  862. {
  863. Turn
  864. mov rx,ry
  865. op rx,rw
  866. mov rw,rx
  867. Into
  868. op rw,ry
  869. }
  870. else if (taicpu(p).ops=2) and
  871. MatchOpType(taicpu(p),top_reg,top_reg) and
  872. GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
  873. (hp1.typ=ait_instruction) and
  874. (taicpu(hp1).ops = 2) and
  875. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  876. GetNextInstructionUsingReg(hp1,hp2,taicpu(hp1).oper[0]^.reg) and
  877. (hp2.typ=ait_instruction) and
  878. (taicpu(hp2).opcode=A_MOV) and
  879. MatchOpType(taicpu(hp2),top_reg,top_reg) and
  880. (taicpu(hp2).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
  881. (taicpu(hp2).oper[1]^.reg = taicpu(hp1).oper[0]^.reg) and
  882. (taicpu(hp2).oper[1]^.reg = taicpu(p).oper[0]^.reg) and
  883. (not RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) and
  884. (taicpu(hp1).opcode in [A_ADD,A_ADC,A_AND,A_OR,A_EOR]) and
  885. assigned(FindRegDeAlloc(taicpu(p).oper[0]^.reg, tai(hp2.Next))) then
  886. begin
  887. DebugMsg('Peephole MovOpMov2Op2 performed', p);
  888. taicpu(hp1).oper[0]^.reg:=taicpu(hp2).oper[0]^.reg;
  889. taicpu(hp1).oper[1]^.reg:=taicpu(p).oper[1]^.reg;
  890. alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.Previous));
  891. dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(hp2.Next));
  892. if assigned(alloc) and assigned(dealloc) then
  893. begin
  894. asml.Remove(alloc);
  895. alloc.Free;
  896. asml.Remove(dealloc);
  897. dealloc.Free;
  898. end;
  899. result:=RemoveCurrentP(p);
  900. asml.remove(hp2);
  901. hp2.free;
  902. end
  903. { fold
  904. mov reg2,reg0
  905. mov reg3,reg1
  906. to
  907. movw reg2,reg0
  908. }
  909. else if (CPUAVR_HAS_MOVW in cpu_capabilities[current_settings.cputype]) and
  910. (taicpu(p).ops=2) and
  911. (taicpu(p).oper[0]^.typ = top_reg) and
  912. (taicpu(p).oper[1]^.typ = top_reg) and
  913. getnextinstruction(p,hp1) and
  914. (hp1.typ = ait_instruction) and
  915. (taicpu(hp1).opcode = A_MOV) and
  916. (taicpu(hp1).ops=2) and
  917. (taicpu(hp1).oper[0]^.typ = top_reg) and
  918. (taicpu(hp1).oper[1]^.typ = top_reg) and
  919. (getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(p).oper[0]^.reg)+1) and
  920. ((getsupreg(taicpu(p).oper[0]^.reg) mod 2)=0) and
  921. ((getsupreg(taicpu(p).oper[1]^.reg) mod 2)=0) and
  922. (getsupreg(taicpu(hp1).oper[1]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)+1) then
  923. begin
  924. DebugMsg('Peephole MovMov2Movw performed', p);
  925. alloc:=FindRegAllocBackward(taicpu(hp1).oper[0]^.reg,tai(hp1.Previous));
  926. if assigned(alloc) then
  927. begin
  928. asml.Remove(alloc);
  929. asml.InsertBefore(alloc,p);
  930. { proper book keeping of currently used registers }
  931. IncludeRegInUsedRegs(taicpu(hp1).oper[0]^.reg,UsedRegs);
  932. end;
  933. taicpu(p).opcode:=A_MOVW;
  934. asml.remove(hp1);
  935. hp1.free;
  936. result:=true;
  937. end
  938. {
  939. This removes the first mov from
  940. mov rX,...
  941. mov rX,...
  942. }
  943. else if GetNextInstruction(p,hp1) and MatchInstruction(hp1,A_MOV) then
  944. while MatchInstruction(hp1,A_MOV) and
  945. MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^) and
  946. { don't remove the first mov if the second is a mov rX,rX }
  947. not(MatchOperand(taicpu(hp1).oper[0]^,taicpu(hp1).oper[1]^)) do
  948. begin
  949. DebugMsg('Peephole MovMov2Mov performed', p);
  950. result:=RemoveCurrentP(p);
  951. GetNextInstruction(hp1,hp1);
  952. if not assigned(hp1) then
  953. break;
  954. end;
  955. end;
  956. A_SBIC,
  957. A_SBIS:
  958. begin
  959. {
  960. Turn
  961. sbic/sbis X, y
  962. jmp .L1
  963. op
  964. .L1:
  965. into
  966. sbis/sbic X,y
  967. op
  968. .L1:
  969. }
  970. if InvertSkipInstruction(p) then
  971. result:=true
  972. {
  973. Turn
  974. sbiX X, y
  975. jmp .L1
  976. jmp .L2
  977. .L1:
  978. op
  979. .L2:
  980. into
  981. sbiX X,y
  982. .L1:
  983. op
  984. .L2:
  985. }
  986. else if GetNextInstruction(p, hp1) and
  987. (hp1.typ=ait_instruction) and
  988. (taicpu(hp1).opcode in [A_JMP,A_RJMP]) and
  989. (taicpu(hp1).ops>0) and
  990. (taicpu(hp1).oper[0]^.typ = top_ref) and
  991. (taicpu(hp1).oper[0]^.ref^.symbol is TAsmLabel) and
  992. GetNextInstruction(hp1, hp2) and
  993. (hp2.typ=ait_instruction) and
  994. (taicpu(hp2).opcode in [A_JMP,A_RJMP]) and
  995. (taicpu(hp2).ops>0) and
  996. (taicpu(hp2).oper[0]^.typ = top_ref) and
  997. (taicpu(hp2).oper[0]^.ref^.symbol is TAsmLabel) and
  998. GetNextInstruction(hp2, hp3) and
  999. (hp3.typ=ait_label) and
  1000. (taicpu(hp1).oper[0]^.ref^.symbol=tai_label(hp3).labsym) and
  1001. GetNextInstruction(hp3, hp4) and
  1002. (hp4.typ=ait_instruction) and
  1003. GetNextInstruction(hp4, hp5) and
  1004. (hp3.typ=ait_label) and
  1005. (taicpu(hp2).oper[0]^.ref^.symbol=tai_label(hp5).labsym) then
  1006. begin
  1007. DebugMsg('Peephole SbiJmpJmp2Sbi performed',p);
  1008. tai_label(hp3).labsym.decrefs;
  1009. tai_label(hp5).labsym.decrefs;
  1010. AsmL.remove(hp1);
  1011. taicpu(hp1).Free;
  1012. AsmL.remove(hp2);
  1013. taicpu(hp2).Free;
  1014. result:=true;
  1015. end;
  1016. end;
  1017. end;
  1018. end;
  1019. end;
  1020. end;
  1021. procedure TCpuAsmOptimizer.PeepHoleOptPass2;
  1022. begin
  1023. end;
  1024. begin
  1025. casmoptimizer:=TCpuAsmOptimizer;
  1026. End.