cgcpu.pas 25 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl
  3. This unit implements the code generator for the RiscV64
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit cgcpu;
  18. {$I fpcdefs.inc}
  19. interface
  20. uses
  21. globtype, symtype, symdef, symsym,
  22. cgbase, cgobj,cgrv,
  23. aasmbase, aasmcpu, aasmtai,aasmdata,
  24. cpubase, cpuinfo, cgutils, rgcpu,
  25. parabase;
  26. type
  27. tcgrv64 = class(tcgrv)
  28. procedure init_register_allocators; override;
  29. procedure done_register_allocators; override;
  30. { move instructions }
  31. procedure a_load_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  32. procedure a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; register: tregister); override;
  33. procedure a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister; setflags: boolean; var ovloc: tlocation); override;
  34. procedure a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister; setflags: boolean; var ovloc: tlocation); override;
  35. procedure g_overflowcheck(list: TAsmList; const Loc: tlocation; def: tdef); override;
  36. procedure g_proc_entry(list: TAsmList; localsize: longint; nostackframe: boolean); override;
  37. procedure g_proc_exit(list: TAsmList; parasize: longint; nostackframe: boolean); override;
  38. procedure g_concatcopy_move(list: tasmlist; const Source, dest: treference; len: tcgint);
  39. procedure g_concatcopy(list: TAsmList; const source, dest: treference; len: aint); override;
  40. end;
  41. procedure create_codegen;
  42. implementation
  43. uses
  44. sysutils, cclasses,
  45. globals, verbose, systems, cutils,
  46. symconst, fmodule, symtable,
  47. rgobj, tgobj, cpupi, procinfo, paramgr, cpupara;
  48. { Range check must be disabled explicitly as conversions between signed and unsigned
  49. 64-bit and 32-bit values are done without explicit typecasts }
  50. {$R-}
  51. procedure tcgrv64.init_register_allocators;
  52. begin
  53. inherited init_register_allocators;
  54. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  55. [RS_X10,RS_X11,RS_X12,RS_X13,RS_X14,RS_X15,RS_X16,RS_X17,
  56. RS_X31,RS_X30,RS_X29,RS_X28,
  57. RS_X5,RS_X6,RS_X7,
  58. RS_X9,RS_X27,RS_X26,RS_X25,RS_X24,RS_X23,RS_X22,
  59. RS_X21,RS_X20,RS_X19,RS_X18],first_int_imreg,[]);
  60. rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
  61. [RS_F10,RS_F11,RS_F12,RS_F13,RS_F14,RS_F15,RS_F16,RS_F17,
  62. RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,
  63. RS_F28,RS_F29,RS_F30,RS_F31,
  64. RS_F8,RS_F9,
  65. RS_F27,
  66. RS_F26,RS_F25,RS_F24,RS_F23,RS_F22,RS_F21,RS_F20,RS_F19,RS_F18],first_fpu_imreg,[]);
  67. end;
  68. procedure tcgrv64.done_register_allocators;
  69. begin
  70. rg[R_INTREGISTER].free;
  71. rg[R_FPUREGISTER].free;
  72. inherited done_register_allocators;
  73. end;
  74. procedure tcgrv64.a_load_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister);
  75. var
  76. ai: taicpu;
  77. begin
  78. list.concat(tai_comment.Create(strpnew('Move '+tcgsize2str(fromsize)+'->'+tcgsize2str(tosize))));
  79. if (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_S32) then
  80. list.Concat(taicpu.op_reg_reg_const(A_ADDIW,reg2,reg1,0))
  81. else if (tosize=OS_S32) and (tcgsize2unsigned[fromsize]=OS_64) then
  82. list.Concat(taicpu.op_reg_reg_const(A_ADDIW,reg2,reg1,0))
  83. else if (tosize=OS_S32) and (fromsize=OS_32) then
  84. list.Concat(taicpu.op_reg_reg_const(A_ADDIW,reg2,reg1,0))
  85. else if (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_8) then
  86. list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
  87. else if (tosize=OS_8) and (fromsize<>OS_8) then
  88. list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
  89. else if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
  90. ((tcgsize2size[fromsize] = tcgsize2size[tosize]) and (fromsize <> tosize)) or
  91. { do we need to mask out the sign when loading from smaller signed to larger unsigned type? }
  92. ((tcgsize2unsigned[fromsize]<>fromsize) and ((tcgsize2unsigned[tosize]=tosize)) and
  93. (tcgsize2size[fromsize] < tcgsize2size[tosize]) and (tcgsize2size[tosize] <> sizeof(pint)) ) then
  94. begin
  95. if tcgsize2size[fromsize]<tcgsize2size[tosize] then
  96. begin
  97. list.Concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,8*(8-tcgsize2size[fromsize])));
  98. if tcgsize2unsigned[fromsize]<>fromsize then
  99. list.Concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,8*(tcgsize2size[tosize]-tcgsize2size[fromsize])))
  100. else
  101. list.Concat(taicpu.op_reg_reg_const(A_SRLI,reg2,reg2,8*(tcgsize2size[tosize]-tcgsize2size[fromsize])));
  102. end
  103. else if tcgsize2unsigned[tosize]<>OS_64 then
  104. list.Concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,8*(8-tcgsize2size[tosize])))
  105. else
  106. a_load_reg_reg(list,tosize,tosize,reg1,reg2);
  107. if tcgsize2unsigned[tosize]=tosize then
  108. list.Concat(taicpu.op_reg_reg_const(A_SRLI,reg2,reg2,8*(8-tcgsize2size[tosize])))
  109. else
  110. list.Concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,8*(8-tcgsize2size[tosize])));
  111. end
  112. else
  113. begin
  114. ai:=taicpu.op_reg_reg_const(A_ADDI,reg2,reg1,0);
  115. list.concat(ai);
  116. rg[R_INTREGISTER].add_move_instruction(ai);
  117. end;
  118. end;
  119. procedure tcgrv64.a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; register: tregister);
  120. var
  121. l: TAsmLabel;
  122. hr: treference;
  123. begin
  124. if a=0 then
  125. a_load_reg_reg(list,size,size,NR_X0,register)
  126. else
  127. begin
  128. if is_imm12(a) then
  129. list.concat(taicpu.op_reg_reg_const(A_ADDI,register,NR_X0,a))
  130. else if is_lui_imm(a) then
  131. list.concat(taicpu.op_reg_const(A_LUI,register,(a shr 12) and $FFFFF))
  132. else if (int64(longint(a))=a) then
  133. begin
  134. if (a and $800)<>0 then
  135. list.concat(taicpu.op_reg_const(A_LUI,register,((a shr 12)+1) and $FFFFF))
  136. else
  137. list.concat(taicpu.op_reg_const(A_LUI,register,(a shr 12) and $FFFFF));
  138. list.concat(taicpu.op_reg_reg_const(A_ADDIW,register,register,SarSmallint(smallint(a shl 4),4)));
  139. end
  140. else
  141. begin
  142. reference_reset(hr,8,[]);
  143. current_asmdata.getjumplabel(l);
  144. current_procinfo.aktlocaldata.Concat(cai_align.Create(8));
  145. cg.a_label(current_procinfo.aktlocaldata,l);
  146. hr.symboldata:=current_procinfo.aktlocaldata.last;
  147. current_procinfo.aktlocaldata.concat(tai_const.Create_64bit(a));
  148. hr.symbol:=l;
  149. hr.refaddr:=addr_pcrel_hi20;
  150. current_asmdata.getjumplabel(l);
  151. a_label(list,l);
  152. list.concat(taicpu.op_reg_ref(A_AUIPC,register,hr));
  153. reference_reset_symbol(hr,l,0,0,[]);
  154. hr.refaddr:=addr_pcrel_lo12;
  155. hr.base:=register;
  156. list.concat(taicpu.op_reg_ref(A_LD,register,hr));
  157. end;
  158. end;
  159. end;
  160. procedure tcgrv64.a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister; setflags: boolean; var ovloc: tlocation);
  161. var
  162. signed: Boolean;
  163. l: TAsmLabel;
  164. tmpreg: tregister;
  165. ai: taicpu;
  166. begin
  167. if setflags then
  168. begin
  169. tmpreg:=getintregister(list,size);
  170. a_load_const_reg(list,size,a,tmpreg);
  171. a_op_reg_reg_reg_checkoverflow(list,op,size,tmpreg,src,dst,setflags,ovloc);
  172. end
  173. else
  174. a_op_const_reg_reg(list,op,size,a,src,dst);
  175. end;
  176. procedure tcgrv64.a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister; setflags: boolean; var ovloc: tlocation);
  177. var
  178. signed: Boolean;
  179. l: TAsmLabel;
  180. tmpreg, tmpreg0: tregister;
  181. ai: taicpu;
  182. begin
  183. signed:=tcgsize2unsigned[size]<>size;
  184. if setflags then
  185. case op of
  186. OP_ADD:
  187. begin
  188. current_asmdata.getjumplabel(l);
  189. list.Concat(taicpu.op_reg_reg_reg(A_ADD,dst,src2,src1));
  190. if signed then
  191. begin
  192. {
  193. t0=src1<0
  194. t1=result<src2
  195. overflow if t0<>t1
  196. }
  197. tmpreg0:=getintregister(list,OS_INT);
  198. tmpreg:=getintregister(list,OS_INT);
  199. list.Concat(taicpu.op_reg_reg_reg(A_SLT,tmpreg0,src1,NR_X0));
  200. list.Concat(taicpu.op_reg_reg_reg(A_SLT,tmpreg,dst,src2));
  201. ai:=taicpu.op_reg_reg_sym_ofs(A_Bxx,tmpreg,tmpreg0,l,0);
  202. ai.condition:=C_EQ;
  203. list.concat(ai);
  204. end
  205. else
  206. begin
  207. {
  208. jump if sum>=x
  209. }
  210. if size in [OS_S32,OS_32] then
  211. begin
  212. tmpreg:=getintregister(list,OS_INT);
  213. a_load_reg_reg(list,size,OS_64,dst,tmpreg);
  214. dst:=tmpreg;
  215. end;
  216. ai:=taicpu.op_reg_reg_sym_ofs(A_Bxx,dst,src2,l,0);
  217. ai.condition:=C_GEU;
  218. list.concat(ai);
  219. end;
  220. a_call_name(list,'FPC_OVERFLOW',false);
  221. a_label(list,l);
  222. end;
  223. OP_SUB:
  224. begin
  225. current_asmdata.getjumplabel(l);
  226. list.Concat(taicpu.op_reg_reg_reg(A_SUB,dst,src2,src1));
  227. if signed then
  228. begin
  229. tmpreg0:=getintregister(list,OS_INT);
  230. tmpreg:=getintregister(list,OS_INT);
  231. list.Concat(taicpu.op_reg_reg_reg(A_SLT,tmpreg0,NR_X0,src1));
  232. list.Concat(taicpu.op_reg_reg_reg(A_SLT,tmpreg,dst,src2));
  233. ai:=taicpu.op_reg_reg_sym_ofs(A_Bxx,tmpreg,tmpreg0,l,0);
  234. ai.condition:=C_EQ;
  235. list.concat(ai);
  236. end
  237. else
  238. begin
  239. { no overflow if result<=src2 }
  240. if size in [OS_S32,OS_32] then
  241. begin
  242. tmpreg:=getintregister(list,OS_INT);
  243. a_load_reg_reg(list,size,OS_64,dst,tmpreg);
  244. dst:=tmpreg;
  245. end;
  246. ai:=taicpu.op_reg_reg_sym_ofs(A_Bxx,src2,dst,l,0);
  247. ai.condition:=C_GEU;
  248. list.concat(ai);
  249. end;
  250. a_call_name(list,'FPC_OVERFLOW',false);
  251. a_label(list,l);
  252. end;
  253. OP_IMUL:
  254. begin
  255. { No overflow if upper result is same as sign of result }
  256. current_asmdata.getjumplabel(l);
  257. tmpreg:=getintregister(list,OS_INT);
  258. tmpreg0:=getintregister(list,OS_INT);
  259. list.Concat(taicpu.op_reg_reg_reg(A_MUL,dst,src1,src2));
  260. list.Concat(taicpu.op_reg_reg_reg(A_MULH,tmpreg,src1,src2));
  261. list.concat(taicpu.op_reg_reg_const(A_SRAI,tmpreg0,dst,63));
  262. a_cmp_reg_reg_label(list,OS_INT,OC_EQ,tmpreg,tmpreg0,l);
  263. a_call_name(list,'FPC_OVERFLOW',false);
  264. a_label(list,l);
  265. end;
  266. OP_MUL:
  267. begin
  268. { No overflow if upper result is 0 }
  269. current_asmdata.getjumplabel(l);
  270. tmpreg:=getintregister(list,OS_INT);
  271. list.Concat(taicpu.op_reg_reg_reg(A_MUL,dst,src1,src2));
  272. list.Concat(taicpu.op_reg_reg_reg(A_MULHU,tmpreg,src1,src2));
  273. a_cmp_reg_reg_label(list,OS_INT,OC_EQ,tmpreg,NR_X0,l);
  274. a_call_name(list,'FPC_OVERFLOW',false);
  275. a_label(list,l);
  276. end;
  277. OP_IDIV:
  278. begin
  279. { Only overflow if dst is all 1's }
  280. current_asmdata.getjumplabel(l);
  281. tmpreg:=getintregister(list,OS_INT);
  282. list.Concat(taicpu.op_reg_reg_reg(A_DIV,dst,src1,src2));
  283. list.Concat(taicpu.op_reg_reg_const(A_ADDI,tmpreg,dst,1));
  284. a_cmp_reg_reg_label(list,OS_INT,OC_NE,tmpreg,NR_X0,l);
  285. a_call_name(list,'FPC_OVERFLOW',false);
  286. a_label(list,l);
  287. end;
  288. else
  289. internalerror(2019051032);
  290. end
  291. else
  292. a_op_reg_reg_reg(list,op,size,src1,src2,dst);
  293. end;
  294. procedure tcgrv64.g_overflowcheck(list: TAsmList; const Loc: tlocation; def: tdef);
  295. begin
  296. end;
  297. procedure tcgrv64.g_proc_entry(list: TAsmList; localsize: longint; nostackframe: boolean);
  298. var
  299. regs, fregs: tcpuregisterset;
  300. r: TSuperRegister;
  301. href: treference;
  302. stackcount, stackAdjust: longint;
  303. begin
  304. if not(nostackframe) then
  305. begin
  306. a_reg_alloc(list,NR_STACK_POINTER_REG);
  307. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  308. a_reg_alloc(list,NR_FRAME_POINTER_REG);
  309. reference_reset_base(href,NR_STACK_POINTER_REG,-8,ctempposinvalid,0,[]);
  310. { Int registers }
  311. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  312. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  313. regs:=regs+[RS_FRAME_POINTER_REG,RS_RETURN_ADDRESS_REG];
  314. if (pi_do_call in current_procinfo.flags) then
  315. regs:=regs+[RS_RETURN_ADDRESS_REG];
  316. stackcount:=0;
  317. for r:=RS_X0 to RS_X31 do
  318. if r in regs then
  319. inc(stackcount,8);
  320. { Float registers }
  321. fregs:=rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall);
  322. for r:=RS_F0 to RS_F31 do
  323. if r in fregs then
  324. inc(stackcount,8);
  325. inc(localsize,stackcount);
  326. if not is_imm12(-(localsize-stackcount)) then
  327. begin
  328. if not (RS_RETURN_ADDRESS_REG in regs) then
  329. begin
  330. include(regs,RS_RETURN_ADDRESS_REG);
  331. inc(localsize,8);
  332. inc(stackcount,8);
  333. end;
  334. end;
  335. stackAdjust:=0;
  336. if (CPURV_HAS_COMPACT in cpu_capabilities[current_settings.cputype]) and
  337. (stackcount>0) then
  338. begin
  339. list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,-stackcount));
  340. inc(href.offset,stackcount);
  341. stackAdjust:=stackcount;
  342. dec(localsize,stackcount);
  343. end;
  344. for r:=RS_X0 to RS_X31 do
  345. if r in regs then
  346. begin
  347. list.concat(taicpu.op_reg_ref(A_SD,newreg(R_INTREGISTER,r,R_SUBWHOLE),href));
  348. dec(href.offset,8);
  349. end;
  350. { Float registers }
  351. for r:=RS_F0 to RS_F31 do
  352. if r in fregs then
  353. begin
  354. list.concat(taicpu.op_reg_ref(A_FSD,newreg(R_FPUREGISTER,r,R_SUBWHOLE),href));
  355. dec(href.offset,8);
  356. end;
  357. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  358. list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_FRAME_POINTER_REG,NR_STACK_POINTER_REG,stackAdjust));
  359. if localsize>0 then
  360. begin
  361. localsize:=align(localsize,8);
  362. if is_imm12(-localsize) then
  363. list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,-localsize))
  364. else
  365. begin
  366. a_load_const_reg(list,OS_INT,localsize,NR_RETURN_ADDRESS_REG);
  367. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_RETURN_ADDRESS_REG));
  368. end;
  369. end;
  370. end;
  371. end;
  372. procedure tcgrv64.g_proc_exit(list: TAsmList; parasize: longint; nostackframe: boolean);
  373. var
  374. r: tsuperregister;
  375. regs, fregs: tcpuregisterset;
  376. localsize: longint;
  377. href: treference;
  378. begin
  379. if not(nostackframe) then
  380. begin
  381. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  382. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  383. regs:=regs+[RS_FRAME_POINTER_REG,RS_RETURN_ADDRESS_REG];
  384. if (pi_do_call in current_procinfo.flags) then
  385. regs:=regs+[RS_RETURN_ADDRESS_REG];
  386. reference_reset_base(href,NR_STACK_POINTER_REG,-8,ctempposinvalid,0,[]);
  387. for r:=RS_X31 downto RS_X0 do
  388. if r in regs then
  389. dec(href.offset,8);
  390. { Float registers }
  391. fregs:=rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall);
  392. for r:=RS_F0 to RS_F31 do
  393. if r in fregs then
  394. dec(href.offset,8);
  395. localsize:=current_procinfo.calc_stackframe_size+(-href.offset-8);
  396. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  397. list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_FRAME_POINTER_REG,0))
  398. else if localsize>0 then
  399. begin
  400. localsize:=align(localsize,8);
  401. if is_imm12(localsize) then
  402. list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,localsize))
  403. else
  404. begin
  405. if not (RS_RETURN_ADDRESS_REG in regs) then
  406. begin
  407. include(regs,RS_RETURN_ADDRESS_REG);
  408. dec(href.offset,8);
  409. inc(localsize,8);
  410. end;
  411. a_load_const_reg(list,OS_INT,localsize,NR_RETURN_ADDRESS_REG);
  412. list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_RETURN_ADDRESS_REG));
  413. end;
  414. end;
  415. { Float registers }
  416. for r:=RS_F31 downto RS_F0 do
  417. if r in fregs then
  418. begin
  419. inc(href.offset,8);
  420. list.concat(taicpu.op_reg_ref(A_FLD,newreg(R_FPUREGISTER,r,R_SUBWHOLE),href));
  421. end;
  422. for r:=RS_X31 downto RS_X0 do
  423. if r in regs then
  424. begin
  425. inc(href.offset,8);
  426. list.concat(taicpu.op_reg_ref(A_LD,newreg(R_INTREGISTER,r,R_SUBWHOLE),href));
  427. end;
  428. end;
  429. list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG));
  430. end;
  431. procedure tcgrv64.g_concatcopy_move(list: tasmlist; const Source, dest: treference; len: tcgint);
  432. var
  433. paraloc1, paraloc2, paraloc3: TCGPara;
  434. pd: tprocdef;
  435. begin
  436. pd:=search_system_proc('MOVE');
  437. paraloc1.init;
  438. paraloc2.init;
  439. paraloc3.init;
  440. paramanager.getcgtempparaloc(list, pd, 1, paraloc1);
  441. paramanager.getcgtempparaloc(list, pd, 2, paraloc2);
  442. paramanager.getcgtempparaloc(list, pd, 3, paraloc3);
  443. a_load_const_cgpara(list, OS_SINT, len, paraloc3);
  444. a_loadaddr_ref_cgpara(list, dest, paraloc2);
  445. a_loadaddr_ref_cgpara(list, Source, paraloc1);
  446. paramanager.freecgpara(list, paraloc3);
  447. paramanager.freecgpara(list, paraloc2);
  448. paramanager.freecgpara(list, paraloc1);
  449. alloccpuregisters(list, R_INTREGISTER, paramanager.get_volatile_registers_int(pocall_default));
  450. alloccpuregisters(list, R_FPUREGISTER, paramanager.get_volatile_registers_fpu(pocall_default));
  451. a_call_name(list, 'FPC_MOVE', false);
  452. dealloccpuregisters(list, R_FPUREGISTER, paramanager.get_volatile_registers_fpu(pocall_default));
  453. dealloccpuregisters(list, R_INTREGISTER, paramanager.get_volatile_registers_int(pocall_default));
  454. paraloc3.done;
  455. paraloc2.done;
  456. paraloc1.done;
  457. end;
  458. procedure tcgrv64.g_concatcopy(list: TAsmList; const source, dest: treference; len: aint);
  459. var
  460. tmpreg1, hreg, countreg: TRegister;
  461. src, dst, src2, dst2: TReference;
  462. lab: tasmlabel;
  463. Count, count2: aint;
  464. begin
  465. src2:=source;
  466. fixref(list,src2);
  467. dst2:=dest;
  468. fixref(list,dst2);
  469. if len > high(longint) then
  470. internalerror(2002072704);
  471. { A call (to FPC_MOVE) requires the outgoing parameter area to be properly
  472. allocated on stack. This can only be done before tmipsprocinfo.set_first_temp_offset,
  473. i.e. before secondpass. Other internal procedures request correct stack frame
  474. by setting pi_do_call during firstpass, but for this particular one it is impossible.
  475. Therefore, if the current procedure is a leaf one, we have to leave it that way. }
  476. { anybody wants to determine a good value here :)? }
  477. if (len > 100) and
  478. assigned(current_procinfo) and
  479. (pi_do_call in current_procinfo.flags) then
  480. g_concatcopy_move(list, src2, dst2, len)
  481. else
  482. begin
  483. Count := len div 8;
  484. reference_reset(src,sizeof(aint),[]);
  485. { load the address of src2 into src.base }
  486. src.base := GetAddressRegister(list);
  487. a_loadaddr_ref_reg(list, src2, src.base);
  488. reference_reset(dst,sizeof(aint),[]);
  489. { load the address of dst2 into dst.base }
  490. dst.base := GetAddressRegister(list);
  491. a_loadaddr_ref_reg(list, dst2, dst.base);
  492. { generate a loop }
  493. if Count > 4 then
  494. begin
  495. countreg := GetIntRegister(list, OS_INT);
  496. tmpreg1 := GetIntRegister(list, OS_INT);
  497. a_load_const_reg(list, OS_INT, Count, countreg);
  498. current_asmdata.getjumplabel(lab);
  499. a_label(list, lab);
  500. list.concat(taicpu.op_reg_ref(A_LD, tmpreg1, src));
  501. list.concat(taicpu.op_reg_ref(A_SD, tmpreg1, dst));
  502. list.concat(taicpu.op_reg_reg_const(A_ADDI, src.base, src.base, 8));
  503. list.concat(taicpu.op_reg_reg_const(A_ADDI, dst.base, dst.base, 8));
  504. list.concat(taicpu.op_reg_reg_const(A_ADDI, countreg, countreg, -1));
  505. a_cmp_reg_reg_label(list,OS_INT,OC_GT,NR_X0,countreg,lab);
  506. len := len mod 8;
  507. end;
  508. { unrolled loop }
  509. Count := len div 8;
  510. if Count > 0 then
  511. begin
  512. tmpreg1 := GetIntRegister(list, OS_INT);
  513. count2 := 1;
  514. while count2 <= Count do
  515. begin
  516. list.concat(taicpu.op_reg_ref(A_LD, tmpreg1, src));
  517. list.concat(taicpu.op_reg_ref(A_SD, tmpreg1, dst));
  518. Inc(src.offset, 8);
  519. Inc(dst.offset, 8);
  520. Inc(count2);
  521. end;
  522. len := len mod 8;
  523. end;
  524. if (len and 4) <> 0 then
  525. begin
  526. hreg := GetIntRegister(list, OS_INT);
  527. a_load_ref_reg(list, OS_32, OS_32, src, hreg);
  528. a_load_reg_ref(list, OS_32, OS_32, hreg, dst);
  529. Inc(src.offset, 4);
  530. Inc(dst.offset, 4);
  531. end;
  532. { copy the leftovers }
  533. if (len and 2) <> 0 then
  534. begin
  535. hreg := GetIntRegister(list, OS_INT);
  536. a_load_ref_reg(list, OS_16, OS_16, src, hreg);
  537. a_load_reg_ref(list, OS_16, OS_16, hreg, dst);
  538. Inc(src.offset, 2);
  539. Inc(dst.offset, 2);
  540. end;
  541. if (len and 1) <> 0 then
  542. begin
  543. hreg := GetIntRegister(list, OS_INT);
  544. a_load_ref_reg(list, OS_8, OS_8, src, hreg);
  545. a_load_reg_ref(list, OS_8, OS_8, hreg, dst);
  546. end;
  547. end;
  548. end;
  549. procedure create_codegen;
  550. begin
  551. cg := tcgrv64.create;
  552. cg128:=tcg128.create;
  553. end;
  554. end.