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aasmcpu.pas
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e047e7db91
+ RiscV: initial support of pic generation
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%!s(int64=4) %!d(string=hai) anos |
agrvgas.pas
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8382c6f586
Added generic WCH32Vx RISC-V processor types using memory size suffixes
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%!s(int64=2) %!d(string=hai) anos |
aoptcpurv.pas
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39f7172ee8
* do no generated debug comment in assembler output of RiscV if not requested
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hai 1 ano |
cgrv.pas
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a71cc71585
+ function needs_check_for_fpu_exceptions to unify fpu exception handling
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hai 1 ano |
cpubase.pas
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a05aa25aad
* Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738
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%!s(int64=3) %!d(string=hai) anos |
hlcgrv.pas
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637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
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%!s(int64=5) %!d(string=hai) anos |
itcpugas.pas
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ec3a04da9b
+ forgotten pseudo-instructions added
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%!s(int64=3) %!d(string=hai) anos |
nrvadd.pas
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a736a4bba7
+ set pi_do_call on RiscV as well if we check for fpu exceptions
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hai 1 ano |
nrvcnv.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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%!s(int64=7) %!d(string=hai) anos |
nrvcon.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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%!s(int64=7) %!d(string=hai) anos |
nrvinl.pas
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a736a4bba7
+ set pi_do_call on RiscV as well if we check for fpu exceptions
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hai 1 ano |
nrvset.pas
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07bd4ba517
* let all the case code generation work with tconstexprint instead of aint,
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%!s(int64=6) %!d(string=hai) anos |
rarv.pas
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d1fb44044f
* unified RiscV32 and RiscV64 GAS readers
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%!s(int64=4) %!d(string=hai) anos |
rarvgas.pas
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a05aa25aad
* Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738
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%!s(int64=3) %!d(string=hai) anos |
rgcpu.pas
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92b0ea7d02
Add explicit smallint typecast to first marameter of SarSmallint call to avoid range check errors
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%!s(int64=5) %!d(string=hai) anos |
rvreg.dat
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ae457a18ad
* unified Risc-V 32 and 64 register data file
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%!s(int64=3) %!d(string=hai) anos |