cpuinfo.pas 33 KB

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  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv4t,
  28. cpu_armv5,
  29. cpu_armv5t,
  30. cpu_armv5te,
  31. cpu_armv5tej,
  32. cpu_armv6,
  33. cpu_armv6k,
  34. cpu_armv6t2,
  35. cpu_armv6z,
  36. cpu_armv7,
  37. cpu_armv7a,
  38. cpu_armv7r,
  39. cpu_armv7m,
  40. cpu_armv7em
  41. );
  42. Const
  43. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5];
  44. cpu_thumb = [];
  45. cpu_thumb2 = [cpu_armv7m];
  46. Type
  47. tfputype =
  48. (fpu_none,
  49. fpu_soft,
  50. fpu_libgcc,
  51. fpu_fpa,
  52. fpu_fpa10,
  53. fpu_fpa11,
  54. fpu_vfpv2,
  55. fpu_vfpv3,
  56. fpu_vfpv3_d16,
  57. fpu_fpv4_s16
  58. );
  59. tcontrollertype =
  60. (ct_none,
  61. { Phillips }
  62. ct_lpc1343,
  63. ct_lpc2114,
  64. ct_lpc2124,
  65. ct_lpc2194,
  66. ct_lpc1754,
  67. ct_lpc1756,
  68. ct_lpc1758,
  69. ct_lpc1764,
  70. ct_lpc1766,
  71. ct_lpc1768,
  72. { ATMEL }
  73. ct_at91sam7s256,
  74. ct_at91sam7se256,
  75. ct_at91sam7x256,
  76. ct_at91sam7xc256,
  77. { STMicroelectronics }
  78. ct_stm32f100x4, // LD&MD value line, 4=16,6=32,8=64,b=128
  79. ct_stm32f100x6,
  80. ct_stm32f100x8,
  81. ct_stm32f100xB,
  82. ct_stm32f100xC, // HD value line, r=512,d=384,c=256
  83. ct_stm32f100xD,
  84. ct_stm32f100xE,
  85. ct_stm32f101x4, // LD Access line, 4=16,6=32
  86. ct_stm32f101x6,
  87. ct_stm32f101x8, // MD Access line, 8=64,B=128
  88. ct_stm32f101xB,
  89. ct_stm32f101xC, // HD Access line, C=256,D=384,E=512
  90. ct_stm32f101xD,
  91. ct_stm32f101xE,
  92. ct_stm32f101xF, // XL Access line, F=768,G=1M
  93. ct_stm32f101xG,
  94. ct_stm32f102x4, // LD usb access line, 4=16,6=32
  95. ct_stm32f102x6,
  96. ct_stm32f102x8, // MD usb access line, 8=64,B=128
  97. ct_stm32f102xB,
  98. ct_stm32f103x4, // LD performance line, 4=16,6=32
  99. ct_stm32f103x6,
  100. ct_stm32f103x8, // MD performance line, 8=64,B=128
  101. ct_stm32f103xB,
  102. ct_stm32f103xC, // HD performance line, C=256,D=384,E=512
  103. ct_stm32f103xD,
  104. ct_stm32f103xE,
  105. ct_stm32f103xF, // XL performance line, F=768,G=1M
  106. ct_stm32f103xG,
  107. ct_stm32f107x8, // MD and HD connectivity line, 8=64,B=128,C=256
  108. ct_stm32f107xB,
  109. ct_stm32f107xC,
  110. { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
  111. ct_lm3s1110,
  112. ct_lm3s1133,
  113. ct_lm3s1138,
  114. ct_lm3s1150,
  115. ct_lm3s1162,
  116. ct_lm3s1165,
  117. ct_lm3s1166,
  118. ct_lm3s2110,
  119. ct_lm3s2139,
  120. ct_lm3s6100,
  121. ct_lm3s6110,
  122. { TI - Fury Class - 128K Flash, 32K SRAM devices }
  123. ct_lm3s1601,
  124. ct_lm3s1608,
  125. ct_lm3s1620,
  126. ct_lm3s1635,
  127. ct_lm3s1636,
  128. ct_lm3s1637,
  129. ct_lm3s1651,
  130. ct_lm3s2601,
  131. ct_lm3s2608,
  132. ct_lm3s2620,
  133. ct_lm3s2637,
  134. ct_lm3s2651,
  135. ct_lm3s6610,
  136. ct_lm3s6611,
  137. ct_lm3s6618,
  138. ct_lm3s6633,
  139. ct_lm3s6637,
  140. ct_lm3s8630,
  141. { TI - Fury Class - 256K Flash, 64K SRAM devices }
  142. ct_lm3s1911,
  143. ct_lm3s1918,
  144. ct_lm3s1937,
  145. ct_lm3s1958,
  146. ct_lm3s1960,
  147. ct_lm3s1968,
  148. ct_lm3s1969,
  149. ct_lm3s2911,
  150. ct_lm3s2918,
  151. ct_lm3s2919,
  152. ct_lm3s2939,
  153. ct_lm3s2948,
  154. ct_lm3s2950,
  155. ct_lm3s2965,
  156. ct_lm3s6911,
  157. ct_lm3s6918,
  158. ct_lm3s6938,
  159. ct_lm3s6950,
  160. ct_lm3s6952,
  161. ct_lm3s6965,
  162. ct_lm3s8930,
  163. ct_lm3s8933,
  164. ct_lm3s8938,
  165. ct_lm3s8962,
  166. ct_lm3s8970,
  167. ct_lm3s8971,
  168. { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
  169. ct_lm3s5951,
  170. ct_lm3s5956,
  171. ct_lm3s1b21,
  172. ct_lm3s2b93,
  173. ct_lm3s5b91,
  174. ct_lm3s9b81,
  175. ct_lm3s9b90,
  176. ct_lm3s9b92,
  177. ct_lm3s9b95,
  178. ct_lm3s9b96,
  179. { SAMSUNG }
  180. ct_sc32442b,
  181. // generic Thumb2 target
  182. ct_thumb2bare
  183. );
  184. Const
  185. {# Size of native extended floating point type }
  186. extended_size = 12;
  187. {# Size of a multimedia register }
  188. mmreg_size = 16;
  189. { target cpu string (used by compiler options) }
  190. target_cpu_string = 'arm';
  191. { calling conventions supported by the code generator }
  192. supported_calling_conventions : tproccalloptions = [
  193. pocall_internproc,
  194. pocall_safecall,
  195. pocall_stdcall,
  196. { same as stdcall only different name mangling }
  197. pocall_cdecl,
  198. { same as stdcall only different name mangling }
  199. pocall_cppdecl,
  200. { same as stdcall but floating point numbers are handled like equal sized integers }
  201. pocall_softfloat,
  202. { same as stdcall (requires that all const records are passed by
  203. reference, but that's already done for stdcall) }
  204. pocall_mwpascal,
  205. { used for interrupt handling }
  206. pocall_interrupt
  207. ];
  208. cputypestr : array[tcputype] of string[8] = ('',
  209. 'ARMV3',
  210. 'ARMV4',
  211. 'ARMV4T',
  212. 'ARMV5',
  213. 'ARMV5T',
  214. 'ARMV5TE',
  215. 'ARMV5TEJ',
  216. 'ARMV6',
  217. 'ARMV6K',
  218. 'ARMV6T2',
  219. 'ARMV6Z',
  220. 'ARMV7',
  221. 'ARMV7A',
  222. 'ARMV7R',
  223. 'ARMV7M',
  224. 'ARMV7EM'
  225. );
  226. fputypestr : array[tfputype] of string[9] = ('',
  227. 'SOFT',
  228. 'LIBGCC',
  229. 'FPA',
  230. 'FPA10',
  231. 'FPA11',
  232. 'VFPV2',
  233. 'VFPV3',
  234. 'VFPV3_D16',
  235. 'FPV4_S16'
  236. );
  237. { We know that there are fields after sramsize
  238. but we don't care about this warning }
  239. {$WARN 3177 OFF}
  240. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  241. ((
  242. controllertypestr:'';
  243. controllerunitstr:'';
  244. flashbase:0;
  245. flashsize:0;
  246. srambase:0;
  247. sramsize:0
  248. ),
  249. (
  250. controllertypestr:'LPC1343';
  251. controllerunitstr:'LPC1343';
  252. flashbase:$00000000;
  253. flashsize:$00008000;
  254. srambase:$10000000;
  255. sramsize:$00002000
  256. ),
  257. (
  258. controllertypestr:'LPC2114';
  259. controllerunitstr:'LPC21x4';
  260. flashbase:$00000000;
  261. flashsize:$00040000;
  262. srambase:$40000000;
  263. sramsize:$00004000
  264. ),
  265. (
  266. controllertypestr:'LPC2124';
  267. controllerunitstr:'LPC21x4';
  268. flashbase:$00000000;
  269. flashsize:$00040000;
  270. srambase:$40000000;
  271. sramsize:$00004000
  272. ),
  273. (
  274. controllertypestr:'LPC2194';
  275. controllerunitstr:'LPC21x4';
  276. flashbase:$00000000;
  277. flashsize:$00040000;
  278. srambase:$40000000;
  279. sramsize:$00004000
  280. ),
  281. (
  282. controllertypestr:'LPC1754';
  283. controllerunitstr:'LPC1754';
  284. flashbase:$00000000;
  285. flashsize:$00020000;
  286. srambase:$10000000;
  287. sramsize:$00004000
  288. ),
  289. (
  290. controllertypestr:'LPC1756';
  291. controllerunitstr:'LPC1756';
  292. flashbase:$00000000;
  293. flashsize:$00040000;
  294. srambase:$10000000;
  295. sramsize:$00004000
  296. ),
  297. (
  298. controllertypestr:'LPC1758';
  299. controllerunitstr:'LPC1758';
  300. flashbase:$00000000;
  301. flashsize:$00080000;
  302. srambase:$10000000;
  303. sramsize:$00008000
  304. ),
  305. (
  306. controllertypestr:'LPC1764';
  307. controllerunitstr:'LPC1764';
  308. flashbase:$00000000;
  309. flashsize:$00020000;
  310. srambase:$10000000;
  311. sramsize:$00004000
  312. ),
  313. (
  314. controllertypestr:'LPC1766';
  315. controllerunitstr:'LPC1766';
  316. flashbase:$00000000;
  317. flashsize:$00040000;
  318. srambase:$10000000;
  319. sramsize:$00008000
  320. ),
  321. (
  322. controllertypestr:'LPC1768';
  323. controllerunitstr:'LPC1768';
  324. flashbase:$00000000;
  325. flashsize:$00080000;
  326. srambase:$10000000;
  327. sramsize:$00008000
  328. ),
  329. (
  330. controllertypestr:'AT91SAM7S256';
  331. controllerunitstr:'AT91SAM7x256';
  332. flashbase:$00000000;
  333. flashsize:$00040000;
  334. srambase:$00200000;
  335. sramsize:$00010000
  336. ),
  337. (
  338. controllertypestr:'AT91SAM7SE256';
  339. controllerunitstr:'AT91SAM7x256';
  340. flashbase:$00000000;
  341. flashsize:$00040000;
  342. srambase:$00200000;
  343. sramsize:$00010000
  344. ),
  345. (
  346. controllertypestr:'AT91SAM7X256';
  347. controllerunitstr:'AT91SAM7x256';
  348. flashbase:$00000000;
  349. flashsize:$00040000;
  350. srambase:$00200000;
  351. sramsize:$00010000
  352. ),
  353. (
  354. controllertypestr:'AT91SAM7XC256';
  355. controllerunitstr:'AT91SAM7x256';
  356. flashbase:$00000000;
  357. flashsize:$00040000;
  358. srambase:$00200000;
  359. sramsize:$00010000
  360. ),
  361. { STM32F1 series }
  362. (controllertypestr:'STM32F100X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
  363. (controllertypestr:'STM32F100X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
  364. (controllertypestr:'STM32F100X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000),
  365. (controllertypestr:'STM32F100XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00002000),
  366. (controllertypestr:'STM32F100XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00006000),
  367. (controllertypestr:'STM32F100XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00008000),
  368. (controllertypestr:'STM32F100XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00008000),
  369. (controllertypestr:'STM32F101X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
  370. (controllertypestr:'STM32F101X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800),
  371. (controllertypestr:'STM32F101X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800),
  372. (controllertypestr:'STM32F101XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000),
  373. (controllertypestr:'STM32F101XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00008000),
  374. (controllertypestr:'STM32F101XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$0000C000),
  375. (controllertypestr:'STM32F101XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$0000C000),
  376. (controllertypestr:'STM32F101XF'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00014000),
  377. (controllertypestr:'STM32F101XG'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00014000),
  378. (controllertypestr:'STM32F102X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
  379. (controllertypestr:'STM32F102X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800),
  380. (controllertypestr:'STM32F102X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800),
  381. (controllertypestr:'STM32F102XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000),
  382. (controllertypestr:'STM32F103X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
  383. (controllertypestr:'STM32F103X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00002800),
  384. (controllertypestr:'STM32F103X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00005000),
  385. (controllertypestr:'STM32F103XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00005000),
  386. (controllertypestr:'STM32F103XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$0000C000),
  387. (controllertypestr:'STM32F103XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00010000),
  388. (controllertypestr:'STM32F103XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00010000),
  389. (controllertypestr:'STM32F103XF'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00018000),
  390. (controllertypestr:'STM32F103XG'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00018000),
  391. (controllertypestr:'STM32F107X8'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00010000),
  392. (controllertypestr:'STM32F107XB'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
  393. (controllertypestr:'STM32F107XC'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
  394. { TI - 64 K Flash, 16 K SRAM Devices }
  395. // ct_lm3s1110,
  396. (
  397. controllertypestr:'LM3S1110';
  398. controllerunitstr:'LM3FURY';
  399. flashbase:$00000000;
  400. flashsize:$00010000;
  401. srambase:$20000000;
  402. sramsize:$00004000
  403. ),
  404. // ct_lm3s1133,
  405. (
  406. controllertypestr:'LM3S1133';
  407. controllerunitstr:'LM3FURY';
  408. flashbase:$00000000;
  409. flashsize:$00010000;
  410. srambase:$20000000;
  411. sramsize:$00004000
  412. ),
  413. // ct_lm3s1138,
  414. (
  415. controllertypestr:'LM3S1138';
  416. controllerunitstr:'LM3FURY';
  417. flashbase:$00000000;
  418. flashsize:$00010000;
  419. srambase:$20000000;
  420. sramsize:$00004000
  421. ),
  422. // ct_lm3s1150,
  423. (
  424. controllertypestr:'LM3S1150';
  425. controllerunitstr:'LM3FURY';
  426. flashbase:$00000000;
  427. flashsize:$00010000;
  428. srambase:$20000000;
  429. sramsize:$00004000
  430. ),
  431. // ct_lm3s1162,
  432. (
  433. controllertypestr:'LM3S1162';
  434. controllerunitstr:'LM3FURY';
  435. flashbase:$00000000;
  436. flashsize:$00010000;
  437. srambase:$20000000;
  438. sramsize:$00004000
  439. ),
  440. // ct_lm3s1165,
  441. (
  442. controllertypestr:'LM3S1165';
  443. controllerunitstr:'LM3FURY';
  444. flashbase:$00000000;
  445. flashsize:$00010000;
  446. srambase:$20000000;
  447. sramsize:$00004000
  448. ),
  449. // ct_lm3s1166,
  450. (
  451. controllertypestr:'LM3S1166';
  452. controllerunitstr:'LM3FURY';
  453. flashbase:$00000000;
  454. flashsize:$00010000;
  455. srambase:$20000000;
  456. sramsize:$00004000
  457. ),
  458. // ct_lm3s2110,
  459. (
  460. controllertypestr:'LM3S2110';
  461. controllerunitstr:'LM3FURY';
  462. flashbase:$00000000;
  463. flashsize:$00010000;
  464. srambase:$20000000;
  465. sramsize:$00004000
  466. ),
  467. // ct_lm3s2139,
  468. (
  469. controllertypestr:'LM3S2139';
  470. controllerunitstr:'LM3FURY';
  471. flashbase:$00000000;
  472. flashsize:$00010000;
  473. srambase:$20000000;
  474. sramsize:$00004000
  475. ),
  476. // ct_lm3s6100,
  477. (
  478. controllertypestr:'LM3S6100';
  479. controllerunitstr:'LM3FURY';
  480. flashbase:$00000000;
  481. flashsize:$00010000;
  482. srambase:$20000000;
  483. sramsize:$00004000
  484. ),
  485. // ct_lm3s6110,
  486. (
  487. controllertypestr:'LM3S6110';
  488. controllerunitstr:'LM3FURY';
  489. flashbase:$00000000;
  490. flashsize:$00010000;
  491. srambase:$20000000;
  492. sramsize:$00004000
  493. ),
  494. { TI - 128K Flash, 32K SRAM devices }
  495. // ct_lm3s1601,
  496. (
  497. controllertypestr:'LM3S1601';
  498. controllerunitstr:'LM3FURY';
  499. flashbase:$00000000;
  500. flashsize:$00020000;
  501. srambase:$20000000;
  502. sramsize:$00008000
  503. ),
  504. // ct_lm3s1608,
  505. (
  506. controllertypestr:'LM3S1608';
  507. controllerunitstr:'LM3FURY';
  508. flashbase:$00000000;
  509. flashsize:$00020000;
  510. srambase:$20000000;
  511. sramsize:$00008000
  512. ),
  513. // ct_lm3s1620,
  514. (
  515. controllertypestr:'LM3S1620';
  516. controllerunitstr:'LM3FURY';
  517. flashbase:$00000000;
  518. flashsize:$00020000;
  519. srambase:$20000000;
  520. sramsize:$00008000
  521. ),
  522. // ct_lm3s1635,
  523. (
  524. controllertypestr:'LM3S1635';
  525. controllerunitstr:'LM3FURY';
  526. flashbase:$00000000;
  527. flashsize:$00020000;
  528. srambase:$20000000;
  529. sramsize:$00008000
  530. ),
  531. // ct_lm3s1636,
  532. (
  533. controllertypestr:'LM3S1636';
  534. controllerunitstr:'LM3FURY';
  535. flashbase:$00000000;
  536. flashsize:$00020000;
  537. srambase:$20000000;
  538. sramsize:$00008000
  539. ),
  540. // ct_lm3s1637,
  541. (
  542. controllertypestr:'LM3S1637';
  543. controllerunitstr:'LM3FURY';
  544. flashbase:$00000000;
  545. flashsize:$00020000;
  546. srambase:$20000000;
  547. sramsize:$00008000
  548. ),
  549. // ct_lm3s1651,
  550. (
  551. controllertypestr:'LM3S1651';
  552. controllerunitstr:'LM3FURY';
  553. flashbase:$00000000;
  554. flashsize:$00020000;
  555. srambase:$20000000;
  556. sramsize:$00008000
  557. ),
  558. // ct_lm3s2601,
  559. (
  560. controllertypestr:'LM3S2601';
  561. controllerunitstr:'LM3FURY';
  562. flashbase:$00000000;
  563. flashsize:$00020000;
  564. srambase:$20000000;
  565. sramsize:$00008000
  566. ),
  567. // ct_lm3s2608,
  568. (
  569. controllertypestr:'LM3S2608';
  570. controllerunitstr:'LM3FURY';
  571. flashbase:$00000000;
  572. flashsize:$00020000;
  573. srambase:$20000000;
  574. sramsize:$00008000
  575. ),
  576. // ct_lm3s2620,
  577. (
  578. controllertypestr:'LM3S2620';
  579. controllerunitstr:'LM3FURY';
  580. flashbase:$00000000;
  581. flashsize:$00020000;
  582. srambase:$20000000;
  583. sramsize:$00008000
  584. ),
  585. // ct_lm3s2637,
  586. (
  587. controllertypestr:'LM3S2637';
  588. controllerunitstr:'LM3FURY';
  589. flashbase:$00000000;
  590. flashsize:$00020000;
  591. srambase:$20000000;
  592. sramsize:$00008000
  593. ),
  594. // ct_lm3s2651,
  595. (
  596. controllertypestr:'LM3S2651';
  597. controllerunitstr:'LM3FURY';
  598. flashbase:$00000000;
  599. flashsize:$00020000;
  600. srambase:$20000000;
  601. sramsize:$00008000
  602. ),
  603. // ct_lm3s6610,
  604. (
  605. controllertypestr:'LM3S6610';
  606. controllerunitstr:'LM3FURY';
  607. flashbase:$00000000;
  608. flashsize:$00020000;
  609. srambase:$20000000;
  610. sramsize:$00008000
  611. ),
  612. // ct_lm3s6611,
  613. (
  614. controllertypestr:'LM3S6611';
  615. controllerunitstr:'LM3FURY';
  616. flashbase:$00000000;
  617. flashsize:$00020000;
  618. srambase:$20000000;
  619. sramsize:$00008000
  620. ),
  621. // ct_lm3s6618,
  622. (
  623. controllertypestr:'LM3S6618';
  624. controllerunitstr:'LM3FURY';
  625. flashbase:$00000000;
  626. flashsize:$00020000;
  627. srambase:$20000000;
  628. sramsize:$00008000
  629. ),
  630. // ct_lm3s6633,
  631. (
  632. controllertypestr:'LM3S6633';
  633. controllerunitstr:'LM3FURY';
  634. flashbase:$00000000;
  635. flashsize:$00020000;
  636. srambase:$20000000;
  637. sramsize:$00008000
  638. ),
  639. // ct_lm3s6637,
  640. (
  641. controllertypestr:'LM3S6637';
  642. controllerunitstr:'LM3FURY';
  643. flashbase:$00000000;
  644. flashsize:$00020000;
  645. srambase:$20000000;
  646. sramsize:$00008000
  647. ),
  648. // ct_lm3s8630,
  649. (
  650. controllertypestr:'LM3S8630';
  651. controllerunitstr:'LM3FURY';
  652. flashbase:$00000000;
  653. flashsize:$00020000;
  654. srambase:$20000000;
  655. sramsize:$00008000
  656. ),
  657. { TI - 256K Flash, 64K SRAM devices }
  658. // ct_lm3s1911,
  659. (
  660. controllertypestr:'LM3S1911';
  661. controllerunitstr:'LM3FURY';
  662. flashbase:$00000000;
  663. flashsize:$00040000;
  664. srambase:$20000000;
  665. sramsize:$00010000
  666. ),
  667. // ct_lm3s1918,
  668. (
  669. controllertypestr:'LM3S1918';
  670. controllerunitstr:'LM3FURY';
  671. flashbase:$00000000;
  672. flashsize:$00040000;
  673. srambase:$20000000;
  674. sramsize:$00010000
  675. ),
  676. // ct_lm3s1937,
  677. (
  678. controllertypestr:'LM3S1937';
  679. controllerunitstr:'LM3FURY';
  680. flashbase:$00000000;
  681. flashsize:$00040000;
  682. srambase:$20000000;
  683. sramsize:$00010000
  684. ),
  685. // ct_lm3s1958,
  686. (
  687. controllertypestr:'LM3S1958';
  688. controllerunitstr:'LM3FURY';
  689. flashbase:$00000000;
  690. flashsize:$00040000;
  691. srambase:$20000000;
  692. sramsize:$00010000
  693. ),
  694. // ct_lm3s1960,
  695. (
  696. controllertypestr:'LM3S1960';
  697. controllerunitstr:'LM3FURY';
  698. flashbase:$00000000;
  699. flashsize:$00040000;
  700. srambase:$20000000;
  701. sramsize:$00010000
  702. ),
  703. // ct_lm3s1968,
  704. (
  705. controllertypestr:'LM3S1968';
  706. controllerunitstr:'LM3FURY';
  707. flashbase:$00000000;
  708. flashsize:$00040000;
  709. srambase:$20000000;
  710. sramsize:$00010000
  711. ),
  712. // ct_lm3s1969,
  713. (
  714. controllertypestr:'LM3S1969';
  715. controllerunitstr:'LM3FURY';
  716. flashbase:$00000000;
  717. flashsize:$00040000;
  718. srambase:$20000000;
  719. sramsize:$00010000
  720. ),
  721. // ct_lm3s2911,
  722. (
  723. controllertypestr:'LM3S2911';
  724. controllerunitstr:'LM3FURY';
  725. flashbase:$00000000;
  726. flashsize:$00040000;
  727. srambase:$20000000;
  728. sramsize:$00010000
  729. ),
  730. // ct_lm3s2918,
  731. (
  732. controllertypestr:'LM3S2918';
  733. controllerunitstr:'LM3FURY';
  734. flashbase:$00000000;
  735. flashsize:$00040000;
  736. srambase:$20000000;
  737. sramsize:$00010000
  738. ),
  739. // ct_lm3s2919,
  740. (
  741. controllertypestr:'LM3S2919';
  742. controllerunitstr:'LM3FURY';
  743. flashbase:$00000000;
  744. flashsize:$00040000;
  745. srambase:$20000000;
  746. sramsize:$00010000
  747. ),
  748. // ct_lm3s2939,
  749. (
  750. controllertypestr:'LM3S2939';
  751. controllerunitstr:'LM3FURY';
  752. flashbase:$00000000;
  753. flashsize:$00040000;
  754. srambase:$20000000;
  755. sramsize:$00010000
  756. ),
  757. // ct_lm3s2948,
  758. (
  759. controllertypestr:'LM3S2948';
  760. controllerunitstr:'LM3FURY';
  761. flashbase:$00000000;
  762. flashsize:$00040000;
  763. srambase:$20000000;
  764. sramsize:$00010000
  765. ),
  766. // ct_lm3s2950,
  767. (
  768. controllertypestr:'LM3S2950';
  769. controllerunitstr:'LM3FURY';
  770. flashbase:$00000000;
  771. flashsize:$00040000;
  772. srambase:$20000000;
  773. sramsize:$00010000
  774. ),
  775. // ct_lm3s2965,
  776. (
  777. controllertypestr:'LM3S2965';
  778. controllerunitstr:'LM3FURY';
  779. flashbase:$00000000;
  780. flashsize:$00040000;
  781. srambase:$20000000;
  782. sramsize:$00010000
  783. ),
  784. // ct_lm3s6911,
  785. (
  786. controllertypestr:'LM3S6911';
  787. controllerunitstr:'LM3FURY';
  788. flashbase:$00000000;
  789. flashsize:$00040000;
  790. srambase:$20000000;
  791. sramsize:$00010000
  792. ),
  793. // ct_lm3s6918,
  794. (
  795. controllertypestr:'LM3S6918';
  796. controllerunitstr:'LM3FURY';
  797. flashbase:$00000000;
  798. flashsize:$00040000;
  799. srambase:$20000000;
  800. sramsize:$00010000
  801. ),
  802. // ct_lm3s6938,
  803. (
  804. controllertypestr:'LM3S6938';
  805. controllerunitstr:'LM3FURY';
  806. flashbase:$00000000;
  807. flashsize:$00040000;
  808. srambase:$20000000;
  809. sramsize:$00010000
  810. ),
  811. // ct_lm3s6950,
  812. (
  813. controllertypestr:'LM3S6950';
  814. controllerunitstr:'LM3FURY';
  815. flashbase:$00000000;
  816. flashsize:$00040000;
  817. srambase:$20000000;
  818. sramsize:$00010000
  819. ),
  820. // ct_lm3s6952,
  821. (
  822. controllertypestr:'LM3S6952';
  823. controllerunitstr:'LM3FURY';
  824. flashbase:$00000000;
  825. flashsize:$00040000;
  826. srambase:$20000000;
  827. sramsize:$00010000
  828. ),
  829. // ct_lm3s6965,
  830. (
  831. controllertypestr:'LM3S6965';
  832. controllerunitstr:'LM3FURY';
  833. flashbase:$00000000;
  834. flashsize:$00040000;
  835. srambase:$20000000;
  836. sramsize:$00010000
  837. ),
  838. // ct_lm3s8930,
  839. (
  840. controllertypestr:'LM3S8930';
  841. controllerunitstr:'LM3FURY';
  842. flashbase:$00000000;
  843. flashsize:$00040000;
  844. srambase:$20000000;
  845. sramsize:$00010000
  846. ),
  847. // ct_lm3s8933,
  848. (
  849. controllertypestr:'LM3S8933';
  850. controllerunitstr:'LM3FURY';
  851. flashbase:$00000000;
  852. flashsize:$00040000;
  853. srambase:$20000000;
  854. sramsize:$00010000
  855. ),
  856. // ct_lm3s8938,
  857. (
  858. controllertypestr:'LM3S8938';
  859. controllerunitstr:'LM3FURY';
  860. flashbase:$00000000;
  861. flashsize:$00040000;
  862. srambase:$20000000;
  863. sramsize:$00010000
  864. ),
  865. // ct_lm3s8962,
  866. (
  867. controllertypestr:'LM3S8962';
  868. controllerunitstr:'LM3FURY';
  869. flashbase:$00000000;
  870. flashsize:$00040000;
  871. srambase:$20000000;
  872. sramsize:$00010000
  873. ),
  874. // ct_lm3s8970,
  875. (
  876. controllertypestr:'LM3S8970';
  877. controllerunitstr:'LM3FURY';
  878. flashbase:$00000000;
  879. flashsize:$00040000;
  880. srambase:$20000000;
  881. sramsize:$00010000
  882. ),
  883. // ct_lm3s8971,
  884. (
  885. controllertypestr:'LM3S8971';
  886. controllerunitstr:'LM3FURY';
  887. flashbase:$00000000;
  888. flashsize:$00040000;
  889. srambase:$20000000;
  890. sramsize:$00010000
  891. ),
  892. { TI - Tempest parts - 256 K Flash, 64 K SRAM }
  893. // ct_lm3s5951,
  894. (
  895. controllertypestr:'LM3S5951';
  896. controllerunitstr:'LM3TEMPEST';
  897. flashbase:$00000000;
  898. flashsize:$00040000;
  899. srambase:$20000000;
  900. sramsize:$00010000
  901. ),
  902. // ct_lm3s5956,
  903. (
  904. controllertypestr:'LM3S5956';
  905. controllerunitstr:'LM3TEMPEST';
  906. flashbase:$00000000;
  907. flashsize:$00040000;
  908. srambase:$20000000;
  909. sramsize:$00010000
  910. ),
  911. // ct_lm3s1b21,
  912. (
  913. controllertypestr:'LM3S1B21';
  914. controllerunitstr:'LM3TEMPEST';
  915. flashbase:$00000000;
  916. flashsize:$00040000;
  917. srambase:$20000000;
  918. sramsize:$00010000
  919. ),
  920. // ct_lm3s2b93,
  921. (
  922. controllertypestr:'LM3S2B93';
  923. controllerunitstr:'LM3TEMPEST';
  924. flashbase:$00000000;
  925. flashsize:$00040000;
  926. srambase:$20000000;
  927. sramsize:$00010000
  928. ),
  929. // ct_lm3s5b91,
  930. (
  931. controllertypestr:'LM3S5B91';
  932. controllerunitstr:'LM3TEMPEST';
  933. flashbase:$00000000;
  934. flashsize:$00040000;
  935. srambase:$20000000;
  936. sramsize:$00010000
  937. ),
  938. // ct_lm3s9b81,
  939. (
  940. controllertypestr:'LM3S9B81';
  941. controllerunitstr:'LM3TEMPEST';
  942. flashbase:$00000000;
  943. flashsize:$00040000;
  944. srambase:$20000000;
  945. sramsize:$00010000
  946. ),
  947. // ct_lm3s9b90,
  948. (
  949. controllertypestr:'LM3S9B90';
  950. controllerunitstr:'LM3TEMPEST';
  951. flashbase:$00000000;
  952. flashsize:$00040000;
  953. srambase:$20000000;
  954. sramsize:$00010000
  955. ),
  956. // ct_lm3s9b92,
  957. (
  958. controllertypestr:'LM3S9B92';
  959. controllerunitstr:'LM3TEMPEST';
  960. flashbase:$00000000;
  961. flashsize:$00040000;
  962. srambase:$20000000;
  963. sramsize:$00010000
  964. ),
  965. // ct_lm3s9b95,
  966. (
  967. controllertypestr:'LM3S9B95';
  968. controllerunitstr:'LM3TEMPEST';
  969. flashbase:$00000000;
  970. flashsize:$00040000;
  971. srambase:$20000000;
  972. sramsize:$00010000
  973. ),
  974. // ct_lm3s9b96,
  975. (
  976. controllertypestr:'LM3S9B96';
  977. controllerunitstr:'LM3TEMPEST';
  978. flashbase:$00000000;
  979. flashsize:$00040000;
  980. srambase:$20000000;
  981. sramsize:$00010000
  982. ),
  983. //ct_SC32442b,
  984. (
  985. controllertypestr:'SC32442B';
  986. controllerunitstr:'sc32442b';
  987. flashbase:$00000000;
  988. flashsize:$00000000;
  989. srambase:$00000000;
  990. sramsize:$08000000
  991. ),
  992. // bare bones Thumb2
  993. (
  994. controllertypestr:'THUMB2_BARE';
  995. controllerunitstr:'THUMB2_BARE';
  996. flashbase:$00000000;
  997. flashsize:$00100000;
  998. srambase:$20000000;
  999. sramsize:$00100000
  1000. )
  1001. );
  1002. vfp_scalar = [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16,fpu_fpv4_s16];
  1003. { Supported optimizations, only used for information }
  1004. supported_optimizerswitches = genericlevel1optimizerswitches+
  1005. genericlevel2optimizerswitches+
  1006. genericlevel3optimizerswitches-
  1007. { no need to write info about those }
  1008. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  1009. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  1010. cs_opt_stackframe,cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath];
  1011. level1optimizerswitches = genericlevel1optimizerswitches;
  1012. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  1013. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
  1014. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [cs_opt_scheduler{,cs_opt_loopunroll}];
  1015. level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
  1016. type
  1017. tcpuflags =
  1018. (CPUARM_HAS_BX, { CPU supports the BX instruction }
  1019. CPUARM_HAS_BLX, { CPU supports the BLX rX instruction }
  1020. CPUARM_HAS_BLX_LABEL, { CPU supports the BLX <label> instruction }
  1021. CPUARM_HAS_CLZ, { CPU supports the CLZ instruction }
  1022. CPUARM_HAS_EDSP, { CPU supports the PLD,STRD,LDRD,MCRR and MRRC instructions }
  1023. CPUARM_HAS_REV, { CPU supports the REV instruction }
  1024. CPUARM_HAS_RBIT, { CPU supports the RBIT instruction }
  1025. CPUARM_HAS_DMB, { CPU has memory barrier instructions (DMB, DSB, ISB) }
  1026. CPUARM_HAS_LDREX,
  1027. CPUARM_HAS_IDIV
  1028. );
  1029. const
  1030. cpu_capabilities : array[tcputype] of set of tcpuflags =
  1031. ( { cpu_none } [],
  1032. { cpu_armv3 } [],
  1033. { cpu_armv4 } [],
  1034. { cpu_armv4t } [CPUARM_HAS_BX],
  1035. { cpu_armv5 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ],
  1036. { cpu_armv5t } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ],
  1037. { cpu_armv5te } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP],
  1038. { cpu_armv5tej } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP],
  1039. { cpu_armv6 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1040. { cpu_armv6k } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1041. { cpu_armv6t2 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX],
  1042. { cpu_armv6z } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1043. { the identifier armv7 is should not be used, it is considered being equal to armv7a }
  1044. { cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB],
  1045. { cpu_armv7a } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB],
  1046. { cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB],
  1047. { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV,CPUARM_HAS_DMB],
  1048. { cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV,CPUARM_HAS_DMB]
  1049. );
  1050. Implementation
  1051. end.