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aasmcpu.pas
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bc0c94c204
fpcdefs.inc: Set fpc_compiler_has_fixup_jmps for powerpcXX and mips CPUs.
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13 лет назад |
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aoptcpu.pas
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0c8546f94c
* more MIPS code of David Zhang integrated
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15 лет назад |
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aoptcpub.pas
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93e0dd9c2f
* Patch from Fuxin Zhang: other mips and mipsel CPUs changes
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13 лет назад |
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aoptcpud.pas
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0c8546f94c
* more MIPS code of David Zhang integrated
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15 лет назад |
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cgcpu.pas
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db72b8d7fd
* TCGMips.a_loadfpu_reg_cgpara: temps of type Double need 8-byte alignment, according to description of sdcX/ldcX instructions. Using TCGSize2Size to specify alignment is somewhat weird, but it is being used in other CPU back-ends and looks working.
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12 лет назад |
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cpubase.pas
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e327b4581c
Use TRegNameTable instead of array[tregisterindex] of string[10]
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13 лет назад |
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cpugas.pas
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e6863aeb80
* typo fixed, patch by Mark Morgan Lloyd
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12 лет назад |
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cpuinfo.pas
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305206354a
Add arch and abi values for mips cpu
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13 лет назад |
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cpunode.pas
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a3ef2b42a8
Remove more TABs in sources
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13 лет назад |
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cpupara.pas
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bf46526cc7
Set register_used boolean only for calleeside
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13 лет назад |
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cpupi.pas
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7bd7cf275c
handle po_nostackframe for calc_stack_size
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13 лет назад |
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cputarg.pas
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37a7c1fc25
Add Dwarf debug info generation by default for mips cpu
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13 лет назад |
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hlcgcpu.pas
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a3ef2b42a8
Remove more TABs in sources
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13 лет назад |
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itcpugas.pas
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3d2a27c66c
* fix fpu register type
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13 лет назад |
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mipsreg.dat
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944d500d55
Change std reg names to allow use with GAS assembler
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13 лет назад |
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ncpuadd.pas
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93e0dd9c2f
* Patch from Fuxin Zhang: other mips and mipsel CPUs changes
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13 лет назад |
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ncpucall.pas
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a3ef2b42a8
Remove more TABs in sources
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13 лет назад |
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ncpucnv.pas
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a3ef2b42a8
Remove more TABs in sources
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13 лет назад |
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ncpuinln.pas
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f54365db94
* adapted more fpc-mips stuff to trunk
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15 лет назад |
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ncpuld.pas
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c2cd8246cb
Override tloadnode.pass_1 to for use of got for shared library variables and genrate_picvaraccess
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13 лет назад |
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ncpumat.pas
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d01ec10f45
Fix tw22326 for mips CPU
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13 лет назад |
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ncpuset.pas
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b023627f6a
* converted tcgcasenode.pass_generate_code() to hlcgobj
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14 лет назад |
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opcode.inc
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87b6bb5053
+ Add .cpXXX pseudo-instruction for PIC code
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13 лет назад |
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racpugas.pas
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a3ef2b42a8
Remove more TABs in sources
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13 лет назад |
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rgcpu.pas
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de4a96f96d
* fixes several register allocation related mips issues
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13 лет назад |
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rmipscon.inc
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de4a96f96d
* fixes several register allocation related mips issues
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13 лет назад |
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rmipsdwf.inc
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f58fcdf401
+ basic mips stuff
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20 лет назад |
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rmipsgas.inc
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ae37b9f5b9
* fix floating point registers gas name
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13 лет назад |
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rmipsgri.inc
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ae37b9f5b9
* fix floating point registers gas name
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13 лет назад |
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rmipsgss.inc
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f58fcdf401
+ basic mips stuff
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20 лет назад |
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rmipsnor.inc
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f58fcdf401
+ basic mips stuff
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20 лет назад |
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rmipsnum.inc
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de4a96f96d
* fixes several register allocation related mips issues
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13 лет назад |
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rmipsrni.inc
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f58fcdf401
+ basic mips stuff
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20 лет назад |
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rmipssri.inc
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944d500d55
Change std reg names to allow use with GAS assembler
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13 лет назад |
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rmipssta.inc
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f58fcdf401
+ basic mips stuff
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20 лет назад |
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rmipsstd.inc
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944d500d55
Change std reg names to allow use with GAS assembler
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13 лет назад |
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rmipssup.inc
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de4a96f96d
* fixes several register allocation related mips issues
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13 лет назад |
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strinst.inc
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87b6bb5053
+ Add .cpXXX pseudo-instruction for PIC code
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13 лет назад |
sergei
db72b8d7fd
* TCGMips.a_loadfpu_reg_cgpara: temps of type Double need 8-byte alignment, according to description of sdcX/ldcX instructions. Using TCGSize2Size to specify alignment is somewhat weird, but it is being used in other CPU back-ends and looks working.