aoptx86.pas 396 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Jonas Maebe
  3. This unit contains the peephole optimizer.
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit aoptx86;
  18. {$i fpcdefs.inc}
  19. {$define DEBUG_AOPTCPU}
  20. interface
  21. uses
  22. globtype,
  23. cpubase,
  24. aasmtai,aasmcpu,
  25. cgbase,cgutils,
  26. aopt,aoptobj;
  27. type
  28. TOptsToCheck = (
  29. aoc_MovAnd2Mov_3
  30. );
  31. TX86AsmOptimizer = class(TAsmOptimizer)
  32. { some optimizations are very expensive to check, so the
  33. pre opt pass can be used to set some flags, depending on the found
  34. instructions if it is worth to check a certain optimization }
  35. OptsToCheck : set of TOptsToCheck;
  36. function RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean; override;
  37. function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; override;
  38. function RegReadByInstruction(reg : TRegister; hp : tai) : boolean;
  39. function RegInInstruction(Reg: TRegister; p1: tai): Boolean;override;
  40. function GetNextInstructionUsingReg(Current: tai; out Next: tai; reg: TRegister): Boolean;
  41. { This version of GetNextInstructionUsingReg will look across conditional jumps,
  42. potentially allowing further optimisation (although it might need to know if
  43. it crossed a conditional jump. }
  44. function GetNextInstructionUsingRegCond(Current: tai; out Next: tai; reg: TRegister; var CrossJump: Boolean): Boolean;
  45. {
  46. In comparison with GetNextInstructionUsingReg, GetNextInstructionUsingRegTrackingUse tracks
  47. the use of a register by allocs/dealloc, so it can ignore calls.
  48. In the following example, GetNextInstructionUsingReg will return the second movq,
  49. GetNextInstructionUsingRegTrackingUse won't.
  50. movq %rdi,%rax
  51. # Register rdi released
  52. # Register rdi allocated
  53. movq %rax,%rdi
  54. While in this example:
  55. movq %rdi,%rax
  56. call proc
  57. movq %rdi,%rax
  58. GetNextInstructionUsingRegTrackingUse will return the second instruction while GetNextInstructionUsingReg
  59. won't.
  60. }
  61. function GetNextInstructionUsingRegTrackingUse(Current: tai; out Next: tai; reg: TRegister): Boolean;
  62. function RegModifiedByInstruction(Reg: TRegister; p1: tai): boolean; override;
  63. private
  64. function SkipSimpleInstructions(var hp1: tai): Boolean;
  65. protected
  66. class function IsMOVZXAcceptable: Boolean; static; inline;
  67. { checks whether loading a new value in reg1 overwrites the entirety of reg2 }
  68. function Reg1WriteOverwritesReg2Entirely(reg1, reg2: tregister): boolean;
  69. { checks whether reading the value in reg1 depends on the value of reg2. This
  70. is very similar to SuperRegisterEquals, except it takes into account that
  71. R_SUBH and R_SUBL are independendent (e.g. reading from AL does not
  72. depend on the value in AH). }
  73. function Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
  74. { Replaces all references to AOldReg in a memory reference to ANewReg }
  75. class function ReplaceRegisterInRef(var ref: TReference; const AOldReg, ANewReg: TRegister): Boolean; static;
  76. { Replaces all references to AOldReg in an operand to ANewReg }
  77. class function ReplaceRegisterInOper(const p: taicpu; const OperIdx: Integer; const AOldReg, ANewReg: TRegister): Boolean; static;
  78. { Replaces all references to AOldReg in an instruction to ANewReg,
  79. except where the register is being written }
  80. function ReplaceRegisterInInstruction(const p: taicpu; const AOldReg, ANewReg: TRegister): Boolean;
  81. { Returns true if the reference only refers to ESP or EBP (or their 64-bit equivalents),
  82. or writes to a global symbol }
  83. class function IsRefSafe(const ref: PReference): Boolean; static; inline;
  84. { Returns true if the given MOV instruction can be safely converted to CMOV }
  85. class function CanBeCMOV(p : tai) : boolean; static;
  86. { Converts the LEA instruction to ADD/INC/SUB/DEC. Returns True if the
  87. conversion was successful }
  88. function ConvertLEA(const p : taicpu): Boolean;
  89. function DeepMOVOpt(const p_mov: taicpu; const hp: taicpu): Boolean;
  90. procedure DebugMsg(const s : string; p : tai);inline;
  91. class function IsExitCode(p : tai) : boolean; static;
  92. class function isFoldableArithOp(hp1 : taicpu; reg : tregister) : boolean; static;
  93. procedure RemoveLastDeallocForFuncRes(p : tai);
  94. function DoSubAddOpt(var p : tai) : Boolean;
  95. function PrePeepholeOptSxx(var p : tai) : boolean;
  96. function PrePeepholeOptIMUL(var p : tai) : boolean;
  97. function OptPass1Test(var p: tai): boolean;
  98. function OptPass1Add(var p: tai): boolean;
  99. function OptPass1AND(var p : tai) : boolean;
  100. function OptPass1_V_MOVAP(var p : tai) : boolean;
  101. function OptPass1VOP(var p : tai) : boolean;
  102. function OptPass1MOV(var p : tai) : boolean;
  103. function OptPass1Movx(var p : tai) : boolean;
  104. function OptPass1MOVXX(var p : tai) : boolean;
  105. function OptPass1OP(var p : tai) : boolean;
  106. function OptPass1LEA(var p : tai) : boolean;
  107. function OptPass1Sub(var p : tai) : boolean;
  108. function OptPass1SHLSAL(var p : tai) : boolean;
  109. function OptPass1FSTP(var p : tai) : boolean;
  110. function OptPass1FLD(var p : tai) : boolean;
  111. function OptPass1Cmp(var p : tai) : boolean;
  112. function OptPass1PXor(var p : tai) : boolean;
  113. function OptPass1VPXor(var p: tai): boolean;
  114. function OptPass1Imul(var p : tai) : boolean;
  115. function OptPass1Jcc(var p : tai) : boolean;
  116. function OptPass2Movx(var p : tai): Boolean;
  117. function OptPass2MOV(var p : tai) : boolean;
  118. function OptPass2Imul(var p : tai) : boolean;
  119. function OptPass2Jmp(var p : tai) : boolean;
  120. function OptPass2Jcc(var p : tai) : boolean;
  121. function OptPass2Lea(var p: tai): Boolean;
  122. function OptPass2SUB(var p: tai): Boolean;
  123. function OptPass2ADD(var p : tai): Boolean;
  124. function OptPass2SETcc(var p : tai) : boolean;
  125. function CheckMemoryWrite(var first_mov, second_mov: taicpu): Boolean;
  126. function PostPeepholeOptMov(var p : tai) : Boolean;
  127. function PostPeepholeOptMovzx(var p : tai) : Boolean;
  128. {$ifdef x86_64} { These post-peephole optimisations only affect 64-bit registers. [Kit] }
  129. function PostPeepholeOptXor(var p : tai) : Boolean;
  130. {$endif}
  131. function PostPeepholeOptAnd(var p : tai) : boolean;
  132. function PostPeepholeOptMOVSX(var p : tai) : boolean;
  133. function PostPeepholeOptCmp(var p : tai) : Boolean;
  134. function PostPeepholeOptTestOr(var p : tai) : Boolean;
  135. function PostPeepholeOptCall(var p : tai) : Boolean;
  136. function PostPeepholeOptLea(var p : tai) : Boolean;
  137. function PostPeepholeOptPush(var p: tai): Boolean;
  138. function PostPeepholeOptShr(var p : tai) : boolean;
  139. procedure ConvertJumpToRET(const p: tai; const ret_p: tai);
  140. function CheckJumpMovTransferOpt(var p: tai; hp1: tai; LoopCount: Integer; out Count: Integer): Boolean;
  141. procedure SwapMovCmp(var p, hp1: tai);
  142. { Processor-dependent reference optimisation }
  143. class procedure OptimizeRefs(var p: taicpu); static;
  144. end;
  145. function MatchInstruction(const instr: tai; const op: TAsmOp; const opsize: topsizes): boolean;
  146. function MatchInstruction(const instr: tai; const op1,op2: TAsmOp; const opsize: topsizes): boolean;
  147. function MatchInstruction(const instr: tai; const op1,op2,op3: TAsmOp; const opsize: topsizes): boolean;
  148. function MatchInstruction(const instr: tai; const ops: array of TAsmOp; const opsize: topsizes): boolean;
  149. function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
  150. function MatchOperand(const oper: TOper; const a: tcgint): boolean; inline;
  151. function MatchOperand(const oper1: TOper; const oper2: TOper): boolean;
  152. {$if max_operands>2}
  153. function MatchOperand(const oper1: TOper; const oper2: TOper; const oper3: TOper): boolean;
  154. {$endif max_operands>2}
  155. function RefsEqual(const r1, r2: treference): boolean;
  156. function MatchReference(const ref : treference;base,index : TRegister) : Boolean;
  157. { returns true, if ref is a reference using only the registers passed as base and index
  158. and having an offset }
  159. function MatchReferenceWithOffset(const ref : treference;base,index : TRegister) : Boolean;
  160. implementation
  161. uses
  162. cutils,verbose,
  163. systems,
  164. globals,
  165. cpuinfo,
  166. procinfo,
  167. paramgr,
  168. aasmbase,
  169. aoptbase,aoptutils,
  170. symconst,symsym,
  171. cgx86,
  172. itcpugas;
  173. {$ifdef DEBUG_AOPTCPU}
  174. const
  175. SPeepholeOptimization: shortstring = 'Peephole Optimization: ';
  176. {$else DEBUG_AOPTCPU}
  177. { Empty strings help the optimizer to remove string concatenations that won't
  178. ever appear to the user on release builds. [Kit] }
  179. const
  180. SPeepholeOptimization = '';
  181. {$endif DEBUG_AOPTCPU}
  182. LIST_STEP_SIZE = 4;
  183. function MatchInstruction(const instr: tai; const op: TAsmOp; const opsize: topsizes): boolean;
  184. begin
  185. result :=
  186. (instr.typ = ait_instruction) and
  187. (taicpu(instr).opcode = op) and
  188. ((opsize = []) or (taicpu(instr).opsize in opsize));
  189. end;
  190. function MatchInstruction(const instr: tai; const op1,op2: TAsmOp; const opsize: topsizes): boolean;
  191. begin
  192. result :=
  193. (instr.typ = ait_instruction) and
  194. ((taicpu(instr).opcode = op1) or
  195. (taicpu(instr).opcode = op2)
  196. ) and
  197. ((opsize = []) or (taicpu(instr).opsize in opsize));
  198. end;
  199. function MatchInstruction(const instr: tai; const op1,op2,op3: TAsmOp; const opsize: topsizes): boolean;
  200. begin
  201. result :=
  202. (instr.typ = ait_instruction) and
  203. ((taicpu(instr).opcode = op1) or
  204. (taicpu(instr).opcode = op2) or
  205. (taicpu(instr).opcode = op3)
  206. ) and
  207. ((opsize = []) or (taicpu(instr).opsize in opsize));
  208. end;
  209. function MatchInstruction(const instr : tai;const ops : array of TAsmOp;
  210. const opsize : topsizes) : boolean;
  211. var
  212. op : TAsmOp;
  213. begin
  214. result:=false;
  215. for op in ops do
  216. begin
  217. if (instr.typ = ait_instruction) and
  218. (taicpu(instr).opcode = op) and
  219. ((opsize = []) or (taicpu(instr).opsize in opsize)) then
  220. begin
  221. result:=true;
  222. exit;
  223. end;
  224. end;
  225. end;
  226. function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
  227. begin
  228. result := (oper.typ = top_reg) and (oper.reg = reg);
  229. end;
  230. function MatchOperand(const oper: TOper; const a: tcgint): boolean; inline;
  231. begin
  232. result := (oper.typ = top_const) and (oper.val = a);
  233. end;
  234. function MatchOperand(const oper1: TOper; const oper2: TOper): boolean;
  235. begin
  236. result := oper1.typ = oper2.typ;
  237. if result then
  238. case oper1.typ of
  239. top_const:
  240. Result:=oper1.val = oper2.val;
  241. top_reg:
  242. Result:=oper1.reg = oper2.reg;
  243. top_ref:
  244. Result:=RefsEqual(oper1.ref^, oper2.ref^);
  245. else
  246. internalerror(2013102801);
  247. end
  248. end;
  249. function MatchOperand(const oper1: TOper; const oper2: TOper; const oper3: TOper): boolean;
  250. begin
  251. result := (oper1.typ = oper2.typ) and (oper1.typ = oper3.typ);
  252. if result then
  253. case oper1.typ of
  254. top_const:
  255. Result:=(oper1.val = oper2.val) and (oper1.val = oper3.val);
  256. top_reg:
  257. Result:=(oper1.reg = oper2.reg) and (oper1.reg = oper3.reg);
  258. top_ref:
  259. Result:=RefsEqual(oper1.ref^, oper2.ref^) and RefsEqual(oper1.ref^, oper3.ref^);
  260. else
  261. internalerror(2020052401);
  262. end
  263. end;
  264. function RefsEqual(const r1, r2: treference): boolean;
  265. begin
  266. RefsEqual :=
  267. (r1.offset = r2.offset) and
  268. (r1.segment = r2.segment) and (r1.base = r2.base) and
  269. (r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
  270. (r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
  271. (r1.relsymbol = r2.relsymbol) and
  272. (r1.volatility=[]) and
  273. (r2.volatility=[]);
  274. end;
  275. function MatchReference(const ref : treference;base,index : TRegister) : Boolean;
  276. begin
  277. Result:=(ref.offset=0) and
  278. (ref.scalefactor in [0,1]) and
  279. (ref.segment=NR_NO) and
  280. (ref.symbol=nil) and
  281. (ref.relsymbol=nil) and
  282. ((base=NR_INVALID) or
  283. (ref.base=base)) and
  284. ((index=NR_INVALID) or
  285. (ref.index=index)) and
  286. (ref.volatility=[]);
  287. end;
  288. function MatchReferenceWithOffset(const ref : treference;base,index : TRegister) : Boolean;
  289. begin
  290. Result:=(ref.scalefactor in [0,1]) and
  291. (ref.segment=NR_NO) and
  292. (ref.symbol=nil) and
  293. (ref.relsymbol=nil) and
  294. ((base=NR_INVALID) or
  295. (ref.base=base)) and
  296. ((index=NR_INVALID) or
  297. (ref.index=index)) and
  298. (ref.volatility=[]);
  299. end;
  300. function InstrReadsFlags(p: tai): boolean;
  301. begin
  302. InstrReadsFlags := true;
  303. case p.typ of
  304. ait_instruction:
  305. if InsProp[taicpu(p).opcode].Ch*
  306. [Ch_RCarryFlag,Ch_RParityFlag,Ch_RAuxiliaryFlag,Ch_RZeroFlag,Ch_RSignFlag,Ch_ROverflowFlag,
  307. Ch_RWCarryFlag,Ch_RWParityFlag,Ch_RWAuxiliaryFlag,Ch_RWZeroFlag,Ch_RWSignFlag,Ch_RWOverflowFlag,
  308. Ch_RFlags,Ch_RWFlags,Ch_RFLAGScc,Ch_All]<>[] then
  309. exit;
  310. ait_label:
  311. exit;
  312. else
  313. ;
  314. end;
  315. InstrReadsFlags := false;
  316. end;
  317. function TX86AsmOptimizer.GetNextInstructionUsingReg(Current: tai; out Next: tai; reg: TRegister): Boolean;
  318. begin
  319. Next:=Current;
  320. repeat
  321. Result:=GetNextInstruction(Next,Next);
  322. until not (Result) or
  323. not(cs_opt_level3 in current_settings.optimizerswitches) or
  324. (Next.typ<>ait_instruction) or
  325. RegInInstruction(reg,Next) or
  326. is_calljmp(taicpu(Next).opcode);
  327. end;
  328. function TX86AsmOptimizer.GetNextInstructionUsingRegCond(Current: tai; out Next: tai; reg: TRegister; var CrossJump: Boolean): Boolean;
  329. begin
  330. { Note, CrossJump keeps its input value if a conditional jump is not found - it doesn't get set to False }
  331. Next := Current;
  332. repeat
  333. Result := GetNextInstruction(Next,Next);
  334. if Result and (Next.typ=ait_instruction) and is_calljmp(taicpu(Next).opcode) then
  335. if is_calljmpuncond(taicpu(Next).opcode) then
  336. begin
  337. Result := False;
  338. Exit;
  339. end
  340. else
  341. CrossJump := True;
  342. until not Result or
  343. not (cs_opt_level3 in current_settings.optimizerswitches) or
  344. (Next.typ <> ait_instruction) or
  345. RegInInstruction(reg,Next);
  346. end;
  347. function TX86AsmOptimizer.GetNextInstructionUsingRegTrackingUse(Current: tai; out Next: tai; reg: TRegister): Boolean;
  348. begin
  349. if not(cs_opt_level3 in current_settings.optimizerswitches) then
  350. begin
  351. Result:=GetNextInstruction(Current,Next);
  352. exit;
  353. end;
  354. Next:=tai(Current.Next);
  355. Result:=false;
  356. while assigned(Next) do
  357. begin
  358. if ((Next.typ=ait_instruction) and is_calljmp(taicpu(Next).opcode) and not(taicpu(Next).opcode=A_CALL)) or
  359. ((Next.typ=ait_regalloc) and (getsupreg(tai_regalloc(Next).reg)=getsupreg(reg))) or
  360. ((Next.typ=ait_label) and not(labelCanBeSkipped(Tai_Label(Next)))) then
  361. exit
  362. else if (Next.typ=ait_instruction) and RegInInstruction(reg,Next) and not(taicpu(Next).opcode=A_CALL) then
  363. begin
  364. Result:=true;
  365. exit;
  366. end;
  367. Next:=tai(Next.Next);
  368. end;
  369. end;
  370. function TX86AsmOptimizer.InstructionLoadsFromReg(const reg: TRegister;const hp: tai): boolean;
  371. begin
  372. Result:=RegReadByInstruction(reg,hp);
  373. end;
  374. function TX86AsmOptimizer.RegReadByInstruction(reg: TRegister; hp: tai): boolean;
  375. var
  376. p: taicpu;
  377. opcount: longint;
  378. begin
  379. RegReadByInstruction := false;
  380. if hp.typ <> ait_instruction then
  381. exit;
  382. p := taicpu(hp);
  383. case p.opcode of
  384. A_CALL:
  385. regreadbyinstruction := true;
  386. A_IMUL:
  387. case p.ops of
  388. 1:
  389. regReadByInstruction := RegInOp(reg,p.oper[0]^) or
  390. (
  391. ((getregtype(reg)=R_INTREGISTER) and (getsupreg(reg)=RS_EAX)) and
  392. ((getsubreg(reg)<>R_SUBH) or (p.opsize<>S_B))
  393. );
  394. 2,3:
  395. regReadByInstruction :=
  396. reginop(reg,p.oper[0]^) or
  397. reginop(reg,p.oper[1]^);
  398. else
  399. InternalError(2019112801);
  400. end;
  401. A_MUL:
  402. begin
  403. regReadByInstruction := RegInOp(reg,p.oper[0]^) or
  404. (
  405. ((getregtype(reg)=R_INTREGISTER) and (getsupreg(reg)=RS_EAX)) and
  406. ((getsubreg(reg)<>R_SUBH) or (p.opsize<>S_B))
  407. );
  408. end;
  409. A_IDIV,A_DIV:
  410. begin
  411. regReadByInstruction := RegInOp(reg,p.oper[0]^) or
  412. (
  413. (getregtype(reg)=R_INTREGISTER) and
  414. (
  415. (getsupreg(reg)=RS_EAX) or ((getsupreg(reg)=RS_EDX) and (p.opsize<>S_B))
  416. )
  417. );
  418. end;
  419. else
  420. begin
  421. if (p.opcode=A_LEA) and is_segment_reg(reg) then
  422. begin
  423. RegReadByInstruction := false;
  424. exit;
  425. end;
  426. for opcount := 0 to p.ops-1 do
  427. if (p.oper[opCount]^.typ = top_ref) and
  428. RegInRef(reg,p.oper[opcount]^.ref^) then
  429. begin
  430. RegReadByInstruction := true;
  431. exit
  432. end;
  433. { special handling for SSE MOVSD }
  434. if (p.opcode=A_MOVSD) and (p.ops>0) then
  435. begin
  436. if p.ops<>2 then
  437. internalerror(2017042702);
  438. regReadByInstruction := reginop(reg,p.oper[0]^) or
  439. (
  440. (p.oper[1]^.typ=top_reg) and (p.oper[0]^.typ=top_reg) and reginop(reg, p.oper[1]^)
  441. );
  442. exit;
  443. end;
  444. with insprop[p.opcode] do
  445. begin
  446. if getregtype(reg)=R_INTREGISTER then
  447. begin
  448. case getsupreg(reg) of
  449. RS_EAX:
  450. if [Ch_REAX,Ch_RWEAX,Ch_MEAX]*Ch<>[] then
  451. begin
  452. RegReadByInstruction := true;
  453. exit
  454. end;
  455. RS_ECX:
  456. if [Ch_RECX,Ch_RWECX,Ch_MECX]*Ch<>[] then
  457. begin
  458. RegReadByInstruction := true;
  459. exit
  460. end;
  461. RS_EDX:
  462. if [Ch_REDX,Ch_RWEDX,Ch_MEDX]*Ch<>[] then
  463. begin
  464. RegReadByInstruction := true;
  465. exit
  466. end;
  467. RS_EBX:
  468. if [Ch_REBX,Ch_RWEBX,Ch_MEBX]*Ch<>[] then
  469. begin
  470. RegReadByInstruction := true;
  471. exit
  472. end;
  473. RS_ESP:
  474. if [Ch_RESP,Ch_RWESP,Ch_MESP]*Ch<>[] then
  475. begin
  476. RegReadByInstruction := true;
  477. exit
  478. end;
  479. RS_EBP:
  480. if [Ch_REBP,Ch_RWEBP,Ch_MEBP]*Ch<>[] then
  481. begin
  482. RegReadByInstruction := true;
  483. exit
  484. end;
  485. RS_ESI:
  486. if [Ch_RESI,Ch_RWESI,Ch_MESI]*Ch<>[] then
  487. begin
  488. RegReadByInstruction := true;
  489. exit
  490. end;
  491. RS_EDI:
  492. if [Ch_REDI,Ch_RWEDI,Ch_MEDI]*Ch<>[] then
  493. begin
  494. RegReadByInstruction := true;
  495. exit
  496. end;
  497. end;
  498. end;
  499. if SuperRegistersEqual(reg,NR_DEFAULTFLAGS) then
  500. begin
  501. if (Ch_RFLAGScc in Ch) and not(getsubreg(reg) in [R_SUBW,R_SUBD,R_SUBQ]) then
  502. begin
  503. case p.condition of
  504. C_A,C_NBE, { CF=0 and ZF=0 }
  505. C_BE,C_NA: { CF=1 or ZF=1 }
  506. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGCARRY,R_SUBFLAGZERO];
  507. C_AE,C_NB,C_NC, { CF=0 }
  508. C_B,C_NAE,C_C: { CF=1 }
  509. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGCARRY];
  510. C_NE,C_NZ, { ZF=0 }
  511. C_E,C_Z: { ZF=1 }
  512. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGZERO];
  513. C_G,C_NLE, { ZF=0 and SF=OF }
  514. C_LE,C_NG: { ZF=1 or SF<>OF }
  515. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGZERO,R_SUBFLAGSIGN,R_SUBFLAGOVERFLOW];
  516. C_GE,C_NL, { SF=OF }
  517. C_L,C_NGE: { SF<>OF }
  518. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGSIGN,R_SUBFLAGOVERFLOW];
  519. C_NO, { OF=0 }
  520. C_O: { OF=1 }
  521. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGOVERFLOW];
  522. C_NP,C_PO, { PF=0 }
  523. C_P,C_PE: { PF=1 }
  524. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGPARITY];
  525. C_NS, { SF=0 }
  526. C_S: { SF=1 }
  527. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGSIGN];
  528. else
  529. internalerror(2017042701);
  530. end;
  531. if RegReadByInstruction then
  532. exit;
  533. end;
  534. case getsubreg(reg) of
  535. R_SUBW,R_SUBD,R_SUBQ:
  536. RegReadByInstruction :=
  537. [Ch_RCarryFlag,Ch_RParityFlag,Ch_RAuxiliaryFlag,Ch_RZeroFlag,Ch_RSignFlag,Ch_ROverflowFlag,
  538. Ch_RWCarryFlag,Ch_RWParityFlag,Ch_RWAuxiliaryFlag,Ch_RWZeroFlag,Ch_RWSignFlag,Ch_RWOverflowFlag,
  539. Ch_RDirFlag,Ch_RFlags,Ch_RWFlags,Ch_RFLAGScc]*Ch<>[];
  540. R_SUBFLAGCARRY:
  541. RegReadByInstruction:=[Ch_RCarryFlag,Ch_RWCarryFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  542. R_SUBFLAGPARITY:
  543. RegReadByInstruction:=[Ch_RParityFlag,Ch_RWParityFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  544. R_SUBFLAGAUXILIARY:
  545. RegReadByInstruction:=[Ch_RAuxiliaryFlag,Ch_RWAuxiliaryFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  546. R_SUBFLAGZERO:
  547. RegReadByInstruction:=[Ch_RZeroFlag,Ch_RWZeroFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  548. R_SUBFLAGSIGN:
  549. RegReadByInstruction:=[Ch_RSignFlag,Ch_RWSignFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  550. R_SUBFLAGOVERFLOW:
  551. RegReadByInstruction:=[Ch_ROverflowFlag,Ch_RWOverflowFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  552. R_SUBFLAGINTERRUPT:
  553. RegReadByInstruction:=[Ch_RFlags,Ch_RWFlags]*Ch<>[];
  554. R_SUBFLAGDIRECTION:
  555. RegReadByInstruction:=[Ch_RDirFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  556. else
  557. internalerror(2017042601);
  558. end;
  559. exit;
  560. end;
  561. if (Ch_NoReadIfEqualRegs in Ch) and (p.ops=2) and
  562. (p.oper[0]^.typ=top_reg) and (p.oper[1]^.typ=top_reg) and
  563. (p.oper[0]^.reg=p.oper[1]^.reg) then
  564. exit;
  565. if ([CH_RWOP1,CH_ROP1,CH_MOP1]*Ch<>[]) and reginop(reg,p.oper[0]^) then
  566. begin
  567. RegReadByInstruction := true;
  568. exit
  569. end;
  570. if ([Ch_RWOP2,Ch_ROP2,Ch_MOP2]*Ch<>[]) and reginop(reg,p.oper[1]^) then
  571. begin
  572. RegReadByInstruction := true;
  573. exit
  574. end;
  575. if ([Ch_RWOP3,Ch_ROP3,Ch_MOP3]*Ch<>[]) and reginop(reg,p.oper[2]^) then
  576. begin
  577. RegReadByInstruction := true;
  578. exit
  579. end;
  580. if ([Ch_RWOP4,Ch_ROP4,Ch_MOP4]*Ch<>[]) and reginop(reg,p.oper[3]^) then
  581. begin
  582. RegReadByInstruction := true;
  583. exit
  584. end;
  585. end;
  586. end;
  587. end;
  588. end;
  589. function TX86AsmOptimizer.RegInInstruction(Reg: TRegister; p1: tai): Boolean;
  590. begin
  591. result:=false;
  592. if p1.typ<>ait_instruction then
  593. exit;
  594. if (Ch_All in insprop[taicpu(p1).opcode].Ch) then
  595. exit(true);
  596. if (getregtype(reg)=R_INTREGISTER) and
  597. { change information for xmm movsd are not correct }
  598. ((taicpu(p1).opcode<>A_MOVSD) or (taicpu(p1).ops=0)) then
  599. begin
  600. case getsupreg(reg) of
  601. { RS_EAX = RS_RAX on x86-64 }
  602. RS_EAX:
  603. result:=([Ch_REAX,Ch_RRAX,Ch_WEAX,Ch_WRAX,Ch_RWEAX,Ch_RWRAX,Ch_MEAX,Ch_MRAX]*insprop[taicpu(p1).opcode].Ch)<>[];
  604. RS_ECX:
  605. result:=([Ch_RECX,Ch_RRCX,Ch_WECX,Ch_WRCX,Ch_RWECX,Ch_RWRCX,Ch_MECX,Ch_MRCX]*insprop[taicpu(p1).opcode].Ch)<>[];
  606. RS_EDX:
  607. result:=([Ch_REDX,Ch_RRDX,Ch_WEDX,Ch_WRDX,Ch_RWEDX,Ch_RWRDX,Ch_MEDX,Ch_MRDX]*insprop[taicpu(p1).opcode].Ch)<>[];
  608. RS_EBX:
  609. result:=([Ch_REBX,Ch_RRBX,Ch_WEBX,Ch_WRBX,Ch_RWEBX,Ch_RWRBX,Ch_MEBX,Ch_MRBX]*insprop[taicpu(p1).opcode].Ch)<>[];
  610. RS_ESP:
  611. result:=([Ch_RESP,Ch_RRSP,Ch_WESP,Ch_WRSP,Ch_RWESP,Ch_RWRSP,Ch_MESP,Ch_MRSP]*insprop[taicpu(p1).opcode].Ch)<>[];
  612. RS_EBP:
  613. result:=([Ch_REBP,Ch_RRBP,Ch_WEBP,Ch_WRBP,Ch_RWEBP,Ch_RWRBP,Ch_MEBP,Ch_MRBP]*insprop[taicpu(p1).opcode].Ch)<>[];
  614. RS_ESI:
  615. result:=([Ch_RESI,Ch_RRSI,Ch_WESI,Ch_WRSI,Ch_RWESI,Ch_RWRSI,Ch_MESI,Ch_MRSI,Ch_RMemEDI]*insprop[taicpu(p1).opcode].Ch)<>[];
  616. RS_EDI:
  617. result:=([Ch_REDI,Ch_RRDI,Ch_WEDI,Ch_WRDI,Ch_RWEDI,Ch_RWRDI,Ch_MEDI,Ch_MRDI,Ch_WMemEDI]*insprop[taicpu(p1).opcode].Ch)<>[];
  618. else
  619. ;
  620. end;
  621. if result then
  622. exit;
  623. end
  624. else if SuperRegistersEqual(reg,NR_DEFAULTFLAGS) then
  625. begin
  626. if ([Ch_RFlags,Ch_WFlags,Ch_RWFlags,Ch_RFLAGScc]*insprop[taicpu(p1).opcode].Ch)<>[] then
  627. exit(true);
  628. case getsubreg(reg) of
  629. R_SUBFLAGCARRY:
  630. Result:=([Ch_RCarryFlag,Ch_RWCarryFlag,Ch_W0CarryFlag,Ch_W1CarryFlag,Ch_WCarryFlag,Ch_WUCarryFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  631. R_SUBFLAGPARITY:
  632. Result:=([Ch_RParityFlag,Ch_RWParityFlag,Ch_W0ParityFlag,Ch_W1ParityFlag,Ch_WParityFlag,Ch_WUParityFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  633. R_SUBFLAGAUXILIARY:
  634. Result:=([Ch_RAuxiliaryFlag,Ch_RWAuxiliaryFlag,Ch_W0AuxiliaryFlag,Ch_W1AuxiliaryFlag,Ch_WAuxiliaryFlag,Ch_WUAuxiliaryFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  635. R_SUBFLAGZERO:
  636. Result:=([Ch_RZeroFlag,Ch_RWZeroFlag,Ch_W0ZeroFlag,Ch_W1ZeroFlag,Ch_WZeroFlag,Ch_WUZeroFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  637. R_SUBFLAGSIGN:
  638. Result:=([Ch_RSignFlag,Ch_RWSignFlag,Ch_W0SignFlag,Ch_W1SignFlag,Ch_WSignFlag,Ch_WUSignFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  639. R_SUBFLAGOVERFLOW:
  640. Result:=([Ch_ROverflowFlag,Ch_RWOverflowFlag,Ch_W0OverflowFlag,Ch_W1OverflowFlag,Ch_WOverflowFlag,Ch_WUOverflowFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  641. R_SUBFLAGINTERRUPT:
  642. Result:=([Ch_W0IntFlag,Ch_W1IntFlag,Ch_WFlags]*insprop[taicpu(p1).opcode].Ch)<>[];
  643. R_SUBFLAGDIRECTION:
  644. Result:=([Ch_RDirFlag,Ch_W0DirFlag,Ch_W1DirFlag,Ch_WFlags]*insprop[taicpu(p1).opcode].Ch)<>[];
  645. else
  646. ;
  647. end;
  648. if result then
  649. exit;
  650. end
  651. else if (getregtype(reg)=R_FPUREGISTER) and (Ch_FPU in insprop[taicpu(p1).opcode].Ch) then
  652. exit(true);
  653. Result:=inherited RegInInstruction(Reg, p1);
  654. end;
  655. function TX86AsmOptimizer.RegModifiedByInstruction(Reg: TRegister; p1: tai): boolean;
  656. begin
  657. Result := False;
  658. if p1.typ <> ait_instruction then
  659. exit;
  660. with insprop[taicpu(p1).opcode] do
  661. if SuperRegistersEqual(reg,NR_DEFAULTFLAGS) then
  662. begin
  663. case getsubreg(reg) of
  664. R_SUBW,R_SUBD,R_SUBQ:
  665. Result :=
  666. [Ch_WCarryFlag,Ch_WParityFlag,Ch_WAuxiliaryFlag,Ch_WZeroFlag,Ch_WSignFlag,Ch_WOverflowFlag,
  667. Ch_RWCarryFlag,Ch_RWParityFlag,Ch_RWAuxiliaryFlag,Ch_RWZeroFlag,Ch_RWSignFlag,Ch_RWOverflowFlag,
  668. Ch_W0DirFlag,Ch_W1DirFlag,Ch_W0IntFlag,Ch_W1IntFlag,Ch_WFlags,Ch_RWFlags]*Ch<>[];
  669. R_SUBFLAGCARRY:
  670. Result:=[Ch_WCarryFlag,Ch_RWCarryFlag,Ch_WFlags,Ch_RWFlags]*Ch<>[];
  671. R_SUBFLAGPARITY:
  672. Result:=[Ch_WParityFlag,Ch_RWParityFlag,Ch_WFlags,Ch_RWFlags]*Ch<>[];
  673. R_SUBFLAGAUXILIARY:
  674. Result:=[Ch_WAuxiliaryFlag,Ch_RWAuxiliaryFlag,Ch_WFlags,Ch_RWFlags]*Ch<>[];
  675. R_SUBFLAGZERO:
  676. Result:=[Ch_WZeroFlag,Ch_RWZeroFlag,Ch_WFlags,Ch_RWFlags]*Ch<>[];
  677. R_SUBFLAGSIGN:
  678. Result:=[Ch_WSignFlag,Ch_RWSignFlag,Ch_WFlags,Ch_RWFlags]*Ch<>[];
  679. R_SUBFLAGOVERFLOW:
  680. Result:=[Ch_WOverflowFlag,Ch_RWOverflowFlag,Ch_WFlags,Ch_RWFlags]*Ch<>[];
  681. R_SUBFLAGINTERRUPT:
  682. Result:=[Ch_W0IntFlag,Ch_W1IntFlag,Ch_WFlags,Ch_RWFlags]*Ch<>[];
  683. R_SUBFLAGDIRECTION:
  684. Result:=[Ch_W0DirFlag,Ch_W1DirFlag,Ch_WFlags,Ch_RWFlags]*Ch<>[];
  685. else
  686. internalerror(2017042602);
  687. end;
  688. exit;
  689. end;
  690. case taicpu(p1).opcode of
  691. A_CALL:
  692. { We could potentially set Result to False if the register in
  693. question is non-volatile for the subroutine's calling convention,
  694. but this would require detecting the calling convention in use and
  695. also assuming that the routine doesn't contain malformed assembly
  696. language, for example... so it could only be done under -O4 as it
  697. would be considered a side-effect. [Kit] }
  698. Result := True;
  699. A_MOVSD:
  700. { special handling for SSE MOVSD }
  701. if (taicpu(p1).ops>0) then
  702. begin
  703. if taicpu(p1).ops<>2 then
  704. internalerror(2017042703);
  705. Result := (taicpu(p1).oper[1]^.typ=top_reg) and RegInOp(reg,taicpu(p1).oper[1]^);
  706. end;
  707. { VMOVSS and VMOVSD has two and three operand flavours, this cannot modelled by x86ins.dat
  708. so fix it here (FK)
  709. }
  710. A_VMOVSS,
  711. A_VMOVSD:
  712. begin
  713. Result := (taicpu(p1).ops=3) and (taicpu(p1).oper[2]^.typ=top_reg) and RegInOp(reg,taicpu(p1).oper[2]^);
  714. exit;
  715. end;
  716. A_IMUL:
  717. Result := (taicpu(p1).oper[taicpu(p1).ops-1]^.typ=top_reg) and RegInOp(reg,taicpu(p1).oper[taicpu(p1).ops-1]^);
  718. else
  719. ;
  720. end;
  721. if Result then
  722. exit;
  723. with insprop[taicpu(p1).opcode] do
  724. begin
  725. if getregtype(reg)=R_INTREGISTER then
  726. begin
  727. case getsupreg(reg) of
  728. RS_EAX:
  729. if [Ch_WEAX,Ch_RWEAX,Ch_MEAX]*Ch<>[] then
  730. begin
  731. Result := True;
  732. exit
  733. end;
  734. RS_ECX:
  735. if [Ch_WECX,Ch_RWECX,Ch_MECX]*Ch<>[] then
  736. begin
  737. Result := True;
  738. exit
  739. end;
  740. RS_EDX:
  741. if [Ch_WEDX,Ch_RWEDX,Ch_MEDX]*Ch<>[] then
  742. begin
  743. Result := True;
  744. exit
  745. end;
  746. RS_EBX:
  747. if [Ch_WEBX,Ch_RWEBX,Ch_MEBX]*Ch<>[] then
  748. begin
  749. Result := True;
  750. exit
  751. end;
  752. RS_ESP:
  753. if [Ch_WESP,Ch_RWESP,Ch_MESP]*Ch<>[] then
  754. begin
  755. Result := True;
  756. exit
  757. end;
  758. RS_EBP:
  759. if [Ch_WEBP,Ch_RWEBP,Ch_MEBP]*Ch<>[] then
  760. begin
  761. Result := True;
  762. exit
  763. end;
  764. RS_ESI:
  765. if [Ch_WESI,Ch_RWESI,Ch_MESI]*Ch<>[] then
  766. begin
  767. Result := True;
  768. exit
  769. end;
  770. RS_EDI:
  771. if [Ch_WEDI,Ch_RWEDI,Ch_MEDI]*Ch<>[] then
  772. begin
  773. Result := True;
  774. exit
  775. end;
  776. end;
  777. end;
  778. if ([CH_RWOP1,CH_WOP1,CH_MOP1]*Ch<>[]) and reginop(reg,taicpu(p1).oper[0]^) then
  779. begin
  780. Result := true;
  781. exit
  782. end;
  783. if ([Ch_RWOP2,Ch_WOP2,Ch_MOP2]*Ch<>[]) and reginop(reg,taicpu(p1).oper[1]^) then
  784. begin
  785. Result := true;
  786. exit
  787. end;
  788. if ([Ch_RWOP3,Ch_WOP3,Ch_MOP3]*Ch<>[]) and reginop(reg,taicpu(p1).oper[2]^) then
  789. begin
  790. Result := true;
  791. exit
  792. end;
  793. if ([Ch_RWOP4,Ch_WOP4,Ch_MOP4]*Ch<>[]) and reginop(reg,taicpu(p1).oper[3]^) then
  794. begin
  795. Result := true;
  796. exit
  797. end;
  798. end;
  799. end;
  800. {$ifdef DEBUG_AOPTCPU}
  801. procedure TX86AsmOptimizer.DebugMsg(const s: string;p : tai);
  802. begin
  803. asml.insertbefore(tai_comment.Create(strpnew(s)), p);
  804. end;
  805. function debug_tostr(i: tcgint): string; inline;
  806. begin
  807. Result := tostr(i);
  808. end;
  809. function debug_regname(r: TRegister): string; inline;
  810. begin
  811. Result := '%' + std_regname(r);
  812. end;
  813. { Debug output function - creates a string representation of an operator }
  814. function debug_operstr(oper: TOper): string;
  815. begin
  816. case oper.typ of
  817. top_const:
  818. Result := '$' + debug_tostr(oper.val);
  819. top_reg:
  820. Result := debug_regname(oper.reg);
  821. top_ref:
  822. begin
  823. if oper.ref^.offset <> 0 then
  824. Result := debug_tostr(oper.ref^.offset) + '('
  825. else
  826. Result := '(';
  827. if (oper.ref^.base <> NR_INVALID) and (oper.ref^.base <> NR_NO) then
  828. begin
  829. Result := Result + debug_regname(oper.ref^.base);
  830. if (oper.ref^.index <> NR_INVALID) and (oper.ref^.index <> NR_NO) then
  831. Result := Result + ',' + debug_regname(oper.ref^.index);
  832. end
  833. else
  834. if (oper.ref^.index <> NR_INVALID) and (oper.ref^.index <> NR_NO) then
  835. Result := Result + debug_regname(oper.ref^.index);
  836. if (oper.ref^.scalefactor > 1) then
  837. Result := Result + ',' + debug_tostr(oper.ref^.scalefactor) + ')'
  838. else
  839. Result := Result + ')';
  840. end;
  841. else
  842. Result := '[UNKNOWN]';
  843. end;
  844. end;
  845. function debug_op2str(opcode: tasmop): string; inline;
  846. begin
  847. Result := std_op2str[opcode];
  848. end;
  849. function debug_opsize2str(opsize: topsize): string; inline;
  850. begin
  851. Result := gas_opsize2str[opsize];
  852. end;
  853. {$else DEBUG_AOPTCPU}
  854. procedure TX86AsmOptimizer.DebugMsg(const s: string;p : tai);inline;
  855. begin
  856. end;
  857. function debug_tostr(i: tcgint): string; inline;
  858. begin
  859. Result := '';
  860. end;
  861. function debug_regname(r: TRegister): string; inline;
  862. begin
  863. Result := '';
  864. end;
  865. function debug_operstr(oper: TOper): string; inline;
  866. begin
  867. Result := '';
  868. end;
  869. function debug_op2str(opcode: tasmop): string; inline;
  870. begin
  871. Result := '';
  872. end;
  873. function debug_opsize2str(opsize: topsize): string; inline;
  874. begin
  875. Result := '';
  876. end;
  877. {$endif DEBUG_AOPTCPU}
  878. class function TX86AsmOptimizer.IsMOVZXAcceptable: Boolean; inline;
  879. begin
  880. {$ifdef x86_64}
  881. { Always fine on x86-64 }
  882. Result := True;
  883. {$else x86_64}
  884. Result :=
  885. {$ifdef i8086}
  886. (current_settings.cputype >= cpu_386) and
  887. {$endif i8086}
  888. (
  889. { Always accept if optimising for size }
  890. (cs_opt_size in current_settings.optimizerswitches) or
  891. { From the Pentium II onwards, MOVZX only takes 1 cycle. [Kit] }
  892. (current_settings.optimizecputype >= cpu_Pentium2)
  893. );
  894. {$endif x86_64}
  895. end;
  896. function TX86AsmOptimizer.Reg1WriteOverwritesReg2Entirely(reg1, reg2: tregister): boolean;
  897. begin
  898. if not SuperRegistersEqual(reg1,reg2) then
  899. exit(false);
  900. if getregtype(reg1)<>R_INTREGISTER then
  901. exit(true); {because SuperRegisterEqual is true}
  902. case getsubreg(reg1) of
  903. { A write to R_SUBL doesn't change R_SUBH and if reg2 is R_SUBW or
  904. higher, it preserves the high bits, so the new value depends on
  905. reg2's previous value. In other words, it is equivalent to doing:
  906. reg2 := (reg2 and $ffffff00) or byte(reg1); }
  907. R_SUBL:
  908. exit(getsubreg(reg2)=R_SUBL);
  909. { A write to R_SUBH doesn't change R_SUBL and if reg2 is R_SUBW or
  910. higher, it actually does a:
  911. reg2 := (reg2 and $ffff00ff) or (reg1 and $ff00); }
  912. R_SUBH:
  913. exit(getsubreg(reg2)=R_SUBH);
  914. { If reg2 is R_SUBD or larger, a write to R_SUBW preserves the high 16
  915. bits of reg2:
  916. reg2 := (reg2 and $ffff0000) or word(reg1); }
  917. R_SUBW:
  918. exit(getsubreg(reg2) in [R_SUBL,R_SUBH,R_SUBW]);
  919. { a write to R_SUBD always overwrites every other subregister,
  920. because it clears the high 32 bits of R_SUBQ on x86_64 }
  921. R_SUBD,
  922. R_SUBQ:
  923. exit(true);
  924. else
  925. internalerror(2017042801);
  926. end;
  927. end;
  928. function TX86AsmOptimizer.Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
  929. begin
  930. if not SuperRegistersEqual(reg1,reg2) then
  931. exit(false);
  932. if getregtype(reg1)<>R_INTREGISTER then
  933. exit(true); {because SuperRegisterEqual is true}
  934. case getsubreg(reg1) of
  935. R_SUBL:
  936. exit(getsubreg(reg2)<>R_SUBH);
  937. R_SUBH:
  938. exit(getsubreg(reg2)<>R_SUBL);
  939. R_SUBW,
  940. R_SUBD,
  941. R_SUBQ:
  942. exit(true);
  943. else
  944. internalerror(2017042802);
  945. end;
  946. end;
  947. function TX86AsmOptimizer.PrePeepholeOptSxx(var p : tai) : boolean;
  948. var
  949. hp1 : tai;
  950. l : TCGInt;
  951. begin
  952. result:=false;
  953. { changes the code sequence
  954. shr/sar const1, x
  955. shl const2, x
  956. to
  957. either "sar/and", "shl/and" or just "and" depending on const1 and const2 }
  958. if GetNextInstruction(p, hp1) and
  959. MatchInstruction(hp1,A_SHL,[]) and
  960. (taicpu(p).oper[0]^.typ = top_const) and
  961. (taicpu(hp1).oper[0]^.typ = top_const) and
  962. (taicpu(hp1).opsize = taicpu(p).opsize) and
  963. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[1]^.typ) and
  964. OpsEqual(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^) then
  965. begin
  966. if (taicpu(p).oper[0]^.val > taicpu(hp1).oper[0]^.val) and
  967. not(cs_opt_size in current_settings.optimizerswitches) then
  968. begin
  969. { shr/sar const1, %reg
  970. shl const2, %reg
  971. with const1 > const2 }
  972. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  973. taicpu(hp1).opcode := A_AND;
  974. l := (1 shl (taicpu(hp1).oper[0]^.val)) - 1;
  975. case taicpu(p).opsize Of
  976. S_B: taicpu(hp1).loadConst(0,l Xor $ff);
  977. S_W: taicpu(hp1).loadConst(0,l Xor $ffff);
  978. S_L: taicpu(hp1).loadConst(0,l Xor tcgint($ffffffff));
  979. S_Q: taicpu(hp1).loadConst(0,l Xor tcgint($ffffffffffffffff));
  980. else
  981. Internalerror(2017050703)
  982. end;
  983. end
  984. else if (taicpu(p).oper[0]^.val<taicpu(hp1).oper[0]^.val) and
  985. not(cs_opt_size in current_settings.optimizerswitches) then
  986. begin
  987. { shr/sar const1, %reg
  988. shl const2, %reg
  989. with const1 < const2 }
  990. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val-taicpu(p).oper[0]^.val);
  991. taicpu(p).opcode := A_AND;
  992. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  993. case taicpu(p).opsize Of
  994. S_B: taicpu(p).loadConst(0,l Xor $ff);
  995. S_W: taicpu(p).loadConst(0,l Xor $ffff);
  996. S_L: taicpu(p).loadConst(0,l Xor tcgint($ffffffff));
  997. S_Q: taicpu(p).loadConst(0,l Xor tcgint($ffffffffffffffff));
  998. else
  999. Internalerror(2017050702)
  1000. end;
  1001. end
  1002. else if (taicpu(p).oper[0]^.val = taicpu(hp1).oper[0]^.val) then
  1003. begin
  1004. { shr/sar const1, %reg
  1005. shl const2, %reg
  1006. with const1 = const2 }
  1007. taicpu(p).opcode := A_AND;
  1008. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  1009. case taicpu(p).opsize Of
  1010. S_B: taicpu(p).loadConst(0,l Xor $ff);
  1011. S_W: taicpu(p).loadConst(0,l Xor $ffff);
  1012. S_L: taicpu(p).loadConst(0,l Xor tcgint($ffffffff));
  1013. S_Q: taicpu(p).loadConst(0,l Xor tcgint($ffffffffffffffff));
  1014. else
  1015. Internalerror(2017050701)
  1016. end;
  1017. RemoveInstruction(hp1);
  1018. end;
  1019. end;
  1020. end;
  1021. function TX86AsmOptimizer.PrePeepholeOptIMUL(var p : tai) : boolean;
  1022. var
  1023. opsize : topsize;
  1024. hp1 : tai;
  1025. tmpref : treference;
  1026. ShiftValue : Cardinal;
  1027. BaseValue : TCGInt;
  1028. begin
  1029. result:=false;
  1030. opsize:=taicpu(p).opsize;
  1031. { changes certain "imul const, %reg"'s to lea sequences }
  1032. if (MatchOpType(taicpu(p),top_const,top_reg) or
  1033. MatchOpType(taicpu(p),top_const,top_reg,top_reg)) and
  1034. (opsize in [S_L{$ifdef x86_64},S_Q{$endif x86_64}]) then
  1035. if (taicpu(p).oper[0]^.val = 1) then
  1036. if (taicpu(p).ops = 2) then
  1037. { remove "imul $1, reg" }
  1038. begin
  1039. DebugMsg(SPeepholeOptimization + 'Imul2Nop done',p);
  1040. Result := RemoveCurrentP(p);
  1041. end
  1042. else
  1043. { change "imul $1, reg1, reg2" to "mov reg1, reg2" }
  1044. begin
  1045. hp1 := taicpu.Op_Reg_Reg(A_MOV, opsize, taicpu(p).oper[1]^.reg,taicpu(p).oper[2]^.reg);
  1046. InsertLLItem(p.previous, p.next, hp1);
  1047. DebugMsg(SPeepholeOptimization + 'Imul2Mov done',p);
  1048. p.free;
  1049. p := hp1;
  1050. end
  1051. else if ((taicpu(p).ops <= 2) or
  1052. (taicpu(p).oper[2]^.typ = Top_Reg)) and
  1053. not(cs_opt_size in current_settings.optimizerswitches) and
  1054. (not(GetNextInstruction(p, hp1)) or
  1055. not((tai(hp1).typ = ait_instruction) and
  1056. ((taicpu(hp1).opcode=A_Jcc) and
  1057. (taicpu(hp1).condition in [C_O,C_NO])))) then
  1058. begin
  1059. {
  1060. imul X, reg1, reg2 to
  1061. lea (reg1,reg1,Y), reg2
  1062. shl ZZ,reg2
  1063. imul XX, reg1 to
  1064. lea (reg1,reg1,YY), reg1
  1065. shl ZZ,reg2
  1066. This optimziation makes sense for pretty much every x86, except the VIA Nano3000: it has IMUL latency 2, lea/shl pair as well,
  1067. it does not exist as a separate optimization target in FPC though.
  1068. This optimziation can be applied as long as only two bits are set in the constant and those two bits are separated by
  1069. at most two zeros
  1070. }
  1071. reference_reset(tmpref,1,[]);
  1072. if (PopCnt(QWord(taicpu(p).oper[0]^.val))=2) and (BsrQWord(taicpu(p).oper[0]^.val)-BsfQWord(taicpu(p).oper[0]^.val)<=3) then
  1073. begin
  1074. ShiftValue:=BsfQWord(taicpu(p).oper[0]^.val);
  1075. BaseValue:=taicpu(p).oper[0]^.val shr ShiftValue;
  1076. TmpRef.base := taicpu(p).oper[1]^.reg;
  1077. TmpRef.index := taicpu(p).oper[1]^.reg;
  1078. if not(BaseValue in [3,5,9]) then
  1079. Internalerror(2018110101);
  1080. TmpRef.ScaleFactor := BaseValue-1;
  1081. if (taicpu(p).ops = 2) then
  1082. hp1 := taicpu.op_ref_reg(A_LEA, opsize, TmpRef, taicpu(p).oper[1]^.reg)
  1083. else
  1084. hp1 := taicpu.op_ref_reg(A_LEA, opsize, TmpRef, taicpu(p).oper[2]^.reg);
  1085. AsmL.InsertAfter(hp1,p);
  1086. DebugMsg(SPeepholeOptimization + 'Imul2LeaShl done',p);
  1087. taicpu(hp1).fileinfo:=taicpu(p).fileinfo;
  1088. RemoveCurrentP(p, hp1);
  1089. if ShiftValue>0 then
  1090. AsmL.InsertAfter(taicpu.op_const_reg(A_SHL, opsize, ShiftValue, taicpu(hp1).oper[1]^.reg),hp1);
  1091. end;
  1092. end;
  1093. end;
  1094. function TX86AsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
  1095. var
  1096. p: taicpu;
  1097. begin
  1098. if not assigned(hp) or
  1099. (hp.typ <> ait_instruction) then
  1100. begin
  1101. Result := false;
  1102. exit;
  1103. end;
  1104. p := taicpu(hp);
  1105. if SuperRegistersEqual(reg,NR_DEFAULTFLAGS) then
  1106. with insprop[p.opcode] do
  1107. begin
  1108. case getsubreg(reg) of
  1109. R_SUBW,R_SUBD,R_SUBQ:
  1110. Result:=
  1111. RegLoadedWithNewValue(NR_CARRYFLAG,hp) and
  1112. RegLoadedWithNewValue(NR_PARITYFLAG,hp) and
  1113. RegLoadedWithNewValue(NR_AUXILIARYFLAG,hp) and
  1114. RegLoadedWithNewValue(NR_ZEROFLAG,hp) and
  1115. RegLoadedWithNewValue(NR_SIGNFLAG,hp) and
  1116. RegLoadedWithNewValue(NR_OVERFLOWFLAG,hp);
  1117. R_SUBFLAGCARRY:
  1118. Result:=[Ch_W0CarryFlag,Ch_W1CarryFlag,Ch_WCarryFlag,Ch_WUCarryFlag,Ch_WFlags]*Ch<>[];
  1119. R_SUBFLAGPARITY:
  1120. Result:=[Ch_W0ParityFlag,Ch_W1ParityFlag,Ch_WParityFlag,Ch_WUParityFlag,Ch_WFlags]*Ch<>[];
  1121. R_SUBFLAGAUXILIARY:
  1122. Result:=[Ch_W0AuxiliaryFlag,Ch_W1AuxiliaryFlag,Ch_WAuxiliaryFlag,Ch_WUAuxiliaryFlag,Ch_WFlags]*Ch<>[];
  1123. R_SUBFLAGZERO:
  1124. Result:=[Ch_W0ZeroFlag,Ch_W1ZeroFlag,Ch_WZeroFlag,Ch_WUZeroFlag,Ch_WFlags]*Ch<>[];
  1125. R_SUBFLAGSIGN:
  1126. Result:=[Ch_W0SignFlag,Ch_W1SignFlag,Ch_WSignFlag,Ch_WUSignFlag,Ch_WFlags]*Ch<>[];
  1127. R_SUBFLAGOVERFLOW:
  1128. Result:=[Ch_W0OverflowFlag,Ch_W1OverflowFlag,Ch_WOverflowFlag,Ch_WUOverflowFlag,Ch_WFlags]*Ch<>[];
  1129. R_SUBFLAGINTERRUPT:
  1130. Result:=[Ch_W0IntFlag,Ch_W1IntFlag,Ch_WFlags]*Ch<>[];
  1131. R_SUBFLAGDIRECTION:
  1132. Result:=[Ch_W0DirFlag,Ch_W1DirFlag,Ch_WFlags]*Ch<>[];
  1133. else
  1134. begin
  1135. writeln(getsubreg(reg));
  1136. internalerror(2017050501);
  1137. end;
  1138. end;
  1139. exit;
  1140. end;
  1141. Result :=
  1142. (((p.opcode = A_MOV) or
  1143. (p.opcode = A_MOVZX) or
  1144. (p.opcode = A_MOVSX) or
  1145. (p.opcode = A_LEA) or
  1146. (p.opcode = A_VMOVSS) or
  1147. (p.opcode = A_VMOVSD) or
  1148. (p.opcode = A_VMOVAPD) or
  1149. (p.opcode = A_VMOVAPS) or
  1150. (p.opcode = A_VMOVQ) or
  1151. (p.opcode = A_MOVSS) or
  1152. (p.opcode = A_MOVSD) or
  1153. (p.opcode = A_MOVQ) or
  1154. (p.opcode = A_MOVAPD) or
  1155. (p.opcode = A_MOVAPS) or
  1156. {$ifndef x86_64}
  1157. (p.opcode = A_LDS) or
  1158. (p.opcode = A_LES) or
  1159. {$endif not x86_64}
  1160. (p.opcode = A_LFS) or
  1161. (p.opcode = A_LGS) or
  1162. (p.opcode = A_LSS)) and
  1163. (p.ops=2) and { A_MOVSD can have zero operands, so this check is needed }
  1164. (p.oper[1]^.typ = top_reg) and
  1165. (Reg1WriteOverwritesReg2Entirely(p.oper[1]^.reg,reg)) and
  1166. ((p.oper[0]^.typ = top_const) or
  1167. ((p.oper[0]^.typ = top_reg) and
  1168. not(Reg1ReadDependsOnReg2(p.oper[0]^.reg,reg))) or
  1169. ((p.oper[0]^.typ = top_ref) and
  1170. not RegInRef(reg,p.oper[0]^.ref^)))) or
  1171. ((p.opcode = A_POP) and
  1172. (Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg))) or
  1173. ((p.opcode = A_IMUL) and
  1174. (p.ops=3) and
  1175. (Reg1WriteOverwritesReg2Entirely(p.oper[2]^.reg,reg)) and
  1176. (((p.oper[1]^.typ=top_reg) and not(Reg1ReadDependsOnReg2(p.oper[1]^.reg,reg))) or
  1177. ((p.oper[1]^.typ=top_ref) and not(RegInRef(reg,p.oper[1]^.ref^))))) or
  1178. ((((p.opcode = A_IMUL) or
  1179. (p.opcode = A_MUL)) and
  1180. (p.ops=1)) and
  1181. (((p.oper[0]^.typ=top_reg) and not(Reg1ReadDependsOnReg2(p.oper[0]^.reg,reg))) or
  1182. ((p.oper[0]^.typ=top_ref) and not(RegInRef(reg,p.oper[0]^.ref^)))) and
  1183. (((p.opsize=S_B) and Reg1WriteOverwritesReg2Entirely(NR_AX,reg) and not(Reg1ReadDependsOnReg2(NR_AL,reg))) or
  1184. ((p.opsize=S_W) and Reg1WriteOverwritesReg2Entirely(NR_DX,reg)) or
  1185. ((p.opsize=S_L) and Reg1WriteOverwritesReg2Entirely(NR_EDX,reg))
  1186. {$ifdef x86_64}
  1187. or ((p.opsize=S_Q) and Reg1WriteOverwritesReg2Entirely(NR_RDX,reg))
  1188. {$endif x86_64}
  1189. )) or
  1190. ((p.opcode = A_CWD) and Reg1WriteOverwritesReg2Entirely(NR_DX,reg)) or
  1191. ((p.opcode = A_CDQ) and Reg1WriteOverwritesReg2Entirely(NR_EDX,reg)) or
  1192. {$ifdef x86_64}
  1193. ((p.opcode = A_CQO) and Reg1WriteOverwritesReg2Entirely(NR_RDX,reg)) or
  1194. {$endif x86_64}
  1195. ((p.opcode = A_CBW) and Reg1WriteOverwritesReg2Entirely(NR_AX,reg) and not(Reg1ReadDependsOnReg2(NR_AL,reg))) or
  1196. {$ifndef x86_64}
  1197. ((p.opcode = A_LDS) and (reg=NR_DS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  1198. ((p.opcode = A_LES) and (reg=NR_ES) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  1199. {$endif not x86_64}
  1200. ((p.opcode = A_LFS) and (reg=NR_FS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  1201. ((p.opcode = A_LGS) and (reg=NR_GS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  1202. ((p.opcode = A_LSS) and (reg=NR_SS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  1203. {$ifndef x86_64}
  1204. ((p.opcode = A_AAM) and Reg1WriteOverwritesReg2Entirely(NR_AH,reg)) or
  1205. {$endif not x86_64}
  1206. ((p.opcode = A_LAHF) and Reg1WriteOverwritesReg2Entirely(NR_AH,reg)) or
  1207. ((p.opcode = A_LODSB) and Reg1WriteOverwritesReg2Entirely(NR_AL,reg)) or
  1208. ((p.opcode = A_LODSW) and Reg1WriteOverwritesReg2Entirely(NR_AX,reg)) or
  1209. ((p.opcode = A_LODSD) and Reg1WriteOverwritesReg2Entirely(NR_EAX,reg)) or
  1210. {$ifdef x86_64}
  1211. ((p.opcode = A_LODSQ) and Reg1WriteOverwritesReg2Entirely(NR_RAX,reg)) or
  1212. {$endif x86_64}
  1213. ((p.opcode = A_SETcc) and (p.oper[0]^.typ=top_reg) and Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg)) or
  1214. (((p.opcode = A_FSTSW) or
  1215. (p.opcode = A_FNSTSW)) and
  1216. (p.oper[0]^.typ=top_reg) and
  1217. Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg)) or
  1218. (((p.opcode = A_XOR) or (p.opcode = A_SUB) or (p.opcode = A_SBB)) and
  1219. (p.oper[0]^.typ=top_reg) and (p.oper[1]^.typ=top_reg) and
  1220. (p.oper[0]^.reg=p.oper[1]^.reg) and
  1221. Reg1WriteOverwritesReg2Entirely(p.oper[1]^.reg,reg));
  1222. end;
  1223. class function TX86AsmOptimizer.IsExitCode(p : tai) : boolean;
  1224. var
  1225. hp2,hp3 : tai;
  1226. begin
  1227. { some x86-64 issue a NOP before the real exit code }
  1228. if MatchInstruction(p,A_NOP,[]) then
  1229. GetNextInstruction(p,p);
  1230. result:=assigned(p) and (p.typ=ait_instruction) and
  1231. ((taicpu(p).opcode = A_RET) or
  1232. ((taicpu(p).opcode=A_LEAVE) and
  1233. GetNextInstruction(p,hp2) and
  1234. MatchInstruction(hp2,A_RET,[S_NO])
  1235. ) or
  1236. (((taicpu(p).opcode=A_LEA) and
  1237. MatchOpType(taicpu(p),top_ref,top_reg) and
  1238. (taicpu(p).oper[0]^.ref^.base=NR_STACK_POINTER_REG) and
  1239. (taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG)
  1240. ) and
  1241. GetNextInstruction(p,hp2) and
  1242. MatchInstruction(hp2,A_RET,[S_NO])
  1243. ) or
  1244. ((((taicpu(p).opcode=A_MOV) and
  1245. MatchOpType(taicpu(p),top_reg,top_reg) and
  1246. (taicpu(p).oper[0]^.reg=current_procinfo.framepointer) and
  1247. (taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG)) or
  1248. ((taicpu(p).opcode=A_LEA) and
  1249. MatchOpType(taicpu(p),top_ref,top_reg) and
  1250. (taicpu(p).oper[0]^.ref^.base=current_procinfo.framepointer) and
  1251. (taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG)
  1252. )
  1253. ) and
  1254. GetNextInstruction(p,hp2) and
  1255. MatchInstruction(hp2,A_POP,[reg2opsize(current_procinfo.framepointer)]) and
  1256. MatchOpType(taicpu(hp2),top_reg) and
  1257. (taicpu(hp2).oper[0]^.reg=current_procinfo.framepointer) and
  1258. GetNextInstruction(hp2,hp3) and
  1259. MatchInstruction(hp3,A_RET,[S_NO])
  1260. )
  1261. );
  1262. end;
  1263. class function TX86AsmOptimizer.isFoldableArithOp(hp1: taicpu; reg: tregister): boolean;
  1264. begin
  1265. isFoldableArithOp := False;
  1266. case hp1.opcode of
  1267. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR:
  1268. isFoldableArithOp :=
  1269. ((taicpu(hp1).oper[0]^.typ = top_const) or
  1270. ((taicpu(hp1).oper[0]^.typ = top_reg) and
  1271. (taicpu(hp1).oper[0]^.reg <> reg))) and
  1272. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1273. (taicpu(hp1).oper[1]^.reg = reg);
  1274. A_INC,A_DEC,A_NEG,A_NOT:
  1275. isFoldableArithOp :=
  1276. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1277. (taicpu(hp1).oper[0]^.reg = reg);
  1278. else
  1279. ;
  1280. end;
  1281. end;
  1282. procedure TX86AsmOptimizer.RemoveLastDeallocForFuncRes(p: tai);
  1283. procedure DoRemoveLastDeallocForFuncRes( supreg: tsuperregister);
  1284. var
  1285. hp2: tai;
  1286. begin
  1287. hp2 := p;
  1288. repeat
  1289. hp2 := tai(hp2.previous);
  1290. if assigned(hp2) and
  1291. (hp2.typ = ait_regalloc) and
  1292. (tai_regalloc(hp2).ratype=ra_dealloc) and
  1293. (getregtype(tai_regalloc(hp2).reg) = R_INTREGISTER) and
  1294. (getsupreg(tai_regalloc(hp2).reg) = supreg) then
  1295. begin
  1296. RemoveInstruction(hp2);
  1297. break;
  1298. end;
  1299. until not(assigned(hp2)) or regInInstruction(newreg(R_INTREGISTER,supreg,R_SUBWHOLE),hp2);
  1300. end;
  1301. begin
  1302. case current_procinfo.procdef.returndef.typ of
  1303. arraydef,recorddef,pointerdef,
  1304. stringdef,enumdef,procdef,objectdef,errordef,
  1305. filedef,setdef,procvardef,
  1306. classrefdef,forwarddef:
  1307. DoRemoveLastDeallocForFuncRes(RS_EAX);
  1308. orddef:
  1309. if current_procinfo.procdef.returndef.size <> 0 then
  1310. begin
  1311. DoRemoveLastDeallocForFuncRes(RS_EAX);
  1312. { for int64/qword }
  1313. if current_procinfo.procdef.returndef.size = 8 then
  1314. DoRemoveLastDeallocForFuncRes(RS_EDX);
  1315. end;
  1316. else
  1317. ;
  1318. end;
  1319. end;
  1320. function TX86AsmOptimizer.OptPass1_V_MOVAP(var p : tai) : boolean;
  1321. var
  1322. hp1,hp2 : tai;
  1323. begin
  1324. result:=false;
  1325. if MatchOpType(taicpu(p),top_reg,top_reg) then
  1326. begin
  1327. { vmova* reg1,reg1
  1328. =>
  1329. <nop> }
  1330. if MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^) then
  1331. begin
  1332. RemoveCurrentP(p);
  1333. result:=true;
  1334. exit;
  1335. end
  1336. else if GetNextInstruction(p,hp1) then
  1337. begin
  1338. if MatchInstruction(hp1,[taicpu(p).opcode],[S_NO]) and
  1339. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) then
  1340. begin
  1341. { vmova* reg1,reg2
  1342. vmova* reg2,reg3
  1343. dealloc reg2
  1344. =>
  1345. vmova* reg1,reg3 }
  1346. TransferUsedRegs(TmpUsedRegs);
  1347. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1348. if MatchOpType(taicpu(hp1),top_reg,top_reg) and
  1349. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  1350. begin
  1351. DebugMsg(SPeepholeOptimization + '(V)MOVA*(V)MOVA*2(V)MOVA* 1',p);
  1352. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  1353. RemoveInstruction(hp1);
  1354. result:=true;
  1355. exit;
  1356. end
  1357. { special case:
  1358. vmova* reg1,<op>
  1359. vmova* <op>,reg1
  1360. =>
  1361. vmova* reg1,<op> }
  1362. else if MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^) and
  1363. ((taicpu(p).oper[0]^.typ<>top_ref) or
  1364. (not(vol_read in taicpu(p).oper[0]^.ref^.volatility))
  1365. ) then
  1366. begin
  1367. DebugMsg(SPeepholeOptimization + '(V)MOVA*(V)MOVA*2(V)MOVA* 2',p);
  1368. RemoveInstruction(hp1);
  1369. result:=true;
  1370. exit;
  1371. end
  1372. end
  1373. else if ((MatchInstruction(p,[A_MOVAPS,A_VMOVAPS],[S_NO]) and
  1374. MatchInstruction(hp1,[A_MOVSS,A_VMOVSS],[S_NO])) or
  1375. ((MatchInstruction(p,[A_MOVAPD,A_VMOVAPD],[S_NO]) and
  1376. MatchInstruction(hp1,[A_MOVSD,A_VMOVSD],[S_NO])))
  1377. ) and
  1378. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) then
  1379. begin
  1380. { vmova* reg1,reg2
  1381. vmovs* reg2,<op>
  1382. dealloc reg2
  1383. =>
  1384. vmovs* reg1,reg3 }
  1385. TransferUsedRegs(TmpUsedRegs);
  1386. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1387. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  1388. begin
  1389. DebugMsg(SPeepholeOptimization + '(V)MOVA*(V)MOVS*2(V)MOVS* 1',p);
  1390. taicpu(p).opcode:=taicpu(hp1).opcode;
  1391. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  1392. RemoveInstruction(hp1);
  1393. result:=true;
  1394. exit;
  1395. end
  1396. end;
  1397. end;
  1398. if GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[1]^.reg) then
  1399. begin
  1400. if MatchInstruction(hp1,[A_VFMADDPD,
  1401. A_VFMADD132PD,
  1402. A_VFMADD132PS,
  1403. A_VFMADD132SD,
  1404. A_VFMADD132SS,
  1405. A_VFMADD213PD,
  1406. A_VFMADD213PS,
  1407. A_VFMADD213SD,
  1408. A_VFMADD213SS,
  1409. A_VFMADD231PD,
  1410. A_VFMADD231PS,
  1411. A_VFMADD231SD,
  1412. A_VFMADD231SS,
  1413. A_VFMADDSUB132PD,
  1414. A_VFMADDSUB132PS,
  1415. A_VFMADDSUB213PD,
  1416. A_VFMADDSUB213PS,
  1417. A_VFMADDSUB231PD,
  1418. A_VFMADDSUB231PS,
  1419. A_VFMSUB132PD,
  1420. A_VFMSUB132PS,
  1421. A_VFMSUB132SD,
  1422. A_VFMSUB132SS,
  1423. A_VFMSUB213PD,
  1424. A_VFMSUB213PS,
  1425. A_VFMSUB213SD,
  1426. A_VFMSUB213SS,
  1427. A_VFMSUB231PD,
  1428. A_VFMSUB231PS,
  1429. A_VFMSUB231SD,
  1430. A_VFMSUB231SS,
  1431. A_VFMSUBADD132PD,
  1432. A_VFMSUBADD132PS,
  1433. A_VFMSUBADD213PD,
  1434. A_VFMSUBADD213PS,
  1435. A_VFMSUBADD231PD,
  1436. A_VFMSUBADD231PS,
  1437. A_VFNMADD132PD,
  1438. A_VFNMADD132PS,
  1439. A_VFNMADD132SD,
  1440. A_VFNMADD132SS,
  1441. A_VFNMADD213PD,
  1442. A_VFNMADD213PS,
  1443. A_VFNMADD213SD,
  1444. A_VFNMADD213SS,
  1445. A_VFNMADD231PD,
  1446. A_VFNMADD231PS,
  1447. A_VFNMADD231SD,
  1448. A_VFNMADD231SS,
  1449. A_VFNMSUB132PD,
  1450. A_VFNMSUB132PS,
  1451. A_VFNMSUB132SD,
  1452. A_VFNMSUB132SS,
  1453. A_VFNMSUB213PD,
  1454. A_VFNMSUB213PS,
  1455. A_VFNMSUB213SD,
  1456. A_VFNMSUB213SS,
  1457. A_VFNMSUB231PD,
  1458. A_VFNMSUB231PS,
  1459. A_VFNMSUB231SD,
  1460. A_VFNMSUB231SS],[S_NO]) and
  1461. { we mix single and double opperations here because we assume that the compiler
  1462. generates vmovapd only after double operations and vmovaps only after single operations }
  1463. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[2]^) and
  1464. GetNextInstruction(hp1,hp2) and
  1465. MatchInstruction(hp2,[A_VMOVAPD,A_VMOVAPS,A_MOVAPD,A_MOVAPS],[S_NO]) and
  1466. MatchOperand(taicpu(p).oper[0]^,taicpu(hp2).oper[1]^) then
  1467. begin
  1468. TransferUsedRegs(TmpUsedRegs);
  1469. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1470. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1471. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs)) then
  1472. begin
  1473. taicpu(hp1).loadoper(2,taicpu(p).oper[0]^);
  1474. RemoveCurrentP(p, hp1); // <-- Is this actually safe? hp1 is not necessarily the next instruction. [Kit]
  1475. RemoveInstruction(hp2);
  1476. end;
  1477. end
  1478. else if (hp1.typ = ait_instruction) and
  1479. GetNextInstruction(hp1, hp2) and
  1480. MatchInstruction(hp2,taicpu(p).opcode,[]) and
  1481. OpsEqual(taicpu(hp2).oper[1]^, taicpu(p).oper[0]^) and
  1482. MatchOpType(taicpu(hp2),top_reg,top_reg) and
  1483. MatchOperand(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) and
  1484. (((taicpu(p).opcode=A_MOVAPS) and
  1485. ((taicpu(hp1).opcode=A_ADDSS) or (taicpu(hp1).opcode=A_SUBSS) or
  1486. (taicpu(hp1).opcode=A_MULSS) or (taicpu(hp1).opcode=A_DIVSS))) or
  1487. ((taicpu(p).opcode=A_MOVAPD) and
  1488. ((taicpu(hp1).opcode=A_ADDSD) or (taicpu(hp1).opcode=A_SUBSD) or
  1489. (taicpu(hp1).opcode=A_MULSD) or (taicpu(hp1).opcode=A_DIVSD)))
  1490. ) then
  1491. { change
  1492. movapX reg,reg2
  1493. addsX/subsX/... reg3, reg2
  1494. movapX reg2,reg
  1495. to
  1496. addsX/subsX/... reg3,reg
  1497. }
  1498. begin
  1499. TransferUsedRegs(TmpUsedRegs);
  1500. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1501. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1502. If not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs)) then
  1503. begin
  1504. DebugMsg(SPeepholeOptimization + 'MovapXOpMovapX2Op ('+
  1505. debug_op2str(taicpu(p).opcode)+' '+
  1506. debug_op2str(taicpu(hp1).opcode)+' '+
  1507. debug_op2str(taicpu(hp2).opcode)+') done',p);
  1508. { we cannot eliminate the first move if
  1509. the operations uses the same register for source and dest }
  1510. if not(OpsEqual(taicpu(hp1).oper[1]^,taicpu(hp1).oper[0]^)) then
  1511. RemoveCurrentP(p, nil);
  1512. p:=hp1;
  1513. taicpu(hp1).loadoper(1, taicpu(hp2).oper[1]^);
  1514. RemoveInstruction(hp2);
  1515. result:=true;
  1516. end;
  1517. end;
  1518. end;
  1519. end;
  1520. end;
  1521. function TX86AsmOptimizer.OptPass1VOP(var p : tai) : boolean;
  1522. var
  1523. hp1 : tai;
  1524. begin
  1525. result:=false;
  1526. { replace
  1527. V<Op>X %mreg1,%mreg2,%mreg3
  1528. VMovX %mreg3,%mreg4
  1529. dealloc %mreg3
  1530. by
  1531. V<Op>X %mreg1,%mreg2,%mreg4
  1532. ?
  1533. }
  1534. if GetNextInstruction(p,hp1) and
  1535. { we mix single and double operations here because we assume that the compiler
  1536. generates vmovapd only after double operations and vmovaps only after single operations }
  1537. MatchInstruction(hp1,A_VMOVAPD,A_VMOVAPS,[S_NO]) and
  1538. MatchOperand(taicpu(p).oper[2]^,taicpu(hp1).oper[0]^) and
  1539. (taicpu(hp1).oper[1]^.typ=top_reg) then
  1540. begin
  1541. TransferUsedRegs(TmpUsedRegs);
  1542. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1543. if not(RegUsedAfterInstruction(taicpu(hp1).oper[0]^.reg,hp1,TmpUsedRegs)) then
  1544. begin
  1545. taicpu(p).loadoper(2,taicpu(hp1).oper[1]^);
  1546. DebugMsg(SPeepholeOptimization + 'VOpVmov2VOp done',p);
  1547. RemoveInstruction(hp1);
  1548. result:=true;
  1549. end;
  1550. end;
  1551. end;
  1552. { Replaces all references to AOldReg in a memory reference to ANewReg }
  1553. class function TX86AsmOptimizer.ReplaceRegisterInRef(var ref: TReference; const AOldReg, ANewReg: TRegister): Boolean;
  1554. begin
  1555. Result := False;
  1556. { For safety reasons, only check for exact register matches }
  1557. { Check base register }
  1558. if (ref.base = AOldReg) then
  1559. begin
  1560. ref.base := ANewReg;
  1561. Result := True;
  1562. end;
  1563. { Check index register }
  1564. if (ref.index = AOldReg) then
  1565. begin
  1566. ref.index := ANewReg;
  1567. Result := True;
  1568. end;
  1569. end;
  1570. { Replaces all references to AOldReg in an operand to ANewReg }
  1571. class function TX86AsmOptimizer.ReplaceRegisterInOper(const p: taicpu; const OperIdx: Integer; const AOldReg, ANewReg: TRegister): Boolean;
  1572. var
  1573. OldSupReg, NewSupReg: TSuperRegister;
  1574. OldSubReg, NewSubReg: TSubRegister;
  1575. OldRegType: TRegisterType;
  1576. ThisOper: POper;
  1577. begin
  1578. ThisOper := p.oper[OperIdx]; { Faster to access overall }
  1579. Result := False;
  1580. if (AOldReg = NR_NO) or (ANewReg = NR_NO) then
  1581. InternalError(2020011801);
  1582. OldSupReg := getsupreg(AOldReg);
  1583. OldSubReg := getsubreg(AOldReg);
  1584. OldRegType := getregtype(AOldReg);
  1585. NewSupReg := getsupreg(ANewReg);
  1586. NewSubReg := getsubreg(ANewReg);
  1587. if OldRegType <> getregtype(ANewReg) then
  1588. InternalError(2020011802);
  1589. if OldSubReg <> NewSubReg then
  1590. InternalError(2020011803);
  1591. case ThisOper^.typ of
  1592. top_reg:
  1593. if (
  1594. (ThisOper^.reg = AOldReg) or
  1595. (
  1596. (OldRegType = R_INTREGISTER) and
  1597. (getsupreg(ThisOper^.reg) = OldSupReg) and
  1598. (getregtype(ThisOper^.reg) = R_INTREGISTER) and
  1599. (
  1600. (getsubreg(ThisOper^.reg) <= OldSubReg)
  1601. {$ifndef x86_64}
  1602. and (
  1603. { Under i386 and i8086, ESI, EDI, EBP and ESP
  1604. don't have an 8-bit representation }
  1605. (getsubreg(ThisOper^.reg) >= R_SUBW) or
  1606. not (NewSupReg in [RS_ESI, RS_EDI, RS_EBP, RS_ESP])
  1607. )
  1608. {$endif x86_64}
  1609. )
  1610. )
  1611. ) then
  1612. begin
  1613. ThisOper^.reg := newreg(getregtype(ANewReg), NewSupReg, getsubreg(p.oper[OperIdx]^.reg));
  1614. Result := True;
  1615. end;
  1616. top_ref:
  1617. if ReplaceRegisterInRef(ThisOper^.ref^, AOldReg, ANewReg) then
  1618. Result := True;
  1619. else
  1620. ;
  1621. end;
  1622. end;
  1623. { Replaces all references to AOldReg in an instruction to ANewReg }
  1624. function TX86AsmOptimizer.ReplaceRegisterInInstruction(const p: taicpu; const AOldReg, ANewReg: TRegister): Boolean;
  1625. const
  1626. ReadFlag: array[0..3] of TInsChange = (Ch_Rop1, Ch_Rop2, Ch_Rop3, Ch_Rop4);
  1627. var
  1628. OperIdx: Integer;
  1629. begin
  1630. Result := False;
  1631. for OperIdx := 0 to p.ops - 1 do
  1632. if (ReadFlag[OperIdx] in InsProp[p.Opcode].Ch) and
  1633. { The shift and rotate instructions can only use CL }
  1634. not (
  1635. (OperIdx = 0) and
  1636. { This second condition just helps to avoid unnecessarily
  1637. calling MatchInstruction for 10 different opcodes }
  1638. (p.oper[0]^.reg = NR_CL) and
  1639. MatchInstruction(p, [A_RCL, A_RCR, A_ROL, A_ROR, A_SAL, A_SAR, A_SHL, A_SHLD, A_SHR, A_SHRD], [])
  1640. ) then
  1641. Result := ReplaceRegisterInOper(p, OperIdx, AOldReg, ANewReg) or Result;
  1642. end;
  1643. class function TX86AsmOptimizer.IsRefSafe(const ref: PReference): Boolean; inline;
  1644. begin
  1645. Result :=
  1646. (ref^.index = NR_NO) and
  1647. (
  1648. {$ifdef x86_64}
  1649. (
  1650. (ref^.base = NR_RIP) and
  1651. (ref^.refaddr in [addr_pic, addr_pic_no_got])
  1652. ) or
  1653. {$endif x86_64}
  1654. (ref^.base = NR_STACK_POINTER_REG) or
  1655. (ref^.base = current_procinfo.framepointer)
  1656. );
  1657. end;
  1658. function TX86AsmOptimizer.ConvertLEA(const p: taicpu): Boolean;
  1659. var
  1660. l: asizeint;
  1661. begin
  1662. Result := False;
  1663. { Should have been checked previously }
  1664. if p.opcode <> A_LEA then
  1665. InternalError(2020072501);
  1666. { do not mess with the stack point as adjusting it by lea is recommend, except if we optimize for size }
  1667. if (p.oper[1]^.reg=NR_STACK_POINTER_REG) and
  1668. not(cs_opt_size in current_settings.optimizerswitches) then
  1669. exit;
  1670. with p.oper[0]^.ref^ do
  1671. begin
  1672. if (base <> p.oper[1]^.reg) or
  1673. (index <> NR_NO) or
  1674. assigned(symbol) then
  1675. exit;
  1676. l:=offset;
  1677. if (l=1) and UseIncDec then
  1678. begin
  1679. p.opcode:=A_INC;
  1680. p.loadreg(0,p.oper[1]^.reg);
  1681. p.ops:=1;
  1682. DebugMsg(SPeepholeOptimization + 'Lea2Inc done',p);
  1683. end
  1684. else if (l=-1) and UseIncDec then
  1685. begin
  1686. p.opcode:=A_DEC;
  1687. p.loadreg(0,p.oper[1]^.reg);
  1688. p.ops:=1;
  1689. DebugMsg(SPeepholeOptimization + 'Lea2Dec done',p);
  1690. end
  1691. else
  1692. begin
  1693. if (l<0) and (l<>-2147483648) then
  1694. begin
  1695. p.opcode:=A_SUB;
  1696. p.loadConst(0,-l);
  1697. DebugMsg(SPeepholeOptimization + 'Lea2Sub done',p);
  1698. end
  1699. else
  1700. begin
  1701. p.opcode:=A_ADD;
  1702. p.loadConst(0,l);
  1703. DebugMsg(SPeepholeOptimization + 'Lea2Add done',p);
  1704. end;
  1705. end;
  1706. end;
  1707. Result := True;
  1708. end;
  1709. function TX86AsmOptimizer.DeepMOVOpt(const p_mov: taicpu; const hp: taicpu): Boolean;
  1710. var
  1711. CurrentReg, ReplaceReg: TRegister;
  1712. begin
  1713. Result := False;
  1714. ReplaceReg := taicpu(p_mov).oper[0]^.reg;
  1715. CurrentReg := taicpu(p_mov).oper[1]^.reg;
  1716. case hp.opcode of
  1717. A_FSTSW, A_FNSTSW,
  1718. A_IN, A_INS, A_OUT, A_OUTS,
  1719. A_CMPS, A_LODS, A_MOVS, A_SCAS, A_STOS:
  1720. { These routines have explicit operands, but they are restricted in
  1721. what they can be (e.g. IN and OUT can only read from AL, AX or
  1722. EAX. }
  1723. Exit;
  1724. A_IMUL:
  1725. begin
  1726. { The 1-operand version writes to implicit registers
  1727. The 2-operand version reads from the first operator, and reads
  1728. from and writes to the second (equivalent to Ch_ROp1, ChRWOp2).
  1729. the 3-operand version reads from a register that it doesn't write to
  1730. }
  1731. case hp.ops of
  1732. 1:
  1733. if (
  1734. (
  1735. (hp.opsize = S_B) and (getsupreg(CurrentReg) <> RS_EAX)
  1736. ) or
  1737. not (getsupreg(CurrentReg) in [RS_EAX, RS_EDX])
  1738. ) and ReplaceRegisterInOper(hp, 0, CurrentReg, ReplaceReg) then
  1739. begin
  1740. Result := True;
  1741. DebugMsg(SPeepholeOptimization + debug_regname(CurrentReg) + ' = ' + debug_regname(ReplaceReg) + '; changed to minimise pipeline stall (MovIMul2MovIMul 1)', hp);
  1742. AllocRegBetween(ReplaceReg, p_mov, hp, UsedRegs);
  1743. end;
  1744. 2:
  1745. { Only modify the first parameter }
  1746. if ReplaceRegisterInOper(hp, 0, CurrentReg, ReplaceReg) then
  1747. begin
  1748. Result := True;
  1749. DebugMsg(SPeepholeOptimization + debug_regname(CurrentReg) + ' = ' + debug_regname(ReplaceReg) + '; changed to minimise pipeline stall (MovIMul2MovIMul 2)', hp);
  1750. AllocRegBetween(ReplaceReg, p_mov, hp, UsedRegs);
  1751. end;
  1752. 3:
  1753. { Only modify the second parameter }
  1754. if ReplaceRegisterInOper(hp, 1, CurrentReg, ReplaceReg) then
  1755. begin
  1756. Result := True;
  1757. DebugMsg(SPeepholeOptimization + debug_regname(CurrentReg) + ' = ' + debug_regname(ReplaceReg) + '; changed to minimise pipeline stall (MovIMul2MovIMul 3)', hp);
  1758. AllocRegBetween(ReplaceReg, p_mov, hp, UsedRegs);
  1759. end;
  1760. else
  1761. InternalError(2020012901);
  1762. end;
  1763. end;
  1764. else
  1765. if (hp.ops > 0) and
  1766. ReplaceRegisterInInstruction(hp, CurrentReg, ReplaceReg) then
  1767. begin
  1768. Result := True;
  1769. DebugMsg(SPeepholeOptimization + debug_regname(CurrentReg) + ' = ' + debug_regname(ReplaceReg) + '; changed to minimise pipeline stall (MovXXX2MovXXX)', hp);
  1770. AllocRegBetween(ReplaceReg, p_mov, hp, UsedRegs);
  1771. end;
  1772. end;
  1773. end;
  1774. function TX86AsmOptimizer.OptPass1MOV(var p : tai) : boolean;
  1775. var
  1776. hp1, hp2, hp3: tai;
  1777. procedure convert_mov_value(signed_movop: tasmop; max_value: tcgint); inline;
  1778. begin
  1779. if taicpu(hp1).opcode = signed_movop then
  1780. begin
  1781. if taicpu(p).oper[0]^.val > max_value shr 1 then
  1782. taicpu(p).oper[0]^.val:=taicpu(p).oper[0]^.val - max_value - 1 { Convert to signed }
  1783. end
  1784. else
  1785. taicpu(p).oper[0]^.val:=taicpu(p).oper[0]^.val and max_value; { Trim to unsigned }
  1786. end;
  1787. var
  1788. GetNextInstruction_p, TempRegUsed, CrossJump: Boolean;
  1789. PreMessage, RegName1, RegName2, InputVal, MaskNum: string;
  1790. NewSize: topsize;
  1791. CurrentReg: TRegister;
  1792. begin
  1793. Result:=false;
  1794. GetNextInstruction_p:=GetNextInstruction(p, hp1);
  1795. { remove mov reg1,reg1? }
  1796. if MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^)
  1797. then
  1798. begin
  1799. DebugMsg(SPeepholeOptimization + 'Mov2Nop 1 done',p);
  1800. { take care of the register (de)allocs following p }
  1801. RemoveCurrentP(p, hp1);
  1802. Result:=true;
  1803. exit;
  1804. end;
  1805. { All the next optimisations require a next instruction }
  1806. if not GetNextInstruction_p or (hp1.typ <> ait_instruction) then
  1807. Exit;
  1808. { Look for:
  1809. mov %reg1,%reg2
  1810. ??? %reg2,r/m
  1811. Change to:
  1812. mov %reg1,%reg2
  1813. ??? %reg1,r/m
  1814. }
  1815. if MatchOpType(taicpu(p), top_reg, top_reg) then
  1816. begin
  1817. CurrentReg := taicpu(p).oper[1]^.reg;
  1818. if RegReadByInstruction(CurrentReg, hp1) and
  1819. DeepMOVOpt(taicpu(p), taicpu(hp1)) then
  1820. begin
  1821. TransferUsedRegs(TmpUsedRegs);
  1822. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  1823. if not RegUsedAfterInstruction(CurrentReg, hp1, TmpUsedRegs) and
  1824. { Just in case something didn't get modified (e.g. an
  1825. implicit register) }
  1826. not RegReadByInstruction(CurrentReg, hp1) then
  1827. begin
  1828. { We can remove the original MOV }
  1829. DebugMsg(SPeepholeOptimization + 'Mov2Nop 3 done',p);
  1830. RemoveCurrentp(p, hp1);
  1831. { UsedRegs got updated by RemoveCurrentp }
  1832. Result := True;
  1833. Exit;
  1834. end;
  1835. { If we know a MOV instruction has become a null operation, we might as well
  1836. get rid of it now to save time. }
  1837. if (taicpu(hp1).opcode = A_MOV) and
  1838. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1839. SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, taicpu(p).oper[0]^.reg) and
  1840. { Just being a register is enough to confirm it's a null operation }
  1841. (taicpu(hp1).oper[0]^.typ = top_reg) then
  1842. begin
  1843. Result := True;
  1844. { Speed-up to reduce a pipeline stall... if we had something like...
  1845. movl %eax,%edx
  1846. movw %dx,%ax
  1847. ... the second instruction would change to movw %ax,%ax, but
  1848. given that it is now %ax that's active rather than %eax,
  1849. penalties might occur due to a partial register write, so instead,
  1850. change it to a MOVZX instruction when optimising for speed.
  1851. }
  1852. if not (cs_opt_size in current_settings.optimizerswitches) and
  1853. IsMOVZXAcceptable and
  1854. (taicpu(hp1).opsize < taicpu(p).opsize)
  1855. {$ifdef x86_64}
  1856. { operations already implicitly set the upper 64 bits to zero }
  1857. and not ((taicpu(hp1).opsize = S_L) and (taicpu(p).opsize = S_Q))
  1858. {$endif x86_64}
  1859. then
  1860. begin
  1861. CurrentReg := taicpu(hp1).oper[1]^.reg;
  1862. DebugMsg(SPeepholeOptimization + 'Zero-extension to minimise pipeline stall (Mov2Movz)',hp1);
  1863. case taicpu(p).opsize of
  1864. S_W:
  1865. if taicpu(hp1).opsize = S_B then
  1866. taicpu(hp1).opsize := S_BL
  1867. else
  1868. InternalError(2020012911);
  1869. S_L{$ifdef x86_64}, S_Q{$endif x86_64}:
  1870. case taicpu(hp1).opsize of
  1871. S_B:
  1872. taicpu(hp1).opsize := S_BL;
  1873. S_W:
  1874. taicpu(hp1).opsize := S_WL;
  1875. else
  1876. InternalError(2020012912);
  1877. end;
  1878. else
  1879. InternalError(2020012910);
  1880. end;
  1881. taicpu(hp1).opcode := A_MOVZX;
  1882. taicpu(hp1).oper[1]^.reg := newreg(getregtype(CurrentReg), getsupreg(CurrentReg), R_SUBD)
  1883. end
  1884. else
  1885. begin
  1886. GetNextInstruction_p := GetNextInstruction(hp1, hp2);
  1887. DebugMsg(SPeepholeOptimization + 'Mov2Nop 4 done',hp1);
  1888. RemoveInstruction(hp1);
  1889. { The instruction after what was hp1 is now the immediate next instruction,
  1890. so we can continue to make optimisations if it's present }
  1891. if not GetNextInstruction_p or (hp2.typ <> ait_instruction) then
  1892. Exit;
  1893. hp1 := hp2;
  1894. end;
  1895. end;
  1896. end;
  1897. end;
  1898. { Depending on the DeepMOVOpt above, it may turn out that hp1 completely
  1899. overwrites the original destination register. e.g.
  1900. movl ###,%reg2d
  1901. movslq ###,%reg2q (### doesn't have to be the same as the first one)
  1902. In this case, we can remove the MOV (Go to "Mov2Nop 5" below)
  1903. }
  1904. if (taicpu(p).oper[1]^.typ = top_reg) and
  1905. MatchInstruction(hp1, [A_LEA, A_MOV, A_MOVSX, A_MOVZX{$ifdef x86_64}, A_MOVSXD{$endif x86_64}], []) and
  1906. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1907. Reg1WriteOverwritesReg2Entirely(taicpu(hp1).oper[1]^.reg, taicpu(p).oper[1]^.reg) then
  1908. begin
  1909. if RegInOp(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[0]^) then
  1910. begin
  1911. if (taicpu(hp1).oper[0]^.typ = top_reg) then
  1912. case taicpu(p).oper[0]^.typ of
  1913. top_const:
  1914. { We have something like:
  1915. movb $x, %regb
  1916. movzbl %regb,%regd
  1917. Change to:
  1918. movl $x, %regd
  1919. }
  1920. begin
  1921. case taicpu(hp1).opsize of
  1922. S_BW:
  1923. begin
  1924. convert_mov_value(A_MOVSX, $FF);
  1925. setsubreg(taicpu(p).oper[1]^.reg, R_SUBW);
  1926. taicpu(p).opsize := S_W;
  1927. end;
  1928. S_BL:
  1929. begin
  1930. convert_mov_value(A_MOVSX, $FF);
  1931. setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
  1932. taicpu(p).opsize := S_L;
  1933. end;
  1934. S_WL:
  1935. begin
  1936. convert_mov_value(A_MOVSX, $FFFF);
  1937. setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
  1938. taicpu(p).opsize := S_L;
  1939. end;
  1940. {$ifdef x86_64}
  1941. S_BQ:
  1942. begin
  1943. convert_mov_value(A_MOVSX, $FF);
  1944. setsubreg(taicpu(p).oper[1]^.reg, R_SUBQ);
  1945. taicpu(p).opsize := S_Q;
  1946. end;
  1947. S_WQ:
  1948. begin
  1949. convert_mov_value(A_MOVSX, $FFFF);
  1950. setsubreg(taicpu(p).oper[1]^.reg, R_SUBQ);
  1951. taicpu(p).opsize := S_Q;
  1952. end;
  1953. S_LQ:
  1954. begin
  1955. convert_mov_value(A_MOVSXD, $FFFFFFFF); { Note it's MOVSXD, not MOVSX }
  1956. setsubreg(taicpu(p).oper[1]^.reg, R_SUBQ);
  1957. taicpu(p).opsize := S_Q;
  1958. end;
  1959. {$endif x86_64}
  1960. else
  1961. { If hp1 was a MOV instruction, it should have been
  1962. optimised already }
  1963. InternalError(2020021001);
  1964. end;
  1965. DebugMsg(SPeepholeOptimization + 'MovMovXX2MovXX 2 done',p);
  1966. RemoveInstruction(hp1);
  1967. Result := True;
  1968. Exit;
  1969. end;
  1970. top_ref:
  1971. { We have something like:
  1972. movb mem, %regb
  1973. movzbl %regb,%regd
  1974. Change to:
  1975. movzbl mem, %regd
  1976. }
  1977. if (taicpu(p).oper[0]^.ref^.refaddr<>addr_full) and (IsMOVZXAcceptable or (taicpu(hp1).opcode<>A_MOVZX)) then
  1978. begin
  1979. DebugMsg(SPeepholeOptimization + 'MovMovXX2MovXX 1 done',p);
  1980. taicpu(hp1).loadref(0,taicpu(p).oper[0]^.ref^);
  1981. RemoveCurrentP(p, hp1);
  1982. Result:=True;
  1983. Exit;
  1984. end;
  1985. else
  1986. if (taicpu(hp1).opcode <> A_MOV) and (taicpu(hp1).opcode <> A_LEA) then
  1987. { Just to make a saving, since there are no more optimisations with MOVZX and MOVSX/D }
  1988. Exit;
  1989. end;
  1990. end
  1991. { The RegInOp check makes sure that movl r/m,%reg1l; movzbl (%reg1l),%reg1l"
  1992. and "movl r/m,%reg1; leal $1(%reg1,%reg2),%reg1" etc. are not incorrectly
  1993. optimised }
  1994. else
  1995. begin
  1996. DebugMsg(SPeepholeOptimization + 'Mov2Nop 5 done',p);
  1997. RemoveCurrentP(p, hp1);
  1998. Result := True;
  1999. Exit;
  2000. end;
  2001. end;
  2002. if (taicpu(hp1).opcode = A_AND) and
  2003. (taicpu(p).oper[1]^.typ = top_reg) and
  2004. MatchOpType(taicpu(hp1),top_const,top_reg) then
  2005. begin
  2006. if MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) then
  2007. begin
  2008. case taicpu(p).opsize of
  2009. S_L:
  2010. if (taicpu(hp1).oper[0]^.val = $ffffffff) then
  2011. begin
  2012. { Optimize out:
  2013. mov x, %reg
  2014. and ffffffffh, %reg
  2015. }
  2016. DebugMsg(SPeepholeOptimization + 'MovAnd2Mov 1 done',p);
  2017. RemoveInstruction(hp1);
  2018. Result:=true;
  2019. exit;
  2020. end;
  2021. S_Q: { TODO: Confirm if this is even possible }
  2022. if (taicpu(hp1).oper[0]^.val = $ffffffffffffffff) then
  2023. begin
  2024. { Optimize out:
  2025. mov x, %reg
  2026. and ffffffffffffffffh, %reg
  2027. }
  2028. DebugMsg(SPeepholeOptimization + 'MovAnd2Mov 2 done',p);
  2029. RemoveInstruction(hp1);
  2030. Result:=true;
  2031. exit;
  2032. end;
  2033. else
  2034. ;
  2035. end;
  2036. if ((taicpu(p).oper[0]^.typ=top_reg) or
  2037. ((taicpu(p).oper[0]^.typ=top_ref) and (taicpu(p).oper[0]^.ref^.refaddr<>addr_full))) and
  2038. GetNextInstruction(hp1,hp2) and
  2039. MatchInstruction(hp2,A_TEST,[taicpu(p).opsize]) and
  2040. MatchOperand(taicpu(hp1).oper[1]^,taicpu(hp2).oper[1]^) and
  2041. MatchOperand(taicpu(hp2).oper[0]^,taicpu(hp2).oper[1]^) and
  2042. GetNextInstruction(hp2,hp3) and
  2043. MatchInstruction(hp3,A_Jcc,A_Setcc,[S_NO]) and
  2044. (taicpu(hp3).condition in [C_E,C_NE]) then
  2045. begin
  2046. TransferUsedRegs(TmpUsedRegs);
  2047. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  2048. UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
  2049. if not(RegUsedAfterInstruction(taicpu(hp2).oper[1]^.reg, hp2, TmpUsedRegs)) then
  2050. begin
  2051. DebugMsg(SPeepholeOptimization + 'MovAndTest2Test done',p);
  2052. taicpu(hp1).loadoper(1,taicpu(p).oper[0]^);
  2053. taicpu(hp1).opcode:=A_TEST;
  2054. RemoveInstruction(hp2);
  2055. RemoveCurrentP(p, hp1);
  2056. Result:=true;
  2057. exit;
  2058. end;
  2059. end;
  2060. end
  2061. else if IsMOVZXAcceptable and
  2062. (taicpu(p).oper[1]^.typ = top_reg) and (taicpu(hp1).oper[1]^.typ = top_reg) and
  2063. (taicpu(p).oper[0]^.typ <> top_const) and { MOVZX only supports registers and memory, not immediates (use MOV for that!) }
  2064. (getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg))
  2065. then
  2066. begin
  2067. InputVal := debug_operstr(taicpu(p).oper[0]^);
  2068. MaskNum := debug_tostr(taicpu(hp1).oper[0]^.val);
  2069. case taicpu(p).opsize of
  2070. S_B:
  2071. if (taicpu(hp1).oper[0]^.val = $ff) then
  2072. begin
  2073. { Convert:
  2074. movb x, %regl movb x, %regl
  2075. andw ffh, %regw andl ffh, %regd
  2076. To:
  2077. movzbw x, %regd movzbl x, %regd
  2078. (Identical registers, just different sizes)
  2079. }
  2080. RegName1 := debug_regname(taicpu(p).oper[1]^.reg); { 8-bit register name }
  2081. RegName2 := debug_regname(taicpu(hp1).oper[1]^.reg); { 16/32-bit register name }
  2082. case taicpu(hp1).opsize of
  2083. S_W: NewSize := S_BW;
  2084. S_L: NewSize := S_BL;
  2085. {$ifdef x86_64}
  2086. S_Q: NewSize := S_BQ;
  2087. {$endif x86_64}
  2088. else
  2089. InternalError(2018011510);
  2090. end;
  2091. end
  2092. else
  2093. NewSize := S_NO;
  2094. S_W:
  2095. if (taicpu(hp1).oper[0]^.val = $ffff) then
  2096. begin
  2097. { Convert:
  2098. movw x, %regw
  2099. andl ffffh, %regd
  2100. To:
  2101. movzwl x, %regd
  2102. (Identical registers, just different sizes)
  2103. }
  2104. RegName1 := debug_regname(taicpu(p).oper[1]^.reg); { 16-bit register name }
  2105. RegName2 := debug_regname(taicpu(hp1).oper[1]^.reg); { 32-bit register name }
  2106. case taicpu(hp1).opsize of
  2107. S_L: NewSize := S_WL;
  2108. {$ifdef x86_64}
  2109. S_Q: NewSize := S_WQ;
  2110. {$endif x86_64}
  2111. else
  2112. InternalError(2018011511);
  2113. end;
  2114. end
  2115. else
  2116. NewSize := S_NO;
  2117. else
  2118. NewSize := S_NO;
  2119. end;
  2120. if NewSize <> S_NO then
  2121. begin
  2122. PreMessage := 'mov' + debug_opsize2str(taicpu(p).opsize) + ' ' + InputVal + ',' + RegName1;
  2123. { The actual optimization }
  2124. taicpu(p).opcode := A_MOVZX;
  2125. taicpu(p).changeopsize(NewSize);
  2126. taicpu(p).oper[1]^ := taicpu(hp1).oper[1]^;
  2127. { Safeguard if "and" is followed by a conditional command }
  2128. TransferUsedRegs(TmpUsedRegs);
  2129. UpdateUsedRegs(TmpUsedRegs,tai(p.next));
  2130. if (RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs)) then
  2131. begin
  2132. { At this point, the "and" command is effectively equivalent to
  2133. "test %reg,%reg". This will be handled separately by the
  2134. Peephole Optimizer. [Kit] }
  2135. DebugMsg(SPeepholeOptimization + PreMessage +
  2136. ' -> movz' + debug_opsize2str(NewSize) + ' ' + InputVal + ',' + RegName2, p);
  2137. end
  2138. else
  2139. begin
  2140. DebugMsg(SPeepholeOptimization + PreMessage + '; and' + debug_opsize2str(taicpu(hp1).opsize) + ' $' + MaskNum + ',' + RegName2 +
  2141. ' -> movz' + debug_opsize2str(NewSize) + ' ' + InputVal + ',' + RegName2, p);
  2142. RemoveInstruction(hp1);
  2143. end;
  2144. Result := True;
  2145. Exit;
  2146. end;
  2147. end;
  2148. end;
  2149. { Next instruction is also a MOV ? }
  2150. if MatchInstruction(hp1,A_MOV,[taicpu(p).opsize]) then
  2151. begin
  2152. if (taicpu(p).oper[1]^.typ = top_reg) and
  2153. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) then
  2154. begin
  2155. CurrentReg := taicpu(p).oper[1]^.reg;
  2156. TransferUsedRegs(TmpUsedRegs);
  2157. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  2158. { we have
  2159. mov x, %treg
  2160. mov %treg, y
  2161. }
  2162. if not(RegInOp(CurrentReg, taicpu(hp1).oper[1]^)) then
  2163. if not(RegUsedAfterInstruction(CurrentReg, hp1, TmpUsedRegs)) then
  2164. { we've got
  2165. mov x, %treg
  2166. mov %treg, y
  2167. with %treg is not used after }
  2168. case taicpu(p).oper[0]^.typ Of
  2169. { top_reg is covered by DeepMOVOpt }
  2170. top_const:
  2171. begin
  2172. { change
  2173. mov const, %treg
  2174. mov %treg, y
  2175. to
  2176. mov const, y
  2177. }
  2178. if (taicpu(hp1).oper[1]^.typ=top_reg) or
  2179. ((taicpu(p).oper[0]^.val>=low(longint)) and (taicpu(p).oper[0]^.val<=high(longint))) then
  2180. begin
  2181. if taicpu(hp1).oper[1]^.typ=top_reg then
  2182. AllocRegBetween(taicpu(hp1).oper[1]^.reg,p,hp1,usedregs);
  2183. taicpu(p).loadOper(1,taicpu(hp1).oper[1]^);
  2184. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 5 done',p);
  2185. RemoveInstruction(hp1);
  2186. Result:=true;
  2187. Exit;
  2188. end;
  2189. end;
  2190. top_ref:
  2191. if (taicpu(hp1).oper[1]^.typ = top_reg) then
  2192. begin
  2193. { change
  2194. mov mem, %treg
  2195. mov %treg, %reg
  2196. to
  2197. mov mem, %reg"
  2198. }
  2199. AllocRegBetween(taicpu(hp1).oper[1]^.reg,p,hp1,usedregs);
  2200. taicpu(p).loadreg(1, taicpu(hp1).oper[1]^.reg);
  2201. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 3 done',p);
  2202. RemoveInstruction(hp1);
  2203. Result:=true;
  2204. Exit;
  2205. end;
  2206. else
  2207. ;
  2208. end
  2209. else
  2210. { %treg is used afterwards, but all eventualities
  2211. other than the first MOV instruction being a constant
  2212. are covered by DeepMOVOpt, so only check for that }
  2213. if (taicpu(p).oper[0]^.typ = top_const) and
  2214. (
  2215. { For MOV operations, a size saving is only made if the register/const is byte-sized }
  2216. not (cs_opt_size in current_settings.optimizerswitches) or
  2217. (taicpu(hp1).opsize = S_B)
  2218. ) and
  2219. (
  2220. (taicpu(hp1).oper[1]^.typ = top_reg) or
  2221. ((taicpu(p).oper[0]^.val >= low(longint)) and (taicpu(p).oper[0]^.val <= high(longint)))
  2222. ) then
  2223. begin
  2224. DebugMsg(SPeepholeOptimization + debug_operstr(taicpu(hp1).oper[0]^) + ' = $' + debug_tostr(taicpu(p).oper[0]^.val) + '; changed to minimise pipeline stall (MovMov2Mov 6b)',hp1);
  2225. taicpu(hp1).loadconst(0, taicpu(p).oper[0]^.val);
  2226. end;
  2227. end;
  2228. if (taicpu(hp1).oper[0]^.typ = taicpu(p).oper[1]^.typ) and
  2229. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[0]^.typ) then
  2230. { mov reg1, mem1 or mov mem1, reg1
  2231. mov mem2, reg2 mov reg2, mem2}
  2232. begin
  2233. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) then
  2234. { mov reg1, mem1 or mov mem1, reg1
  2235. mov mem2, reg1 mov reg2, mem1}
  2236. begin
  2237. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  2238. { Removes the second statement from
  2239. mov reg1, mem1/reg2
  2240. mov mem1/reg2, reg1 }
  2241. begin
  2242. if taicpu(p).oper[0]^.typ=top_reg then
  2243. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  2244. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 1',p);
  2245. RemoveInstruction(hp1);
  2246. Result:=true;
  2247. exit;
  2248. end
  2249. else
  2250. begin
  2251. TransferUsedRegs(TmpUsedRegs);
  2252. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  2253. if (taicpu(p).oper[1]^.typ = top_ref) and
  2254. { mov reg1, mem1
  2255. mov mem2, reg1 }
  2256. (taicpu(hp1).oper[0]^.ref^.refaddr = addr_no) and
  2257. GetNextInstruction(hp1, hp2) and
  2258. MatchInstruction(hp2,A_CMP,[taicpu(p).opsize]) and
  2259. OpsEqual(taicpu(p).oper[1]^,taicpu(hp2).oper[0]^) and
  2260. OpsEqual(taicpu(p).oper[0]^,taicpu(hp2).oper[1]^) and
  2261. not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp2, TmpUsedRegs)) then
  2262. { change to
  2263. mov reg1, mem1 mov reg1, mem1
  2264. mov mem2, reg1 cmp reg1, mem2
  2265. cmp mem1, reg1
  2266. }
  2267. begin
  2268. RemoveInstruction(hp2);
  2269. taicpu(hp1).opcode := A_CMP;
  2270. taicpu(hp1).loadref(1,taicpu(hp1).oper[0]^.ref^);
  2271. taicpu(hp1).loadreg(0,taicpu(p).oper[0]^.reg);
  2272. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,UsedRegs);
  2273. DebugMsg(SPeepholeOptimization + 'MovMovCmp2MovCmp done',hp1);
  2274. end;
  2275. end;
  2276. end
  2277. else if (taicpu(p).oper[1]^.typ=top_ref) and
  2278. OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  2279. begin
  2280. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,UsedRegs);
  2281. taicpu(hp1).loadreg(0,taicpu(p).oper[0]^.reg);
  2282. DebugMsg(SPeepholeOptimization + 'MovMov2MovMov1 done',p);
  2283. end
  2284. else
  2285. begin
  2286. TransferUsedRegs(TmpUsedRegs);
  2287. if GetNextInstruction(hp1, hp2) and
  2288. MatchOpType(taicpu(p),top_ref,top_reg) and
  2289. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) and
  2290. (taicpu(hp1).oper[1]^.typ = top_ref) and
  2291. MatchInstruction(hp2,A_MOV,[taicpu(p).opsize]) and
  2292. MatchOpType(taicpu(hp2),top_ref,top_reg) and
  2293. RefsEqual(taicpu(hp2).oper[0]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  2294. if not RegInRef(taicpu(hp2).oper[1]^.reg,taicpu(hp2).oper[0]^.ref^) and
  2295. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,tmpUsedRegs)) then
  2296. { mov mem1, %reg1
  2297. mov %reg1, mem2
  2298. mov mem2, reg2
  2299. to:
  2300. mov mem1, reg2
  2301. mov reg2, mem2}
  2302. begin
  2303. AllocRegBetween(taicpu(hp2).oper[1]^.reg,p,hp2,usedregs);
  2304. DebugMsg(SPeepholeOptimization + 'MovMovMov2MovMov 1 done',p);
  2305. taicpu(p).loadoper(1,taicpu(hp2).oper[1]^);
  2306. taicpu(hp1).loadoper(0,taicpu(hp2).oper[1]^);
  2307. RemoveInstruction(hp2);
  2308. end
  2309. {$ifdef i386}
  2310. { this is enabled for i386 only, as the rules to create the reg sets below
  2311. are too complicated for x86-64, so this makes this code too error prone
  2312. on x86-64
  2313. }
  2314. else if (taicpu(p).oper[1]^.reg <> taicpu(hp2).oper[1]^.reg) and
  2315. not(RegInRef(taicpu(p).oper[1]^.reg,taicpu(p).oper[0]^.ref^)) and
  2316. not(RegInRef(taicpu(hp2).oper[1]^.reg,taicpu(hp2).oper[0]^.ref^)) then
  2317. { mov mem1, reg1 mov mem1, reg1
  2318. mov reg1, mem2 mov reg1, mem2
  2319. mov mem2, reg2 mov mem2, reg1
  2320. to: to:
  2321. mov mem1, reg1 mov mem1, reg1
  2322. mov mem1, reg2 mov reg1, mem2
  2323. mov reg1, mem2
  2324. or (if mem1 depends on reg1
  2325. and/or if mem2 depends on reg2)
  2326. to:
  2327. mov mem1, reg1
  2328. mov reg1, mem2
  2329. mov reg1, reg2
  2330. }
  2331. begin
  2332. taicpu(hp1).loadRef(0,taicpu(p).oper[0]^.ref^);
  2333. taicpu(hp1).loadReg(1,taicpu(hp2).oper[1]^.reg);
  2334. taicpu(hp2).loadRef(1,taicpu(hp2).oper[0]^.ref^);
  2335. taicpu(hp2).loadReg(0,taicpu(p).oper[1]^.reg);
  2336. AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  2337. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  2338. (getsupreg(taicpu(p).oper[0]^.ref^.base) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  2339. AllocRegBetween(taicpu(p).oper[0]^.ref^.base,p,hp2,usedregs);
  2340. if (taicpu(p).oper[0]^.ref^.index <> NR_NO) and
  2341. (getsupreg(taicpu(p).oper[0]^.ref^.index) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  2342. AllocRegBetween(taicpu(p).oper[0]^.ref^.index,p,hp2,usedregs);
  2343. end
  2344. else if (taicpu(hp1).Oper[0]^.reg <> taicpu(hp2).Oper[1]^.reg) then
  2345. begin
  2346. taicpu(hp2).loadReg(0,taicpu(hp1).Oper[0]^.reg);
  2347. AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  2348. end
  2349. else
  2350. begin
  2351. RemoveInstruction(hp2);
  2352. end
  2353. {$endif i386}
  2354. ;
  2355. end;
  2356. end
  2357. { movl [mem1],reg1
  2358. movl [mem1],reg2
  2359. to
  2360. movl [mem1],reg1
  2361. movl reg1,reg2
  2362. }
  2363. else if MatchOpType(taicpu(p),top_ref,top_reg) and
  2364. MatchOpType(taicpu(hp1),top_ref,top_reg) and
  2365. (taicpu(p).opsize = taicpu(hp1).opsize) and
  2366. RefsEqual(taicpu(p).oper[0]^.ref^,taicpu(hp1).oper[0]^.ref^) and
  2367. (taicpu(p).oper[0]^.ref^.volatility=[]) and
  2368. (taicpu(hp1).oper[0]^.ref^.volatility=[]) and
  2369. not(SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[0]^.ref^.base)) and
  2370. not(SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[0]^.ref^.index)) then
  2371. begin
  2372. DebugMsg(SPeepholeOptimization + 'MovMov2MovMov 2',p);
  2373. taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg);
  2374. end;
  2375. { movl const1,[mem1]
  2376. movl [mem1],reg1
  2377. to
  2378. movl const1,reg1
  2379. movl reg1,[mem1]
  2380. }
  2381. if MatchOpType(Taicpu(p),top_const,top_ref) and
  2382. MatchOpType(Taicpu(hp1),top_ref,top_reg) and
  2383. (taicpu(p).opsize = taicpu(hp1).opsize) and
  2384. RefsEqual(taicpu(hp1).oper[0]^.ref^,taicpu(p).oper[1]^.ref^) and
  2385. not(RegInRef(taicpu(hp1).oper[1]^.reg,taicpu(hp1).oper[0]^.ref^)) then
  2386. begin
  2387. AllocRegBetween(taicpu(hp1).oper[1]^.reg,p,hp1,usedregs);
  2388. taicpu(hp1).loadReg(0,taicpu(hp1).oper[1]^.reg);
  2389. taicpu(hp1).loadRef(1,taicpu(p).oper[1]^.ref^);
  2390. taicpu(p).loadReg(1,taicpu(hp1).oper[0]^.reg);
  2391. taicpu(hp1).fileinfo := taicpu(p).fileinfo;
  2392. DebugMsg(SPeepholeOptimization + 'MovMov2MovMov 1',p);
  2393. Result:=true;
  2394. exit;
  2395. end;
  2396. { mov x,reg1; mov y,reg1 -> mov y,reg1 is handled by the Mov2Nop 5 optimisation }
  2397. end;
  2398. { search further than the next instruction for a mov }
  2399. if
  2400. { check as much as possible before the expensive GetNextInstructionUsingRegCond call }
  2401. (taicpu(p).oper[1]^.typ = top_reg) and
  2402. (taicpu(p).oper[0]^.typ in [top_reg,top_const]) and
  2403. not RegModifiedByInstruction(taicpu(p).oper[1]^.reg, hp1) then
  2404. begin
  2405. { we work with hp2 here, so hp1 can be still used later on when
  2406. checking for GetNextInstruction_p }
  2407. hp3 := hp1;
  2408. { Initialise CrossJump (if it becomes True at any point, it will remain True) }
  2409. CrossJump := False;
  2410. while GetNextInstructionUsingRegCond(hp3,hp2,taicpu(p).oper[1]^.reg,CrossJump) and
  2411. { GetNextInstructionUsingRegCond only searches one instruction ahead unless -O3 is specified }
  2412. (hp2.typ=ait_instruction) do
  2413. begin
  2414. case taicpu(hp2).opcode of
  2415. A_MOV:
  2416. if MatchOperand(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^.reg) and
  2417. ((taicpu(p).oper[0]^.typ=top_const) or
  2418. ((taicpu(p).oper[0]^.typ=top_reg) and
  2419. not(RegModifiedBetween(taicpu(p).oper[0]^.reg, p, hp2))
  2420. )
  2421. ) then
  2422. begin
  2423. { we have
  2424. mov x, %treg
  2425. mov %treg, y
  2426. }
  2427. TransferUsedRegs(TmpUsedRegs);
  2428. TmpUsedRegs[R_INTREGISTER].Update(tai(p.Next));
  2429. { We don't need to call UpdateUsedRegs for every instruction between
  2430. p and hp2 because the register we're concerned about will not
  2431. become deallocated (otherwise GetNextInstructionUsingReg would
  2432. have stopped at an earlier instruction). [Kit] }
  2433. TempRegUsed :=
  2434. CrossJump { Assume the register is in use if it crossed a conditional jump } or
  2435. RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp2, TmpUsedRegs) or
  2436. RegReadByInstruction(taicpu(p).oper[1]^.reg, hp1);
  2437. case taicpu(p).oper[0]^.typ Of
  2438. top_reg:
  2439. begin
  2440. { change
  2441. mov %reg, %treg
  2442. mov %treg, y
  2443. to
  2444. mov %reg, y
  2445. }
  2446. CurrentReg := taicpu(p).oper[0]^.reg; { Saves on a handful of pointer dereferences }
  2447. RegName1 := debug_regname(taicpu(hp2).oper[0]^.reg);
  2448. if taicpu(hp2).oper[1]^.reg = CurrentReg then
  2449. begin
  2450. { %reg = y - remove hp2 completely (doing it here instead of relying on
  2451. the "mov %reg,%reg" optimisation might cut down on a pass iteration) }
  2452. if TempRegUsed then
  2453. begin
  2454. DebugMsg(SPeepholeOptimization + debug_regname(CurrentReg) + ' = ' + RegName1 + '; removed unnecessary instruction (MovMov2MovNop 6b}',hp2);
  2455. AllocRegBetween(CurrentReg, p, hp2, UsedRegs);
  2456. { Set the start of the next GetNextInstructionUsingRegCond search
  2457. to start at the entry right before hp2 (which is about to be removed) }
  2458. hp3 := tai(hp2.Previous);
  2459. RemoveInstruction(hp2);
  2460. { See if there's more we can optimise }
  2461. Continue;
  2462. end
  2463. else
  2464. begin
  2465. RemoveInstruction(hp2);
  2466. { We can remove the original MOV too }
  2467. DebugMsg(SPeepholeOptimization + 'MovMov2NopNop 6b done',p);
  2468. RemoveCurrentP(p, hp1);
  2469. Result:=true;
  2470. Exit;
  2471. end;
  2472. end
  2473. else
  2474. begin
  2475. AllocRegBetween(CurrentReg, p, hp2, UsedRegs);
  2476. taicpu(hp2).loadReg(0, CurrentReg);
  2477. if TempRegUsed then
  2478. begin
  2479. { Don't remove the first instruction if the temporary register is in use }
  2480. DebugMsg(SPeepholeOptimization + RegName1 + ' = ' + debug_regname(CurrentReg) + '; changed to minimise pipeline stall (MovMov2Mov 6a}',hp2);
  2481. { No need to set Result to True. If there's another instruction later on
  2482. that can be optimised, it will be detected when the main Pass 1 loop
  2483. reaches what is now hp2 and passes it through OptPass1MOV. [Kit] };
  2484. end
  2485. else
  2486. begin
  2487. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 6 done',p);
  2488. RemoveCurrentP(p, hp1);
  2489. Result:=true;
  2490. Exit;
  2491. end;
  2492. end;
  2493. end;
  2494. top_const:
  2495. if not (cs_opt_size in current_settings.optimizerswitches) or (taicpu(hp2).opsize = S_B) then
  2496. begin
  2497. { change
  2498. mov const, %treg
  2499. mov %treg, y
  2500. to
  2501. mov const, y
  2502. }
  2503. if (taicpu(hp2).oper[1]^.typ=top_reg) or
  2504. ((taicpu(p).oper[0]^.val>=low(longint)) and (taicpu(p).oper[0]^.val<=high(longint))) then
  2505. begin
  2506. RegName1 := debug_regname(taicpu(hp2).oper[0]^.reg);
  2507. taicpu(hp2).loadOper(0,taicpu(p).oper[0]^);
  2508. if TempRegUsed then
  2509. begin
  2510. { Don't remove the first instruction if the temporary register is in use }
  2511. DebugMsg(SPeepholeOptimization + RegName1 + ' = ' + debug_tostr(taicpu(p).oper[0]^.val) + '; changed to minimise pipeline stall (MovMov2Mov 7a)',hp2);
  2512. { No need to set Result to True. If there's another instruction later on
  2513. that can be optimised, it will be detected when the main Pass 1 loop
  2514. reaches what is now hp2 and passes it through OptPass1MOV. [Kit] };
  2515. end
  2516. else
  2517. begin
  2518. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 7 done',p);
  2519. RemoveCurrentP(p, hp1);
  2520. Result:=true;
  2521. Exit;
  2522. end;
  2523. end;
  2524. end;
  2525. else
  2526. Internalerror(2019103001);
  2527. end;
  2528. end;
  2529. A_MOVZX, A_MOVSX{$ifdef x86_64}, A_MOVSXD{$endif x86_64}:
  2530. if MatchOpType(taicpu(hp2), top_reg, top_reg) and
  2531. MatchOperand(taicpu(hp2).oper[0]^, taicpu(p).oper[1]^.reg) and
  2532. SuperRegistersEqual(taicpu(hp2).oper[1]^.reg, taicpu(p).oper[1]^.reg) then
  2533. begin
  2534. {
  2535. Change from:
  2536. mov ###, %reg
  2537. ...
  2538. movs/z %reg,%reg (Same register, just different sizes)
  2539. To:
  2540. movs/z ###, %reg (Longer version)
  2541. ...
  2542. (remove)
  2543. }
  2544. DebugMsg(SPeepholeOptimization + 'MovMovs/z2Mov/s/z done', p);
  2545. taicpu(p).oper[1]^.reg := taicpu(hp2).oper[1]^.reg;
  2546. { Keep the first instruction as mov if ### is a constant }
  2547. if taicpu(p).oper[0]^.typ = top_const then
  2548. taicpu(p).opsize := reg2opsize(taicpu(hp2).oper[1]^.reg)
  2549. else
  2550. begin
  2551. taicpu(p).opcode := taicpu(hp2).opcode;
  2552. taicpu(p).opsize := taicpu(hp2).opsize;
  2553. end;
  2554. DebugMsg(SPeepholeOptimization + 'Removed movs/z instruction and extended earlier write (MovMovs/z2Mov/s/z)', hp2);
  2555. AllocRegBetween(taicpu(hp2).oper[1]^.reg, p, hp2, UsedRegs);
  2556. RemoveInstruction(hp2);
  2557. Result := True;
  2558. Exit;
  2559. end;
  2560. else
  2561. if MatchOpType(taicpu(p), top_reg, top_reg) then
  2562. begin
  2563. CurrentReg := taicpu(p).oper[1]^.reg;
  2564. TransferUsedRegs(TmpUsedRegs);
  2565. TmpUsedRegs[R_INTREGISTER].Update(tai(p.Next));
  2566. if
  2567. not RegModifiedByInstruction(taicpu(p).oper[0]^.reg, hp1) and
  2568. not RegModifiedBetween(taicpu(p).oper[0]^.reg, hp1, hp2) and
  2569. DeepMovOpt(taicpu(p), taicpu(hp2)) then
  2570. begin
  2571. { Just in case something didn't get modified (e.g. an
  2572. implicit register) }
  2573. if not RegReadByInstruction(CurrentReg, hp2) and
  2574. { If a conditional jump was crossed, do not delete
  2575. the original MOV no matter what }
  2576. not CrossJump then
  2577. begin
  2578. TransferUsedRegs(TmpUsedRegs);
  2579. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  2580. UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
  2581. if not RegUsedAfterInstruction(CurrentReg, hp2, TmpUsedRegs) then
  2582. begin
  2583. { We can remove the original MOV }
  2584. DebugMsg(SPeepholeOptimization + 'Mov2Nop 3b done',p);
  2585. RemoveCurrentp(p, hp1);
  2586. Result := True;
  2587. Exit;
  2588. end
  2589. else
  2590. begin
  2591. { See if there's more we can optimise }
  2592. hp3 := hp2;
  2593. Continue;
  2594. end;
  2595. end;
  2596. end;
  2597. end;
  2598. end;
  2599. { Break out of the while loop under normal circumstances }
  2600. Break;
  2601. end;
  2602. end;
  2603. if (aoc_MovAnd2Mov_3 in OptsToCheck) and
  2604. (taicpu(p).oper[1]^.typ = top_reg) and
  2605. (taicpu(p).opsize = S_L) and
  2606. GetNextInstructionUsingRegTrackingUse(p,hp2,taicpu(p).oper[1]^.reg) and
  2607. (taicpu(hp2).opcode = A_AND) and
  2608. (MatchOpType(taicpu(hp2),top_const,top_reg) or
  2609. (MatchOpType(taicpu(hp2),top_reg,top_reg) and
  2610. MatchOperand(taicpu(hp2).oper[0]^,taicpu(hp2).oper[1]^))
  2611. ) then
  2612. begin
  2613. if SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp2).oper[1]^.reg) then
  2614. begin
  2615. if ((taicpu(hp2).oper[0]^.typ=top_const) and (taicpu(hp2).oper[0]^.val = $ffffffff)) or
  2616. ((taicpu(hp2).oper[0]^.typ=top_reg) and (taicpu(hp2).opsize=S_L)) then
  2617. begin
  2618. { Optimize out:
  2619. mov x, %reg
  2620. and ffffffffh, %reg
  2621. }
  2622. DebugMsg(SPeepholeOptimization + 'MovAnd2Mov 3 done',p);
  2623. RemoveInstruction(hp2);
  2624. Result:=true;
  2625. exit;
  2626. end;
  2627. end;
  2628. end;
  2629. { leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  2630. x >= RetOffset) as it doesn't do anything (it writes either to a
  2631. parameter or to the temporary storage room for the function
  2632. result)
  2633. }
  2634. if IsExitCode(hp1) and
  2635. (taicpu(p).oper[1]^.typ = top_ref) and
  2636. (taicpu(p).oper[1]^.ref^.index = NR_NO) and
  2637. (
  2638. (
  2639. (taicpu(p).oper[1]^.ref^.base = current_procinfo.FramePointer) and
  2640. not (
  2641. assigned(current_procinfo.procdef.funcretsym) and
  2642. (taicpu(p).oper[1]^.ref^.offset <= tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)
  2643. )
  2644. ) or
  2645. { Also discard writes to the stack that are below the base pointer,
  2646. as this is temporary storage rather than a function result on the
  2647. stack, say. }
  2648. (
  2649. (taicpu(p).oper[1]^.ref^.base = NR_STACK_POINTER_REG) and
  2650. (taicpu(p).oper[1]^.ref^.offset < current_procinfo.final_localsize)
  2651. )
  2652. ) then
  2653. begin
  2654. RemoveCurrentp(p, hp1);
  2655. DebugMsg(SPeepholeOptimization + 'removed deadstore before leave/ret',p);
  2656. RemoveLastDeallocForFuncRes(p);
  2657. Result:=true;
  2658. exit;
  2659. end;
  2660. if MatchInstruction(hp1,A_CMP,A_TEST,[taicpu(p).opsize]) then
  2661. begin
  2662. if MatchOpType(taicpu(p),top_reg,top_ref) and
  2663. (taicpu(hp1).oper[1]^.typ = top_ref) and
  2664. RefsEqual(taicpu(p).oper[1]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  2665. begin
  2666. { change
  2667. mov reg1, mem1
  2668. test/cmp x, mem1
  2669. to
  2670. mov reg1, mem1
  2671. test/cmp x, reg1
  2672. }
  2673. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  2674. DebugMsg(SPeepholeOptimization + 'MovTestCmp2MovTestCmp 1',hp1);
  2675. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  2676. Result := True;
  2677. Exit;
  2678. end;
  2679. if MatchOpType(taicpu(p),top_ref,top_reg) and
  2680. { The x86 assemblers have difficulty comparing values against absolute addresses }
  2681. (taicpu(p).oper[0]^.ref^.refaddr in [addr_no, addr_pic, addr_pic_no_got]) and
  2682. (taicpu(hp1).oper[0]^.typ <> top_ref) and
  2683. MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^.reg) and
  2684. (
  2685. (
  2686. (taicpu(hp1).opcode = A_TEST)
  2687. ) or (
  2688. (taicpu(hp1).opcode = A_CMP) and
  2689. { A sanity check more than anything }
  2690. not MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[1]^.reg)
  2691. )
  2692. ) then
  2693. begin
  2694. { change
  2695. mov mem, %reg
  2696. cmp/test x, %reg / test %reg,%reg
  2697. (reg deallocated)
  2698. to
  2699. cmp/test x, mem / cmp 0, mem
  2700. }
  2701. TransferUsedRegs(TmpUsedRegs);
  2702. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  2703. if not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs) then
  2704. begin
  2705. { Convert test %reg,%reg or test $-1,%reg to cmp $0,mem }
  2706. if (taicpu(hp1).opcode = A_TEST) and
  2707. (
  2708. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[1]^.reg) or
  2709. MatchOperand(taicpu(hp1).oper[0]^, -1)
  2710. ) then
  2711. begin
  2712. taicpu(hp1).opcode := A_CMP;
  2713. taicpu(hp1).loadconst(0, 0);
  2714. end;
  2715. taicpu(hp1).loadref(1, taicpu(p).oper[0]^.ref^);
  2716. DebugMsg(SPeepholeOptimization + 'MOV/CMP -> CMP (memory check)', p);
  2717. RemoveCurrentP(p, hp1);
  2718. Result := True;
  2719. Exit;
  2720. end;
  2721. end;
  2722. end;
  2723. if MatchInstruction(hp1,A_LEA,[S_L{$ifdef x86_64},S_Q{$endif x86_64}]) and
  2724. { If the flags register is in use, don't change the instruction to an
  2725. ADD otherwise this will scramble the flags. [Kit] }
  2726. not RegInUsedRegs(NR_DEFAULTFLAGS, UsedRegs) then
  2727. begin
  2728. if MatchOpType(Taicpu(p),top_ref,top_reg) and
  2729. ((MatchReference(Taicpu(hp1).oper[0]^.ref^,Taicpu(hp1).oper[1]^.reg,Taicpu(p).oper[1]^.reg) and
  2730. (Taicpu(hp1).oper[0]^.ref^.base<>Taicpu(p).oper[1]^.reg)
  2731. ) or
  2732. (MatchReference(Taicpu(hp1).oper[0]^.ref^,Taicpu(p).oper[1]^.reg,Taicpu(hp1).oper[1]^.reg) and
  2733. (Taicpu(hp1).oper[0]^.ref^.index<>Taicpu(p).oper[1]^.reg)
  2734. )
  2735. ) then
  2736. { mov reg1,ref
  2737. lea reg2,[reg1,reg2]
  2738. to
  2739. add reg2,ref}
  2740. begin
  2741. TransferUsedRegs(TmpUsedRegs);
  2742. { reg1 may not be used afterwards }
  2743. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs)) then
  2744. begin
  2745. Taicpu(hp1).opcode:=A_ADD;
  2746. Taicpu(hp1).oper[0]^.ref^:=Taicpu(p).oper[0]^.ref^;
  2747. DebugMsg(SPeepholeOptimization + 'MovLea2Add done',hp1);
  2748. RemoveCurrentp(p, hp1);
  2749. result:=true;
  2750. exit;
  2751. end;
  2752. end;
  2753. { If the LEA instruction can be converted into an arithmetic instruction,
  2754. it may be possible to then fold it in the next optimisation, otherwise
  2755. there's nothing more that can be optimised here. }
  2756. if not ConvertLEA(taicpu(hp1)) then
  2757. Exit;
  2758. end;
  2759. if (taicpu(p).oper[1]^.typ = top_reg) and
  2760. (hp1.typ = ait_instruction) and
  2761. GetNextInstruction(hp1, hp2) and
  2762. MatchInstruction(hp2,A_MOV,[]) and
  2763. (SuperRegistersEqual(taicpu(hp2).oper[0]^.reg,taicpu(p).oper[1]^.reg)) and
  2764. (
  2765. IsFoldableArithOp(taicpu(hp1), taicpu(p).oper[1]^.reg)
  2766. {$ifdef x86_64}
  2767. or
  2768. (
  2769. (taicpu(p).opsize=S_L) and (taicpu(hp1).opsize=S_Q) and (taicpu(hp2).opsize=S_L) and
  2770. IsFoldableArithOp(taicpu(hp1), newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[1]^.reg),R_SUBQ))
  2771. )
  2772. {$endif x86_64}
  2773. ) then
  2774. begin
  2775. if OpsEqual(taicpu(hp2).oper[1]^, taicpu(p).oper[0]^) and
  2776. (taicpu(hp2).oper[0]^.typ=top_reg) then
  2777. { change movsX/movzX reg/ref, reg2
  2778. add/sub/or/... reg3/$const, reg2
  2779. mov reg2 reg/ref
  2780. dealloc reg2
  2781. to
  2782. add/sub/or/... reg3/$const, reg/ref }
  2783. begin
  2784. TransferUsedRegs(TmpUsedRegs);
  2785. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  2786. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  2787. If not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs)) then
  2788. begin
  2789. { by example:
  2790. movswl %si,%eax movswl %si,%eax p
  2791. decl %eax addl %edx,%eax hp1
  2792. movw %ax,%si movw %ax,%si hp2
  2793. ->
  2794. movswl %si,%eax movswl %si,%eax p
  2795. decw %eax addw %edx,%eax hp1
  2796. movw %ax,%si movw %ax,%si hp2
  2797. }
  2798. DebugMsg(SPeepholeOptimization + 'MovOpMov2Op ('+
  2799. debug_op2str(taicpu(p).opcode)+debug_opsize2str(taicpu(p).opsize)+' '+
  2800. debug_op2str(taicpu(hp1).opcode)+debug_opsize2str(taicpu(hp1).opsize)+' '+
  2801. debug_op2str(taicpu(hp2).opcode)+debug_opsize2str(taicpu(hp2).opsize)+')',p);
  2802. taicpu(hp1).changeopsize(taicpu(hp2).opsize);
  2803. {
  2804. ->
  2805. movswl %si,%eax movswl %si,%eax p
  2806. decw %si addw %dx,%si hp1
  2807. movw %ax,%si movw %ax,%si hp2
  2808. }
  2809. case taicpu(hp1).ops of
  2810. 1:
  2811. begin
  2812. taicpu(hp1).loadoper(0, taicpu(hp2).oper[1]^);
  2813. if taicpu(hp1).oper[0]^.typ=top_reg then
  2814. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  2815. end;
  2816. 2:
  2817. begin
  2818. taicpu(hp1).loadoper(1, taicpu(hp2).oper[1]^);
  2819. if (taicpu(hp1).oper[0]^.typ=top_reg) and
  2820. (taicpu(hp1).opcode<>A_SHL) and
  2821. (taicpu(hp1).opcode<>A_SHR) and
  2822. (taicpu(hp1).opcode<>A_SAR) then
  2823. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  2824. end;
  2825. else
  2826. internalerror(2008042701);
  2827. end;
  2828. {
  2829. ->
  2830. decw %si addw %dx,%si p
  2831. }
  2832. RemoveInstruction(hp2);
  2833. RemoveCurrentP(p, hp1);
  2834. Result:=True;
  2835. Exit;
  2836. end;
  2837. end;
  2838. if MatchOpType(taicpu(hp2),top_reg,top_reg) and
  2839. not(SuperRegistersEqual(taicpu(hp1).oper[0]^.reg,taicpu(hp2).oper[1]^.reg)) and
  2840. ((topsize2memsize[taicpu(hp1).opsize]<= topsize2memsize[taicpu(hp2).opsize]) or
  2841. { opsize matters for these opcodes, we could probably work around this, but it is not worth the effort }
  2842. ((taicpu(hp1).opcode<>A_SHL) and (taicpu(hp1).opcode<>A_SHR) and (taicpu(hp1).opcode<>A_SAR))
  2843. )
  2844. {$ifdef i386}
  2845. { byte registers of esi, edi, ebp, esp are not available on i386 }
  2846. and ((taicpu(hp2).opsize<>S_B) or not(getsupreg(taicpu(hp1).oper[0]^.reg) in [RS_ESI,RS_EDI,RS_EBP,RS_ESP]))
  2847. and ((taicpu(hp2).opsize<>S_B) or not(getsupreg(taicpu(p).oper[0]^.reg) in [RS_ESI,RS_EDI,RS_EBP,RS_ESP]))
  2848. {$endif i386}
  2849. then
  2850. { change movsX/movzX reg/ref, reg2
  2851. add/sub/or/... regX/$const, reg2
  2852. mov reg2, reg3
  2853. dealloc reg2
  2854. to
  2855. movsX/movzX reg/ref, reg3
  2856. add/sub/or/... reg3/$const, reg3
  2857. }
  2858. begin
  2859. TransferUsedRegs(TmpUsedRegs);
  2860. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  2861. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  2862. If not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs)) then
  2863. begin
  2864. { by example:
  2865. movswl %si,%eax movswl %si,%eax p
  2866. decl %eax addl %edx,%eax hp1
  2867. movw %ax,%si movw %ax,%si hp2
  2868. ->
  2869. movswl %si,%eax movswl %si,%eax p
  2870. decw %eax addw %edx,%eax hp1
  2871. movw %ax,%si movw %ax,%si hp2
  2872. }
  2873. DebugMsg(SPeepholeOptimization + 'MovOpMov2MovOp ('+
  2874. debug_op2str(taicpu(p).opcode)+debug_opsize2str(taicpu(p).opsize)+' '+
  2875. debug_op2str(taicpu(hp1).opcode)+debug_opsize2str(taicpu(hp1).opsize)+' '+
  2876. debug_op2str(taicpu(hp2).opcode)+debug_opsize2str(taicpu(hp2).opsize)+')',p);
  2877. { limit size of constants as well to avoid assembler errors, but
  2878. check opsize to avoid overflow when left shifting the 1 }
  2879. if (taicpu(p).oper[0]^.typ=top_const) and (topsize2memsize[taicpu(hp2).opsize]<=63) then
  2880. taicpu(p).oper[0]^.val:=taicpu(p).oper[0]^.val and ((qword(1) shl topsize2memsize[taicpu(hp2).opsize])-1);
  2881. {$ifdef x86_64}
  2882. { Be careful of, for example:
  2883. movl %reg1,%reg2
  2884. addl %reg3,%reg2
  2885. movq %reg2,%reg4
  2886. This will cause problems if the upper 32-bits of %reg3 or %reg4 are non-zero
  2887. }
  2888. if (taicpu(hp1).opsize = S_L) and (taicpu(hp2).opsize = S_Q) then
  2889. begin
  2890. taicpu(hp2).changeopsize(S_L);
  2891. setsubreg(taicpu(hp2).oper[0]^.reg, R_SUBD);
  2892. setsubreg(taicpu(hp2).oper[1]^.reg, R_SUBD);
  2893. end;
  2894. {$endif x86_64}
  2895. taicpu(hp1).changeopsize(taicpu(hp2).opsize);
  2896. taicpu(p).changeopsize(taicpu(hp2).opsize);
  2897. if taicpu(p).oper[0]^.typ=top_reg then
  2898. setsubreg(taicpu(p).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  2899. taicpu(p).loadoper(1, taicpu(hp2).oper[1]^);
  2900. AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp1,usedregs);
  2901. {
  2902. ->
  2903. movswl %si,%eax movswl %si,%eax p
  2904. decw %si addw %dx,%si hp1
  2905. movw %ax,%si movw %ax,%si hp2
  2906. }
  2907. case taicpu(hp1).ops of
  2908. 1:
  2909. begin
  2910. taicpu(hp1).loadoper(0, taicpu(hp2).oper[1]^);
  2911. if taicpu(hp1).oper[0]^.typ=top_reg then
  2912. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  2913. end;
  2914. 2:
  2915. begin
  2916. taicpu(hp1).loadoper(1, taicpu(hp2).oper[1]^);
  2917. if (taicpu(hp1).oper[0]^.typ=top_reg) and
  2918. (taicpu(hp1).opcode<>A_SHL) and
  2919. (taicpu(hp1).opcode<>A_SHR) and
  2920. (taicpu(hp1).opcode<>A_SAR) then
  2921. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  2922. end;
  2923. else
  2924. internalerror(2018111801);
  2925. end;
  2926. {
  2927. ->
  2928. decw %si addw %dx,%si p
  2929. }
  2930. RemoveInstruction(hp2);
  2931. end;
  2932. end;
  2933. end;
  2934. if MatchInstruction(hp1,A_BTS,A_BTR,[Taicpu(p).opsize]) and
  2935. GetNextInstruction(hp1, hp2) and
  2936. MatchInstruction(hp2,A_OR,[Taicpu(p).opsize]) and
  2937. MatchOperand(Taicpu(p).oper[0]^,0) and
  2938. (Taicpu(p).oper[1]^.typ = top_reg) and
  2939. MatchOperand(Taicpu(p).oper[1]^,Taicpu(hp1).oper[1]^) and
  2940. MatchOperand(Taicpu(p).oper[1]^,Taicpu(hp2).oper[1]^) then
  2941. { mov reg1,0
  2942. bts reg1,operand1 --> mov reg1,operand2
  2943. or reg1,operand2 bts reg1,operand1}
  2944. begin
  2945. Taicpu(hp2).opcode:=A_MOV;
  2946. asml.remove(hp1);
  2947. insertllitem(hp2,hp2.next,hp1);
  2948. RemoveCurrentp(p, hp1);
  2949. Result:=true;
  2950. exit;
  2951. end;
  2952. {$ifdef x86_64}
  2953. { Convert:
  2954. movq x(ref),%reg64
  2955. shrq y,%reg64
  2956. To:
  2957. movq x+4(ref),%reg32
  2958. shrq y-32,%reg32 (Remove if y = 32)
  2959. }
  2960. if (taicpu(p).opsize = S_Q) and
  2961. (taicpu(p).oper[0]^.typ = top_ref) and { Second operand will be a register }
  2962. (taicpu(p).oper[0]^.ref^.offset <= $7FFFFFFB) and
  2963. MatchInstruction(hp1, A_SHR, [taicpu(p).opsize]) and
  2964. MatchOpType(taicpu(hp1), top_const, top_reg) and
  2965. (taicpu(hp1).oper[0]^.val >= 32) and
  2966. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  2967. begin
  2968. RegName1 := debug_regname(taicpu(hp1).oper[1]^.reg);
  2969. PreMessage := 'movq ' + debug_operstr(taicpu(p).oper[0]^) + ',' + RegName1 + '; ' +
  2970. 'shrq $' + debug_tostr(taicpu(hp1).oper[0]^.val) + ',' + RegName1 + ' -> movl ';
  2971. { Convert to 32-bit }
  2972. setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
  2973. taicpu(p).opsize := S_L;
  2974. Inc(taicpu(p).oper[0]^.ref^.offset, 4);
  2975. PreMessage := PreMessage + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg);
  2976. if (taicpu(hp1).oper[0]^.val = 32) then
  2977. begin
  2978. DebugMsg(SPeepholeOptimization + PreMessage + ' (MovShr2Mov)', p);
  2979. RemoveInstruction(hp1);
  2980. end
  2981. else
  2982. begin
  2983. { This will potentially open up more arithmetic operations since
  2984. the peephole optimizer now has a big hint that only the lower
  2985. 32 bits are currently in use (and opcodes are smaller in size) }
  2986. setsubreg(taicpu(hp1).oper[1]^.reg, R_SUBD);
  2987. taicpu(hp1).opsize := S_L;
  2988. Dec(taicpu(hp1).oper[0]^.val, 32);
  2989. DebugMsg(SPeepholeOptimization + PreMessage +
  2990. '; shrl $' + debug_tostr(taicpu(hp1).oper[0]^.val) + ',' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' (MovShr2MovShr)', p);
  2991. end;
  2992. Result := True;
  2993. Exit;
  2994. end;
  2995. {$endif x86_64}
  2996. end;
  2997. function TX86AsmOptimizer.OptPass1MOVXX(var p : tai) : boolean;
  2998. var
  2999. hp1 : tai;
  3000. begin
  3001. Result:=false;
  3002. if taicpu(p).ops <> 2 then
  3003. exit;
  3004. if GetNextInstruction(p,hp1) and
  3005. MatchInstruction(hp1,taicpu(p).opcode,[taicpu(p).opsize]) and
  3006. (taicpu(hp1).ops = 2) then
  3007. begin
  3008. if (taicpu(hp1).oper[0]^.typ = taicpu(p).oper[1]^.typ) and
  3009. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[0]^.typ) then
  3010. { movXX reg1, mem1 or movXX mem1, reg1
  3011. movXX mem2, reg2 movXX reg2, mem2}
  3012. begin
  3013. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) then
  3014. { movXX reg1, mem1 or movXX mem1, reg1
  3015. movXX mem2, reg1 movXX reg2, mem1}
  3016. begin
  3017. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  3018. begin
  3019. { Removes the second statement from
  3020. movXX reg1, mem1/reg2
  3021. movXX mem1/reg2, reg1
  3022. }
  3023. if taicpu(p).oper[0]^.typ=top_reg then
  3024. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  3025. { Removes the second statement from
  3026. movXX mem1/reg1, reg2
  3027. movXX reg2, mem1/reg1
  3028. }
  3029. if (taicpu(p).oper[1]^.typ=top_reg) and
  3030. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,UsedRegs)) then
  3031. begin
  3032. DebugMsg(SPeepholeOptimization + 'MovXXMovXX2Nop 1 done',p);
  3033. RemoveInstruction(hp1);
  3034. RemoveCurrentp(p); { p will now be equal to the instruction that follows what was hp1 }
  3035. end
  3036. else
  3037. begin
  3038. DebugMsg(SPeepholeOptimization + 'MovXXMovXX2MoVXX 1 done',p);
  3039. RemoveInstruction(hp1);
  3040. end;
  3041. Result:=true;
  3042. exit;
  3043. end
  3044. end;
  3045. end;
  3046. end;
  3047. end;
  3048. function TX86AsmOptimizer.OptPass1OP(var p : tai) : boolean;
  3049. var
  3050. hp1 : tai;
  3051. begin
  3052. result:=false;
  3053. { replace
  3054. <Op>X %mreg1,%mreg2 // Op in [ADD,MUL]
  3055. MovX %mreg2,%mreg1
  3056. dealloc %mreg2
  3057. by
  3058. <Op>X %mreg2,%mreg1
  3059. ?
  3060. }
  3061. if GetNextInstruction(p,hp1) and
  3062. { we mix single and double opperations here because we assume that the compiler
  3063. generates vmovapd only after double operations and vmovaps only after single operations }
  3064. MatchInstruction(hp1,A_MOVAPD,A_MOVAPS,[S_NO]) and
  3065. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) and
  3066. MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^) and
  3067. (taicpu(p).oper[0]^.typ=top_reg) then
  3068. begin
  3069. TransferUsedRegs(TmpUsedRegs);
  3070. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  3071. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  3072. begin
  3073. taicpu(p).loadoper(0,taicpu(hp1).oper[0]^);
  3074. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  3075. DebugMsg(SPeepholeOptimization + 'OpMov2Op done',p);
  3076. RemoveInstruction(hp1);
  3077. result:=true;
  3078. end;
  3079. end;
  3080. end;
  3081. function TX86AsmOptimizer.OptPass1Test(var p: tai) : boolean;
  3082. var
  3083. hp1, p_label, p_dist, hp1_dist: tai;
  3084. JumpLabel, JumpLabel_dist: TAsmLabel;
  3085. begin
  3086. Result := False;
  3087. if (taicpu(p).oper[1]^.typ = top_reg) then
  3088. begin
  3089. if GetNextInstruction(p, hp1) and
  3090. MatchInstruction(hp1,A_MOV,[]) and
  3091. not RegInInstruction(taicpu(p).oper[1]^.reg, hp1) and
  3092. (
  3093. (taicpu(p).oper[0]^.typ <> top_reg) or
  3094. not RegInInstruction(taicpu(p).oper[0]^.reg, hp1)
  3095. ) then
  3096. begin
  3097. { If we have something like:
  3098. test %reg1,%reg1
  3099. mov 0,%reg2
  3100. And no registers are shared (the two %reg1's can be different, as
  3101. long as neither of them are also %reg2), move the MOV command to
  3102. before the comparison as this means it can be optimised without
  3103. worrying about the FLAGS register. (This combination is generated
  3104. by "J(c)Mov1JmpMov0 -> Set(~c)", among other things).
  3105. }
  3106. SwapMovCmp(p, hp1);
  3107. Result := True;
  3108. Exit;
  3109. end;
  3110. { Search for:
  3111. test %reg,%reg
  3112. j(c1) @lbl1
  3113. ...
  3114. @lbl:
  3115. test %reg,%reg (same register)
  3116. j(c2) @lbl2
  3117. If c2 is a subset of c1, change to:
  3118. test %reg,%reg
  3119. j(c1) @lbl2
  3120. (@lbl1 may become a dead label as a result)
  3121. }
  3122. if (taicpu(p).oper[0]^.typ = top_reg) and
  3123. (taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  3124. MatchInstruction(hp1, A_JCC, []) and
  3125. (taicpu(hp1).oper[0]^.typ = top_ref) then
  3126. begin
  3127. JumpLabel := TAsmLabel(taicpu(hp1).oper[0]^.ref^.symbol);
  3128. p_label := nil;
  3129. if Assigned(JumpLabel) then
  3130. p_label := getlabelwithsym(JumpLabel);
  3131. if Assigned(p_label) and
  3132. GetNextInstruction(p_label, p_dist) and
  3133. MatchInstruction(p_dist, A_TEST, []) and
  3134. { It's fine if the second test uses smaller sub-registers }
  3135. (taicpu(p_dist).opsize <= taicpu(p).opsize) and
  3136. MatchOpType(taicpu(p_dist), top_reg, top_reg) and
  3137. SuperRegistersEqual(taicpu(p_dist).oper[0]^.reg, taicpu(p).oper[0]^.reg) and
  3138. SuperRegistersEqual(taicpu(p_dist).oper[1]^.reg, taicpu(p).oper[1]^.reg) and
  3139. GetNextInstruction(p_dist, hp1_dist) and
  3140. MatchInstruction(hp1_dist, A_JCC, []) then
  3141. begin
  3142. JumpLabel_dist := TAsmLabel(taicpu(hp1_dist).oper[0]^.ref^.symbol);
  3143. if JumpLabel = JumpLabel_dist then
  3144. { This is an infinite loop }
  3145. Exit;
  3146. { Best optimisation when the second condition is a subset (or equal) to the first }
  3147. if condition_in(taicpu(hp1_dist).condition, taicpu(hp1).condition) then
  3148. begin
  3149. if Assigned(JumpLabel_dist) then
  3150. JumpLabel_dist.IncRefs;
  3151. if Assigned(JumpLabel) then
  3152. JumpLabel.DecRefs;
  3153. DebugMsg(SPeepholeOptimization + 'TEST/Jcc/@Lbl/TEST/Jcc -> TEST/Jcc, redirecting first jump', hp1);
  3154. taicpu(hp1).loadref(0, taicpu(hp1_dist).oper[0]^.ref^);
  3155. Result := True;
  3156. Exit;
  3157. end;
  3158. end;
  3159. end;
  3160. end;
  3161. end;
  3162. function TX86AsmOptimizer.OptPass1Add(var p : tai) : boolean;
  3163. var
  3164. hp1 : tai;
  3165. begin
  3166. result:=false;
  3167. { replace
  3168. addX const,%reg1
  3169. leaX (%reg1,%reg1,Y),%reg2 // Base or index might not be equal to reg1
  3170. dealloc %reg1
  3171. by
  3172. leaX const+const*Y(%reg1,%reg1,Y),%reg2
  3173. }
  3174. if MatchOpType(taicpu(p),top_const,top_reg) and
  3175. GetNextInstruction(p,hp1) and
  3176. MatchInstruction(hp1,A_LEA,[taicpu(p).opsize]) and
  3177. ((taicpu(p).oper[1]^.reg=taicpu(hp1).oper[0]^.ref^.base) or
  3178. (taicpu(p).oper[1]^.reg=taicpu(hp1).oper[0]^.ref^.index)) then
  3179. begin
  3180. TransferUsedRegs(TmpUsedRegs);
  3181. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  3182. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  3183. begin
  3184. DebugMsg(SPeepholeOptimization + 'AddLea2Lea done',p);
  3185. if taicpu(p).oper[1]^.reg=taicpu(hp1).oper[0]^.ref^.base then
  3186. inc(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.val);
  3187. if taicpu(p).oper[1]^.reg=taicpu(hp1).oper[0]^.ref^.index then
  3188. inc(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.val*max(taicpu(hp1).oper[0]^.ref^.scalefactor,1));
  3189. RemoveCurrentP(p);
  3190. result:=true;
  3191. end;
  3192. end;
  3193. end;
  3194. function TX86AsmOptimizer.OptPass1LEA(var p : tai) : boolean;
  3195. var
  3196. hp1: tai;
  3197. ref: Integer;
  3198. saveref: treference;
  3199. TempReg: TRegister;
  3200. Multiple: TCGInt;
  3201. begin
  3202. Result:=false;
  3203. { removes seg register prefixes from LEA operations, as they
  3204. don't do anything}
  3205. taicpu(p).oper[0]^.ref^.Segment:=NR_NO;
  3206. { changes "lea (%reg1), %reg2" into "mov %reg1, %reg2" }
  3207. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  3208. (taicpu(p).oper[0]^.ref^.index = NR_NO) and
  3209. { do not mess with leas acessing the stack pointer }
  3210. (taicpu(p).oper[1]^.reg <> NR_STACK_POINTER_REG) and
  3211. (not(Assigned(taicpu(p).oper[0]^.ref^.Symbol))) then
  3212. begin
  3213. if (taicpu(p).oper[0]^.ref^.offset = 0) then
  3214. begin
  3215. if (taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) then
  3216. begin
  3217. hp1:=taicpu.op_reg_reg(A_MOV,taicpu(p).opsize,taicpu(p).oper[0]^.ref^.base,
  3218. taicpu(p).oper[1]^.reg);
  3219. InsertLLItem(p.previous,p.next, hp1);
  3220. DebugMsg(SPeepholeOptimization + 'Lea2Mov done',hp1);
  3221. p.free;
  3222. p:=hp1;
  3223. end
  3224. else
  3225. begin
  3226. DebugMsg(SPeepholeOptimization + 'Lea2Nop done',p);
  3227. RemoveCurrentP(p);
  3228. end;
  3229. Result:=true;
  3230. exit;
  3231. end
  3232. else if (
  3233. { continue to use lea to adjust the stack pointer,
  3234. it is the recommended way, but only if not optimizing for size }
  3235. (taicpu(p).oper[1]^.reg<>NR_STACK_POINTER_REG) or
  3236. (cs_opt_size in current_settings.optimizerswitches)
  3237. ) and
  3238. { If the flags register is in use, don't change the instruction
  3239. to an ADD otherwise this will scramble the flags. [Kit] }
  3240. not RegInUsedRegs(NR_DEFAULTFLAGS, UsedRegs) and
  3241. ConvertLEA(taicpu(p)) then
  3242. begin
  3243. Result:=true;
  3244. exit;
  3245. end;
  3246. end;
  3247. if GetNextInstruction(p,hp1) and
  3248. (hp1.typ=ait_instruction) then
  3249. begin
  3250. if MatchInstruction(hp1,A_MOV,[taicpu(p).opsize]) and
  3251. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) and
  3252. MatchOpType(Taicpu(hp1),top_reg,top_reg) and
  3253. (taicpu(p).oper[1]^.reg<>NR_STACK_POINTER_REG) then
  3254. begin
  3255. TransferUsedRegs(TmpUsedRegs);
  3256. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  3257. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  3258. begin
  3259. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  3260. DebugMsg(SPeepholeOptimization + 'LeaMov2Lea done',p);
  3261. RemoveInstruction(hp1);
  3262. result:=true;
  3263. exit;
  3264. end;
  3265. end;
  3266. { changes
  3267. lea <ref1>, reg1
  3268. <op> ...,<ref. with reg1>,...
  3269. to
  3270. <op> ...,<ref1>,... }
  3271. if (taicpu(p).oper[1]^.reg<>current_procinfo.framepointer) and
  3272. (taicpu(p).oper[1]^.reg<>NR_STACK_POINTER_REG) and
  3273. not(MatchInstruction(hp1,A_LEA,[])) then
  3274. begin
  3275. { find a reference which uses reg1 }
  3276. if (taicpu(hp1).ops>=1) and (taicpu(hp1).oper[0]^.typ=top_ref) and RegInOp(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[0]^) then
  3277. ref:=0
  3278. else if (taicpu(hp1).ops>=2) and (taicpu(hp1).oper[1]^.typ=top_ref) and RegInOp(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[1]^) then
  3279. ref:=1
  3280. else
  3281. ref:=-1;
  3282. if (ref<>-1) and
  3283. { reg1 must be either the base or the index }
  3284. ((taicpu(hp1).oper[ref]^.ref^.base=taicpu(p).oper[1]^.reg) xor (taicpu(hp1).oper[ref]^.ref^.index=taicpu(p).oper[1]^.reg)) then
  3285. begin
  3286. { reg1 can be removed from the reference }
  3287. saveref:=taicpu(hp1).oper[ref]^.ref^;
  3288. if taicpu(hp1).oper[ref]^.ref^.base=taicpu(p).oper[1]^.reg then
  3289. taicpu(hp1).oper[ref]^.ref^.base:=NR_NO
  3290. else if taicpu(hp1).oper[ref]^.ref^.index=taicpu(p).oper[1]^.reg then
  3291. taicpu(hp1).oper[ref]^.ref^.index:=NR_NO
  3292. else
  3293. Internalerror(2019111201);
  3294. { check if the can insert all data of the lea into the second instruction }
  3295. if ((taicpu(hp1).oper[ref]^.ref^.base=taicpu(p).oper[1]^.reg) or (taicpu(hp1).oper[ref]^.ref^.scalefactor <= 1)) and
  3296. ((taicpu(p).oper[0]^.ref^.base=NR_NO) or (taicpu(hp1).oper[ref]^.ref^.base=NR_NO)) and
  3297. ((taicpu(p).oper[0]^.ref^.index=NR_NO) or (taicpu(hp1).oper[ref]^.ref^.index=NR_NO)) and
  3298. ((taicpu(p).oper[0]^.ref^.symbol=nil) or (taicpu(hp1).oper[ref]^.ref^.symbol=nil)) and
  3299. ((taicpu(p).oper[0]^.ref^.relsymbol=nil) or (taicpu(hp1).oper[ref]^.ref^.relsymbol=nil)) and
  3300. ((taicpu(p).oper[0]^.ref^.scalefactor <= 1) or (taicpu(hp1).oper[ref]^.ref^.scalefactor <= 1)) and
  3301. (taicpu(p).oper[0]^.ref^.segment=NR_NO) and (taicpu(hp1).oper[ref]^.ref^.segment=NR_NO)
  3302. {$ifdef x86_64}
  3303. and (abs(taicpu(hp1).oper[ref]^.ref^.offset+taicpu(p).oper[0]^.ref^.offset)<=$7fffffff)
  3304. and (((taicpu(p).oper[0]^.ref^.base<>NR_RIP) and (taicpu(p).oper[0]^.ref^.index<>NR_RIP)) or
  3305. ((taicpu(hp1).oper[ref]^.ref^.base=NR_NO) and (taicpu(hp1).oper[ref]^.ref^.index=NR_NO))
  3306. )
  3307. {$endif x86_64}
  3308. then
  3309. begin
  3310. { reg1 might not used by the second instruction after it is remove from the reference }
  3311. if not(RegInInstruction(taicpu(p).oper[1]^.reg,taicpu(hp1))) then
  3312. begin
  3313. TransferUsedRegs(TmpUsedRegs);
  3314. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  3315. { reg1 is not updated so it might not be used afterwards }
  3316. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  3317. begin
  3318. DebugMsg(SPeepholeOptimization + 'LeaOp2Op done',p);
  3319. if taicpu(p).oper[0]^.ref^.base<>NR_NO then
  3320. taicpu(hp1).oper[ref]^.ref^.base:=taicpu(p).oper[0]^.ref^.base;
  3321. if taicpu(p).oper[0]^.ref^.index<>NR_NO then
  3322. taicpu(hp1).oper[ref]^.ref^.index:=taicpu(p).oper[0]^.ref^.index;
  3323. if taicpu(p).oper[0]^.ref^.symbol<>nil then
  3324. taicpu(hp1).oper[ref]^.ref^.symbol:=taicpu(p).oper[0]^.ref^.symbol;
  3325. if taicpu(p).oper[0]^.ref^.relsymbol<>nil then
  3326. taicpu(hp1).oper[ref]^.ref^.relsymbol:=taicpu(p).oper[0]^.ref^.relsymbol;
  3327. if taicpu(p).oper[0]^.ref^.scalefactor > 1 then
  3328. taicpu(hp1).oper[ref]^.ref^.scalefactor:=taicpu(p).oper[0]^.ref^.scalefactor;
  3329. inc(taicpu(hp1).oper[ref]^.ref^.offset,taicpu(p).oper[0]^.ref^.offset);
  3330. RemoveCurrentP(p, hp1);
  3331. result:=true;
  3332. exit;
  3333. end
  3334. end;
  3335. end;
  3336. { recover }
  3337. taicpu(hp1).oper[ref]^.ref^:=saveref;
  3338. end;
  3339. end;
  3340. end;
  3341. { for now, we do not mess with the stack pointer, thought it might be usefull to remove
  3342. unneeded lea sequences on the stack pointer, it needs to be tested in detail }
  3343. if (taicpu(p).oper[1]^.reg <> NR_STACK_POINTER_REG) and
  3344. GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[1]^.reg) then
  3345. begin
  3346. { Check common LEA/LEA conditions }
  3347. if MatchInstruction(hp1,A_LEA,[taicpu(p).opsize]) and
  3348. (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg) and
  3349. (taicpu(p).oper[0]^.ref^.relsymbol = nil) and
  3350. (taicpu(p).oper[0]^.ref^.segment = NR_NO) and
  3351. (taicpu(p).oper[0]^.ref^.symbol = nil) and
  3352. (taicpu(hp1).oper[0]^.ref^.relsymbol = nil) and
  3353. (taicpu(hp1).oper[0]^.ref^.segment = NR_NO) and
  3354. (taicpu(hp1).oper[0]^.ref^.symbol = nil) and
  3355. (
  3356. (taicpu(p).oper[0]^.ref^.base = NR_NO) or { Don't call RegModifiedBetween unnecessarily }
  3357. not(RegModifiedBetween(taicpu(p).oper[0]^.ref^.base,p,hp1))
  3358. ) and (
  3359. (taicpu(p).oper[0]^.ref^.index = taicpu(p).oper[0]^.ref^.base) or { Don't call RegModifiedBetween unnecessarily }
  3360. (taicpu(p).oper[0]^.ref^.index = NR_NO) or
  3361. not(RegModifiedBetween(taicpu(p).oper[0]^.ref^.index,p,hp1))
  3362. ) then
  3363. begin
  3364. { changes
  3365. lea (regX,scale), reg1
  3366. lea offset(reg1,reg1), reg1
  3367. to
  3368. lea offset(regX,scale*2), reg1
  3369. and
  3370. lea (regX,scale1), reg1
  3371. lea offset(reg1,scale2), reg1
  3372. to
  3373. lea offset(regX,scale1*scale2), reg1
  3374. ... so long as the final scale does not exceed 8
  3375. (Similarly, allow the first instruction to be "lea (regX,regX),reg1")
  3376. }
  3377. if (taicpu(p).oper[0]^.ref^.offset = 0) and
  3378. (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) and
  3379. (
  3380. (
  3381. (taicpu(p).oper[0]^.ref^.base = NR_NO)
  3382. ) or (
  3383. (taicpu(p).oper[0]^.ref^.scalefactor <= 1) and
  3384. (
  3385. (taicpu(p).oper[0]^.ref^.base = taicpu(p).oper[0]^.ref^.index) and
  3386. not(RegUsedBetween(taicpu(p).oper[0]^.ref^.index, p, hp1))
  3387. )
  3388. )
  3389. ) and (
  3390. (
  3391. { lea (reg1,scale2), reg1 variant }
  3392. (taicpu(hp1).oper[0]^.ref^.base = NR_NO) and
  3393. (
  3394. (
  3395. (taicpu(p).oper[0]^.ref^.base = NR_NO) and
  3396. (taicpu(hp1).oper[0]^.ref^.scalefactor * taicpu(p).oper[0]^.ref^.scalefactor <= 8)
  3397. ) or (
  3398. { lea (regX,regX), reg1 variant }
  3399. (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  3400. (taicpu(hp1).oper[0]^.ref^.scalefactor <= 4)
  3401. )
  3402. )
  3403. ) or (
  3404. { lea (reg1,reg1), reg1 variant }
  3405. (taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) and
  3406. (taicpu(hp1).oper[0]^.ref^.scalefactor <= 1)
  3407. )
  3408. ) then
  3409. begin
  3410. DebugMsg(SPeepholeOptimization + 'LeaLea2Lea 2 done',p);
  3411. { Make everything homogeneous to make calculations easier }
  3412. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) then
  3413. begin
  3414. if taicpu(p).oper[0]^.ref^.index <> NR_NO then
  3415. { Convert lea (regX,regX),reg1 to lea (regX,2),reg1 }
  3416. taicpu(p).oper[0]^.ref^.scalefactor := 2
  3417. else
  3418. taicpu(p).oper[0]^.ref^.index := taicpu(p).oper[0]^.ref^.base;
  3419. taicpu(p).oper[0]^.ref^.base := NR_NO;
  3420. end;
  3421. if (taicpu(hp1).oper[0]^.ref^.base = NR_NO) then
  3422. begin
  3423. { Just to prevent miscalculations }
  3424. if (taicpu(hp1).oper[0]^.ref^.scalefactor = 0) then
  3425. taicpu(hp1).oper[0]^.ref^.scalefactor := taicpu(p).oper[0]^.ref^.scalefactor
  3426. else
  3427. taicpu(hp1).oper[0]^.ref^.scalefactor := taicpu(hp1).oper[0]^.ref^.scalefactor * taicpu(p).oper[0]^.ref^.scalefactor;
  3428. end
  3429. else
  3430. begin
  3431. taicpu(hp1).oper[0]^.ref^.base := NR_NO;
  3432. taicpu(hp1).oper[0]^.ref^.scalefactor := taicpu(p).oper[0]^.ref^.scalefactor * 2;
  3433. end;
  3434. taicpu(hp1).oper[0]^.ref^.index := taicpu(p).oper[0]^.ref^.index;
  3435. RemoveCurrentP(p);
  3436. result:=true;
  3437. exit;
  3438. end
  3439. { changes
  3440. lea offset1(regX), reg1
  3441. lea offset2(reg1), reg1
  3442. to
  3443. lea offset1+offset2(regX), reg1 }
  3444. else if
  3445. (
  3446. (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) and
  3447. (taicpu(p).oper[0]^.ref^.index = NR_NO)
  3448. ) or (
  3449. (taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) and
  3450. (taicpu(hp1).oper[0]^.ref^.scalefactor <= 1) and
  3451. (
  3452. (
  3453. (taicpu(p).oper[0]^.ref^.index = NR_NO) or
  3454. (taicpu(p).oper[0]^.ref^.base = NR_NO)
  3455. ) or (
  3456. (taicpu(p).oper[0]^.ref^.scalefactor <= 1) and
  3457. (
  3458. (taicpu(p).oper[0]^.ref^.index = NR_NO) or
  3459. (
  3460. (taicpu(p).oper[0]^.ref^.index = taicpu(p).oper[0]^.ref^.base) and
  3461. (
  3462. (taicpu(hp1).oper[0]^.ref^.index = NR_NO) or
  3463. (taicpu(hp1).oper[0]^.ref^.base = NR_NO)
  3464. )
  3465. )
  3466. )
  3467. )
  3468. )
  3469. ) then
  3470. begin
  3471. DebugMsg(SPeepholeOptimization + 'LeaLea2Lea 1 done',p);
  3472. if taicpu(hp1).oper[0]^.ref^.index=taicpu(p).oper[1]^.reg then
  3473. begin
  3474. taicpu(hp1).oper[0]^.ref^.index:=taicpu(p).oper[0]^.ref^.base;
  3475. inc(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.ref^.offset*max(taicpu(hp1).oper[0]^.ref^.scalefactor,1));
  3476. { if the register is used as index and base, we have to increase for base as well
  3477. and adapt base }
  3478. if taicpu(hp1).oper[0]^.ref^.base=taicpu(p).oper[1]^.reg then
  3479. begin
  3480. taicpu(hp1).oper[0]^.ref^.base:=taicpu(p).oper[0]^.ref^.base;
  3481. inc(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.ref^.offset);
  3482. end;
  3483. end
  3484. else
  3485. begin
  3486. inc(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.ref^.offset);
  3487. taicpu(hp1).oper[0]^.ref^.base:=taicpu(p).oper[0]^.ref^.base;
  3488. end;
  3489. if taicpu(p).oper[0]^.ref^.index<>NR_NO then
  3490. begin
  3491. taicpu(hp1).oper[0]^.ref^.base:=taicpu(hp1).oper[0]^.ref^.index;
  3492. taicpu(hp1).oper[0]^.ref^.index:=taicpu(p).oper[0]^.ref^.index;
  3493. taicpu(hp1).oper[0]^.ref^.scalefactor:=taicpu(p).oper[0]^.ref^.scalefactor;
  3494. end;
  3495. RemoveCurrentP(p);
  3496. result:=true;
  3497. exit;
  3498. end;
  3499. end;
  3500. { Change:
  3501. leal/q $x(%reg1),%reg2
  3502. ...
  3503. shll/q $y,%reg2
  3504. To:
  3505. leal/q $(x+2^y)(%reg1,2^y),%reg2 (if y <= 3)
  3506. }
  3507. if MatchInstruction(hp1, A_SHL, [taicpu(p).opsize]) and
  3508. MatchOpType(taicpu(hp1), top_const, top_reg) and
  3509. (taicpu(hp1).oper[0]^.val <= 3) then
  3510. begin
  3511. Multiple := 1 shl taicpu(hp1).oper[0]^.val;
  3512. TransferUsedRegs(TmpUsedRegs);
  3513. UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
  3514. TempReg := taicpu(hp1).oper[1]^.reg; { Store locally to reduce the number of dereferences }
  3515. if
  3516. { This allows the optimisation in some circumstances even if the lea instruction already has a scale factor
  3517. (this works even if scalefactor is zero) }
  3518. ((Multiple * taicpu(p).oper[0]^.ref^.scalefactor) <= 8) and
  3519. { Ensure offset doesn't go out of bounds }
  3520. (abs(taicpu(p).oper[0]^.ref^.offset * Multiple) <= $7FFFFFFF) and
  3521. not (RegInUsedRegs(NR_DEFAULTFLAGS,TmpUsedRegs)) and
  3522. MatchOperand(taicpu(p).oper[1]^, TempReg) and
  3523. (
  3524. (
  3525. not SuperRegistersEqual(taicpu(p).oper[0]^.ref^.base, TempReg) and
  3526. (
  3527. (taicpu(p).oper[0]^.ref^.index = NR_NO) or
  3528. (taicpu(p).oper[0]^.ref^.index = NR_INVALID) or
  3529. (
  3530. { Check for lea $x(%reg1,%reg1),%reg2 and treat as it it were lea $x(%reg1,2),%reg2 }
  3531. (taicpu(p).oper[0]^.ref^.index = taicpu(p).oper[0]^.ref^.base) and
  3532. (taicpu(p).oper[0]^.ref^.scalefactor <= 1)
  3533. )
  3534. )
  3535. ) or (
  3536. (
  3537. (taicpu(p).oper[0]^.ref^.base = NR_NO) or
  3538. (taicpu(p).oper[0]^.ref^.base = NR_INVALID)
  3539. ) and
  3540. not SuperRegistersEqual(taicpu(p).oper[0]^.ref^.index, TempReg)
  3541. )
  3542. ) then
  3543. begin
  3544. repeat
  3545. with taicpu(p).oper[0]^.ref^ do
  3546. begin
  3547. { Convert lea $x(%reg1,%reg1),%reg2 to lea $x(%reg1,2),%reg2 }
  3548. if index = base then
  3549. begin
  3550. if Multiple > 4 then
  3551. { Optimisation will no longer work because resultant
  3552. scale factor will exceed 8 }
  3553. Break;
  3554. base := NR_NO;
  3555. scalefactor := 2;
  3556. DebugMsg(SPeepholeOptimization + 'lea $x(%reg1,%reg1),%reg2 -> lea $x(%reg1,2),%reg2 for following optimisation', p);
  3557. end
  3558. else if (base <> NR_NO) and (base <> NR_INVALID) then
  3559. begin
  3560. { Scale factor only works on the index register }
  3561. index := base;
  3562. base := NR_NO;
  3563. end;
  3564. { For safety }
  3565. if scalefactor <= 1 then
  3566. begin
  3567. DebugMsg(SPeepholeOptimization + 'LeaShl2Lea 1', p);
  3568. scalefactor := Multiple;
  3569. end
  3570. else
  3571. begin
  3572. DebugMsg(SPeepholeOptimization + 'LeaShl2Lea 2', p);
  3573. scalefactor := scalefactor * Multiple;
  3574. end;
  3575. offset := offset * Multiple;
  3576. end;
  3577. RemoveInstruction(hp1);
  3578. Result := True;
  3579. Exit;
  3580. { This repeat..until loop exists for the benefit of Break }
  3581. until True;
  3582. end;
  3583. end;
  3584. end;
  3585. end;
  3586. function TX86AsmOptimizer.DoSubAddOpt(var p: tai): Boolean;
  3587. var
  3588. hp1 : tai;
  3589. begin
  3590. DoSubAddOpt := False;
  3591. if GetLastInstruction(p, hp1) and
  3592. (hp1.typ = ait_instruction) and
  3593. (taicpu(hp1).opsize = taicpu(p).opsize) then
  3594. case taicpu(hp1).opcode Of
  3595. A_DEC:
  3596. if (taicpu(hp1).oper[0]^.typ = top_reg) and
  3597. MatchOperand(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  3598. begin
  3599. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+1);
  3600. RemoveInstruction(hp1);
  3601. end;
  3602. A_SUB:
  3603. if MatchOpType(taicpu(hp1),top_const,top_reg) and
  3604. MatchOperand(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) then
  3605. begin
  3606. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+taicpu(hp1).oper[0]^.val);
  3607. RemoveInstruction(hp1);
  3608. end;
  3609. A_ADD:
  3610. begin
  3611. if MatchOpType(taicpu(hp1),top_const,top_reg) and
  3612. MatchOperand(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) then
  3613. begin
  3614. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  3615. RemoveInstruction(hp1);
  3616. if (taicpu(p).oper[0]^.val = 0) then
  3617. begin
  3618. hp1 := tai(p.next);
  3619. RemoveInstruction(p); { Note, the choice to not use RemoveCurrentp is deliberate }
  3620. if not GetLastInstruction(hp1, p) then
  3621. p := hp1;
  3622. DoSubAddOpt := True;
  3623. end
  3624. end;
  3625. end;
  3626. else
  3627. ;
  3628. end;
  3629. end;
  3630. function TX86AsmOptimizer.OptPass1Sub(var p : tai) : boolean;
  3631. {$ifdef i386}
  3632. var
  3633. hp1 : tai;
  3634. {$endif i386}
  3635. begin
  3636. Result:=false;
  3637. { * change "subl $2, %esp; pushw x" to "pushl x"}
  3638. { * change "sub/add const1, reg" or "dec reg" followed by
  3639. "sub const2, reg" to one "sub ..., reg" }
  3640. if MatchOpType(taicpu(p),top_const,top_reg) then
  3641. begin
  3642. {$ifdef i386}
  3643. if (taicpu(p).oper[0]^.val = 2) and
  3644. (taicpu(p).oper[1]^.reg = NR_ESP) and
  3645. { Don't do the sub/push optimization if the sub }
  3646. { comes from setting up the stack frame (JM) }
  3647. (not(GetLastInstruction(p,hp1)) or
  3648. not(MatchInstruction(hp1,A_MOV,[S_L]) and
  3649. MatchOperand(taicpu(hp1).oper[0]^,NR_ESP) and
  3650. MatchOperand(taicpu(hp1).oper[0]^,NR_EBP))) then
  3651. begin
  3652. hp1 := tai(p.next);
  3653. while Assigned(hp1) and
  3654. (tai(hp1).typ in [ait_instruction]+SkipInstr) and
  3655. not RegReadByInstruction(NR_ESP,hp1) and
  3656. not RegModifiedByInstruction(NR_ESP,hp1) do
  3657. hp1 := tai(hp1.next);
  3658. if Assigned(hp1) and
  3659. MatchInstruction(hp1,A_PUSH,[S_W]) then
  3660. begin
  3661. taicpu(hp1).changeopsize(S_L);
  3662. if taicpu(hp1).oper[0]^.typ=top_reg then
  3663. setsubreg(taicpu(hp1).oper[0]^.reg,R_SUBWHOLE);
  3664. hp1 := tai(p.next);
  3665. RemoveCurrentp(p, hp1);
  3666. Result:=true;
  3667. exit;
  3668. end;
  3669. end;
  3670. {$endif i386}
  3671. if DoSubAddOpt(p) then
  3672. Result:=true;
  3673. end;
  3674. end;
  3675. function TX86AsmOptimizer.OptPass1SHLSAL(var p : tai) : boolean;
  3676. var
  3677. TmpBool1,TmpBool2 : Boolean;
  3678. tmpref : treference;
  3679. hp1,hp2: tai;
  3680. mask: tcgint;
  3681. begin
  3682. Result:=false;
  3683. { All these optimisations work on "shl/sal const,%reg" }
  3684. if not MatchOpType(taicpu(p),top_const,top_reg) then
  3685. Exit;
  3686. if (taicpu(p).opsize in [S_L{$ifdef x86_64},S_Q{$endif x86_64}]) and
  3687. (taicpu(p).oper[0]^.val <= 3) then
  3688. { Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement }
  3689. begin
  3690. { should we check the next instruction? }
  3691. TmpBool1 := True;
  3692. { have we found an add/sub which could be
  3693. integrated in the lea? }
  3694. TmpBool2 := False;
  3695. reference_reset(tmpref,2,[]);
  3696. TmpRef.index := taicpu(p).oper[1]^.reg;
  3697. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  3698. while TmpBool1 and
  3699. GetNextInstruction(p, hp1) and
  3700. (tai(hp1).typ = ait_instruction) and
  3701. ((((taicpu(hp1).opcode = A_ADD) or
  3702. (taicpu(hp1).opcode = A_SUB)) and
  3703. (taicpu(hp1).oper[1]^.typ = Top_Reg) and
  3704. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg)) or
  3705. (((taicpu(hp1).opcode = A_INC) or
  3706. (taicpu(hp1).opcode = A_DEC)) and
  3707. (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  3708. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg)) or
  3709. ((taicpu(hp1).opcode = A_LEA) and
  3710. (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) and
  3711. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg))) and
  3712. (not GetNextInstruction(hp1,hp2) or
  3713. not instrReadsFlags(hp2)) Do
  3714. begin
  3715. TmpBool1 := False;
  3716. if taicpu(hp1).opcode=A_LEA then
  3717. begin
  3718. if (TmpRef.base = NR_NO) and
  3719. (taicpu(hp1).oper[0]^.ref^.symbol=nil) and
  3720. (taicpu(hp1).oper[0]^.ref^.relsymbol=nil) and
  3721. (taicpu(hp1).oper[0]^.ref^.segment=NR_NO) and
  3722. ((taicpu(hp1).oper[0]^.ref^.scalefactor=0) or
  3723. (taicpu(hp1).oper[0]^.ref^.scalefactor*tmpref.scalefactor<=8)) then
  3724. begin
  3725. TmpBool1 := True;
  3726. TmpBool2 := True;
  3727. inc(TmpRef.offset, taicpu(hp1).oper[0]^.ref^.offset);
  3728. if taicpu(hp1).oper[0]^.ref^.scalefactor<>0 then
  3729. tmpref.scalefactor:=tmpref.scalefactor*taicpu(hp1).oper[0]^.ref^.scalefactor;
  3730. TmpRef.base := taicpu(hp1).oper[0]^.ref^.base;
  3731. RemoveInstruction(hp1);
  3732. end
  3733. end
  3734. else if (taicpu(hp1).oper[0]^.typ = Top_Const) then
  3735. begin
  3736. TmpBool1 := True;
  3737. TmpBool2 := True;
  3738. case taicpu(hp1).opcode of
  3739. A_ADD:
  3740. inc(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  3741. A_SUB:
  3742. dec(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  3743. else
  3744. internalerror(2019050536);
  3745. end;
  3746. RemoveInstruction(hp1);
  3747. end
  3748. else
  3749. if (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  3750. (((taicpu(hp1).opcode = A_ADD) and
  3751. (TmpRef.base = NR_NO)) or
  3752. (taicpu(hp1).opcode = A_INC) or
  3753. (taicpu(hp1).opcode = A_DEC)) then
  3754. begin
  3755. TmpBool1 := True;
  3756. TmpBool2 := True;
  3757. case taicpu(hp1).opcode of
  3758. A_ADD:
  3759. TmpRef.base := taicpu(hp1).oper[0]^.reg;
  3760. A_INC:
  3761. inc(TmpRef.offset);
  3762. A_DEC:
  3763. dec(TmpRef.offset);
  3764. else
  3765. internalerror(2019050535);
  3766. end;
  3767. RemoveInstruction(hp1);
  3768. end;
  3769. end;
  3770. if TmpBool2
  3771. {$ifndef x86_64}
  3772. or
  3773. ((current_settings.optimizecputype < cpu_Pentium2) and
  3774. (taicpu(p).oper[0]^.val <= 3) and
  3775. not(cs_opt_size in current_settings.optimizerswitches))
  3776. {$endif x86_64}
  3777. then
  3778. begin
  3779. if not(TmpBool2) and
  3780. (taicpu(p).oper[0]^.val=1) then
  3781. begin
  3782. hp1:=taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  3783. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg)
  3784. end
  3785. else
  3786. hp1:=taicpu.op_ref_reg(A_LEA, taicpu(p).opsize, TmpRef,
  3787. taicpu(p).oper[1]^.reg);
  3788. DebugMsg(SPeepholeOptimization + 'ShlAddLeaSubIncDec2Lea',p);
  3789. InsertLLItem(p.previous, p.next, hp1);
  3790. p.free;
  3791. p := hp1;
  3792. end;
  3793. end
  3794. {$ifndef x86_64}
  3795. else if (current_settings.optimizecputype < cpu_Pentium2) then
  3796. begin
  3797. { changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  3798. but faster on a 486, and Tairable in both U and V pipes on the Pentium
  3799. (unlike shl, which is only Tairable in the U pipe) }
  3800. if taicpu(p).oper[0]^.val=1 then
  3801. begin
  3802. hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  3803. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
  3804. InsertLLItem(p.previous, p.next, hp1);
  3805. p.free;
  3806. p := hp1;
  3807. end
  3808. { changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  3809. "shl $3, %reg" to "lea (,%reg,8), %reg }
  3810. else if (taicpu(p).opsize = S_L) and
  3811. (taicpu(p).oper[0]^.val<= 3) then
  3812. begin
  3813. reference_reset(tmpref,2,[]);
  3814. TmpRef.index := taicpu(p).oper[1]^.reg;
  3815. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  3816. hp1 := taicpu.Op_ref_reg(A_LEA,S_L,TmpRef, taicpu(p).oper[1]^.reg);
  3817. InsertLLItem(p.previous, p.next, hp1);
  3818. p.free;
  3819. p := hp1;
  3820. end;
  3821. end
  3822. {$endif x86_64}
  3823. else if
  3824. GetNextInstruction(p, hp1) and (hp1.typ = ait_instruction) and MatchOpType(taicpu(hp1), top_const, top_reg) and
  3825. (
  3826. (
  3827. MatchInstruction(hp1, A_AND, [taicpu(p).opsize]) and
  3828. SetAndTest(hp1, hp2)
  3829. {$ifdef x86_64}
  3830. ) or
  3831. (
  3832. MatchInstruction(hp1, A_MOV, [taicpu(p).opsize]) and
  3833. GetNextInstruction(hp1, hp2) and
  3834. MatchInstruction(hp2, A_AND, [taicpu(p).opsize]) and
  3835. MatchOpType(taicpu(hp2), top_reg, top_reg) and
  3836. (taicpu(hp1).oper[1]^.reg = taicpu(hp2).oper[0]^.reg)
  3837. {$endif x86_64}
  3838. )
  3839. ) and
  3840. (taicpu(p).oper[1]^.reg = taicpu(hp2).oper[1]^.reg) then
  3841. begin
  3842. { Change:
  3843. shl x, %reg1
  3844. mov -(1<<x), %reg2
  3845. and %reg2, %reg1
  3846. Or:
  3847. shl x, %reg1
  3848. and -(1<<x), %reg1
  3849. To just:
  3850. shl x, %reg1
  3851. Since the and operation only zeroes bits that are already zero from the shl operation
  3852. }
  3853. case taicpu(p).oper[0]^.val of
  3854. 8:
  3855. mask:=$FFFFFFFFFFFFFF00;
  3856. 16:
  3857. mask:=$FFFFFFFFFFFF0000;
  3858. 32:
  3859. mask:=$FFFFFFFF00000000;
  3860. 63:
  3861. { Constant pre-calculated to prevent overflow errors with Int64 }
  3862. mask:=$8000000000000000;
  3863. else
  3864. begin
  3865. if taicpu(p).oper[0]^.val >= 64 then
  3866. { Shouldn't happen realistically, since the register
  3867. is guaranteed to be set to zero at this point }
  3868. mask := 0
  3869. else
  3870. mask := -(Int64(1 shl taicpu(p).oper[0]^.val));
  3871. end;
  3872. end;
  3873. if taicpu(hp1).oper[0]^.val = mask then
  3874. begin
  3875. { Everything checks out, perform the optimisation, as long as
  3876. the FLAGS register isn't being used}
  3877. TransferUsedRegs(TmpUsedRegs);
  3878. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  3879. {$ifdef x86_64}
  3880. if (hp1 <> hp2) then
  3881. begin
  3882. { "shl/mov/and" version }
  3883. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  3884. { Don't do the optimisation if the FLAGS register is in use }
  3885. if not(RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp2, TmpUsedRegs)) then
  3886. begin
  3887. DebugMsg(SPeepholeOptimization + 'ShlMovAnd2Shl', p);
  3888. { Don't remove the 'mov' instruction if its register is used elsewhere }
  3889. if not(RegUsedAfterInstruction(taicpu(hp1).oper[1]^.reg, hp2, TmpUsedRegs)) then
  3890. begin
  3891. RemoveInstruction(hp1);
  3892. Result := True;
  3893. end;
  3894. { Only set Result to True if the 'mov' instruction was removed }
  3895. RemoveInstruction(hp2);
  3896. end;
  3897. end
  3898. else
  3899. {$endif x86_64}
  3900. begin
  3901. { "shl/and" version }
  3902. { Don't do the optimisation if the FLAGS register is in use }
  3903. if not(RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs)) then
  3904. begin
  3905. DebugMsg(SPeepholeOptimization + 'ShlAnd2Shl', p);
  3906. RemoveInstruction(hp1);
  3907. Result := True;
  3908. end;
  3909. end;
  3910. Exit;
  3911. end
  3912. else {$ifdef x86_64}if (hp1 = hp2) then{$endif x86_64}
  3913. begin
  3914. { Even if the mask doesn't allow for its removal, we might be
  3915. able to optimise the mask for the "shl/and" version, which
  3916. may permit other peephole optimisations }
  3917. {$ifdef DEBUG_AOPTCPU}
  3918. mask := taicpu(hp1).oper[0]^.val and mask;
  3919. if taicpu(hp1).oper[0]^.val <> mask then
  3920. begin
  3921. DebugMsg(
  3922. SPeepholeOptimization +
  3923. 'Changed mask from $' + debug_tostr(taicpu(hp1).oper[0]^.val) +
  3924. ' to $' + debug_tostr(mask) +
  3925. 'based on previous instruction (ShlAnd2ShlAnd)', hp1);
  3926. taicpu(hp1).oper[0]^.val := mask;
  3927. end;
  3928. {$else DEBUG_AOPTCPU}
  3929. { If debugging is off, just set the operand even if it's the same }
  3930. taicpu(hp1).oper[0]^.val := taicpu(hp1).oper[0]^.val and mask;
  3931. {$endif DEBUG_AOPTCPU}
  3932. end;
  3933. end;
  3934. end;
  3935. function TX86AsmOptimizer.CheckMemoryWrite(var first_mov, second_mov: taicpu): Boolean;
  3936. var
  3937. CurrentRef: TReference;
  3938. FullReg: TRegister;
  3939. hp1, hp2: tai;
  3940. begin
  3941. Result := False;
  3942. if (first_mov.opsize <> S_B) or (second_mov.opsize <> S_B) then
  3943. Exit;
  3944. { We assume you've checked if the operand is actually a reference by
  3945. this point. If it isn't, you'll most likely get an access violation }
  3946. CurrentRef := first_mov.oper[1]^.ref^;
  3947. { Memory must be aligned }
  3948. if (CurrentRef.offset mod 4) <> 0 then
  3949. Exit;
  3950. Inc(CurrentRef.offset);
  3951. CurrentRef.alignment := 1; { Otherwise references_equal will return False }
  3952. if MatchOperand(second_mov.oper[0]^, 0) and
  3953. references_equal(second_mov.oper[1]^.ref^, CurrentRef) and
  3954. GetNextInstruction(second_mov, hp1) and
  3955. (hp1.typ = ait_instruction) and
  3956. (taicpu(hp1).opcode = A_MOV) and
  3957. MatchOpType(taicpu(hp1), top_const, top_ref) and
  3958. (taicpu(hp1).oper[0]^.val = 0) then
  3959. begin
  3960. Inc(CurrentRef.offset);
  3961. CurrentRef.alignment := taicpu(hp1).oper[1]^.ref^.alignment; { Otherwise references_equal might return False }
  3962. FullReg := newreg(R_INTREGISTER,getsupreg(first_mov.oper[0]^.reg), R_SUBD);
  3963. if references_equal(taicpu(hp1).oper[1]^.ref^, CurrentRef) then
  3964. begin
  3965. case taicpu(hp1).opsize of
  3966. S_B:
  3967. if GetNextInstruction(hp1, hp2) and
  3968. MatchInstruction(taicpu(hp2), A_MOV, [S_B]) and
  3969. MatchOpType(taicpu(hp2), top_const, top_ref) and
  3970. (taicpu(hp2).oper[0]^.val = 0) then
  3971. begin
  3972. Inc(CurrentRef.offset);
  3973. CurrentRef.alignment := 1; { Otherwise references_equal will return False }
  3974. if references_equal(taicpu(hp2).oper[1]^.ref^, CurrentRef) and
  3975. (taicpu(hp2).opsize = S_B) then
  3976. begin
  3977. RemoveInstruction(hp1);
  3978. RemoveInstruction(hp2);
  3979. first_mov.opsize := S_L;
  3980. if first_mov.oper[0]^.typ = top_reg then
  3981. begin
  3982. DebugMsg(SPeepholeOptimization + 'MOVb/MOVb/MOVb/MOVb -> MOVZX/MOVl', first_mov);
  3983. { Reuse second_mov as a MOVZX instruction }
  3984. second_mov.opcode := A_MOVZX;
  3985. second_mov.opsize := S_BL;
  3986. second_mov.loadreg(0, first_mov.oper[0]^.reg);
  3987. second_mov.loadreg(1, FullReg);
  3988. first_mov.oper[0]^.reg := FullReg;
  3989. asml.Remove(second_mov);
  3990. asml.InsertBefore(second_mov, first_mov);
  3991. end
  3992. else
  3993. { It's a value }
  3994. begin
  3995. DebugMsg(SPeepholeOptimization + 'MOVb/MOVb/MOVb/MOVb -> MOVl', first_mov);
  3996. RemoveInstruction(second_mov);
  3997. end;
  3998. Result := True;
  3999. Exit;
  4000. end;
  4001. end;
  4002. S_W:
  4003. begin
  4004. RemoveInstruction(hp1);
  4005. first_mov.opsize := S_L;
  4006. if first_mov.oper[0]^.typ = top_reg then
  4007. begin
  4008. DebugMsg(SPeepholeOptimization + 'MOVb/MOVb/MOVw -> MOVZX/MOVl', first_mov);
  4009. { Reuse second_mov as a MOVZX instruction }
  4010. second_mov.opcode := A_MOVZX;
  4011. second_mov.opsize := S_BL;
  4012. second_mov.loadreg(0, first_mov.oper[0]^.reg);
  4013. second_mov.loadreg(1, FullReg);
  4014. first_mov.oper[0]^.reg := FullReg;
  4015. asml.Remove(second_mov);
  4016. asml.InsertBefore(second_mov, first_mov);
  4017. end
  4018. else
  4019. { It's a value }
  4020. begin
  4021. DebugMsg(SPeepholeOptimization + 'MOVb/MOVb/MOVw -> MOVl', first_mov);
  4022. RemoveInstruction(second_mov);
  4023. end;
  4024. Result := True;
  4025. Exit;
  4026. end;
  4027. else
  4028. ;
  4029. end;
  4030. end;
  4031. end;
  4032. end;
  4033. function TX86AsmOptimizer.OptPass1FSTP(var p: tai): boolean;
  4034. { returns true if a "continue" should be done after this optimization }
  4035. var
  4036. hp1, hp2: tai;
  4037. begin
  4038. Result := false;
  4039. if MatchOpType(taicpu(p),top_ref) and
  4040. GetNextInstruction(p, hp1) and
  4041. (hp1.typ = ait_instruction) and
  4042. (((taicpu(hp1).opcode = A_FLD) and
  4043. (taicpu(p).opcode = A_FSTP)) or
  4044. ((taicpu(p).opcode = A_FISTP) and
  4045. (taicpu(hp1).opcode = A_FILD))) and
  4046. MatchOpType(taicpu(hp1),top_ref) and
  4047. (taicpu(hp1).opsize = taicpu(p).opsize) and
  4048. RefsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  4049. begin
  4050. { replacing fstp f;fld f by fst f is only valid for extended because of rounding or if fastmath is on }
  4051. if ((taicpu(p).opsize=S_FX) or (cs_opt_fastmath in current_settings.optimizerswitches)) and
  4052. GetNextInstruction(hp1, hp2) and
  4053. (hp2.typ = ait_instruction) and
  4054. IsExitCode(hp2) and
  4055. (taicpu(p).oper[0]^.ref^.base = current_procinfo.FramePointer) and
  4056. not(assigned(current_procinfo.procdef.funcretsym) and
  4057. (taicpu(p).oper[0]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  4058. (taicpu(p).oper[0]^.ref^.index = NR_NO) then
  4059. begin
  4060. RemoveInstruction(hp1);
  4061. RemoveCurrentP(p, hp2);
  4062. RemoveLastDeallocForFuncRes(p);
  4063. Result := true;
  4064. end
  4065. else
  4066. { we can do this only in fast math mode as fstp is rounding ...
  4067. ... still disabled as it breaks the compiler and/or rtl }
  4068. if ({ (cs_opt_fastmath in current_settings.optimizerswitches) or }
  4069. { ... or if another fstp equal to the first one follows }
  4070. (GetNextInstruction(hp1,hp2) and
  4071. (hp2.typ = ait_instruction) and
  4072. (taicpu(p).opcode=taicpu(hp2).opcode) and
  4073. (taicpu(p).opsize=taicpu(hp2).opsize))
  4074. ) and
  4075. { fst can't store an extended/comp value }
  4076. (taicpu(p).opsize <> S_FX) and
  4077. (taicpu(p).opsize <> S_IQ) then
  4078. begin
  4079. if (taicpu(p).opcode = A_FSTP) then
  4080. taicpu(p).opcode := A_FST
  4081. else
  4082. taicpu(p).opcode := A_FIST;
  4083. DebugMsg(SPeepholeOptimization + 'FstpFld2Fst',p);
  4084. RemoveInstruction(hp1);
  4085. end;
  4086. end;
  4087. end;
  4088. function TX86AsmOptimizer.OptPass1FLD(var p : tai) : boolean;
  4089. var
  4090. hp1, hp2: tai;
  4091. begin
  4092. result:=false;
  4093. if MatchOpType(taicpu(p),top_reg) and
  4094. GetNextInstruction(p, hp1) and
  4095. (hp1.typ = Ait_Instruction) and
  4096. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  4097. (taicpu(hp1).oper[0]^.reg = NR_ST) and
  4098. (taicpu(hp1).oper[1]^.reg = NR_ST1) then
  4099. { change to
  4100. fld reg fxxx reg,st
  4101. fxxxp st, st1 (hp1)
  4102. Remark: non commutative operations must be reversed!
  4103. }
  4104. begin
  4105. case taicpu(hp1).opcode Of
  4106. A_FMULP,A_FADDP,
  4107. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  4108. begin
  4109. case taicpu(hp1).opcode Of
  4110. A_FADDP: taicpu(hp1).opcode := A_FADD;
  4111. A_FMULP: taicpu(hp1).opcode := A_FMUL;
  4112. A_FSUBP: taicpu(hp1).opcode := A_FSUBR;
  4113. A_FSUBRP: taicpu(hp1).opcode := A_FSUB;
  4114. A_FDIVP: taicpu(hp1).opcode := A_FDIVR;
  4115. A_FDIVRP: taicpu(hp1).opcode := A_FDIV;
  4116. else
  4117. internalerror(2019050534);
  4118. end;
  4119. taicpu(hp1).oper[0]^.reg := taicpu(p).oper[0]^.reg;
  4120. taicpu(hp1).oper[1]^.reg := NR_ST;
  4121. RemoveCurrentP(p, hp1);
  4122. Result:=true;
  4123. exit;
  4124. end;
  4125. else
  4126. ;
  4127. end;
  4128. end
  4129. else
  4130. if MatchOpType(taicpu(p),top_ref) and
  4131. GetNextInstruction(p, hp2) and
  4132. (hp2.typ = Ait_Instruction) and
  4133. MatchOpType(taicpu(hp2),top_reg,top_reg) and
  4134. (taicpu(p).opsize in [S_FS, S_FL]) and
  4135. (taicpu(hp2).oper[0]^.reg = NR_ST) and
  4136. (taicpu(hp2).oper[1]^.reg = NR_ST1) then
  4137. if GetLastInstruction(p, hp1) and
  4138. MatchInstruction(hp1,A_FLD,A_FST,[taicpu(p).opsize]) and
  4139. MatchOpType(taicpu(hp1),top_ref) and
  4140. RefsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  4141. if ((taicpu(hp2).opcode = A_FMULP) or
  4142. (taicpu(hp2).opcode = A_FADDP)) then
  4143. { change to
  4144. fld/fst mem1 (hp1) fld/fst mem1
  4145. fld mem1 (p) fadd/
  4146. faddp/ fmul st, st
  4147. fmulp st, st1 (hp2) }
  4148. begin
  4149. RemoveCurrentP(p, hp1);
  4150. if (taicpu(hp2).opcode = A_FADDP) then
  4151. taicpu(hp2).opcode := A_FADD
  4152. else
  4153. taicpu(hp2).opcode := A_FMUL;
  4154. taicpu(hp2).oper[1]^.reg := NR_ST;
  4155. end
  4156. else
  4157. { change to
  4158. fld/fst mem1 (hp1) fld/fst mem1
  4159. fld mem1 (p) fld st}
  4160. begin
  4161. taicpu(p).changeopsize(S_FL);
  4162. taicpu(p).loadreg(0,NR_ST);
  4163. end
  4164. else
  4165. begin
  4166. case taicpu(hp2).opcode Of
  4167. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  4168. { change to
  4169. fld/fst mem1 (hp1) fld/fst mem1
  4170. fld mem2 (p) fxxx mem2
  4171. fxxxp st, st1 (hp2) }
  4172. begin
  4173. case taicpu(hp2).opcode Of
  4174. A_FADDP: taicpu(p).opcode := A_FADD;
  4175. A_FMULP: taicpu(p).opcode := A_FMUL;
  4176. A_FSUBP: taicpu(p).opcode := A_FSUBR;
  4177. A_FSUBRP: taicpu(p).opcode := A_FSUB;
  4178. A_FDIVP: taicpu(p).opcode := A_FDIVR;
  4179. A_FDIVRP: taicpu(p).opcode := A_FDIV;
  4180. else
  4181. internalerror(2019050533);
  4182. end;
  4183. RemoveInstruction(hp2);
  4184. end
  4185. else
  4186. ;
  4187. end
  4188. end
  4189. end;
  4190. function TX86AsmOptimizer.OptPass1Cmp(var p: tai): boolean;
  4191. var
  4192. v: TCGInt;
  4193. hp1, hp2: tai;
  4194. FirstMatch: Boolean;
  4195. begin
  4196. Result:=false;
  4197. if taicpu(p).oper[0]^.typ = top_const then
  4198. begin
  4199. { Though GetNextInstruction can be factored out, it is an expensive
  4200. call, so delay calling it until we have first checked cheaper
  4201. conditions that are independent of it. }
  4202. if (taicpu(p).oper[0]^.val = 0) and
  4203. (taicpu(p).oper[1]^.typ = top_reg) and
  4204. GetNextInstruction(p, hp1) and
  4205. MatchInstruction(hp1,A_Jcc,A_SETcc,[]) then
  4206. begin
  4207. hp2 := p;
  4208. FirstMatch := True;
  4209. { When dealing with "cmp $0,%reg", only ZF and SF contain
  4210. anything meaningful once it's converted to "test %reg,%reg";
  4211. additionally, some jumps will always (or never) branch, so
  4212. evaluate every jump immediately following the
  4213. comparison, optimising the conditions if possible.
  4214. Similarly with SETcc... those that are always set to 0 or 1
  4215. are changed to MOV instructions }
  4216. while FirstMatch or { Saves calling GetNextInstruction unnecessarily }
  4217. (
  4218. GetNextInstruction(hp2, hp1) and
  4219. MatchInstruction(hp1,A_Jcc,A_SETcc,[])
  4220. ) do
  4221. begin
  4222. FirstMatch := False;
  4223. case taicpu(hp1).condition of
  4224. C_B, C_C, C_NAE, C_O:
  4225. { For B/NAE:
  4226. Will never branch since an unsigned integer can never be below zero
  4227. For C/O:
  4228. Result cannot overflow because 0 is being subtracted
  4229. }
  4230. begin
  4231. if taicpu(hp1).opcode = A_Jcc then
  4232. begin
  4233. DebugMsg(SPeepholeOptimization + 'Cmpcc2Testcc - condition B/C/NAE/O --> Never (jump removed)', hp1);
  4234. TAsmLabel(taicpu(hp1).oper[0]^.ref^.symbol).decrefs;
  4235. RemoveInstruction(hp1);
  4236. { Since hp1 was deleted, hp2 must not be updated }
  4237. Continue;
  4238. end
  4239. else
  4240. begin
  4241. DebugMsg(SPeepholeOptimization + 'Cmpcc2Testcc - condition B/C/NAE/O --> Never (set -> mov 0)', hp1);
  4242. { Convert "set(c) %reg" instruction to "movb 0,%reg" }
  4243. taicpu(hp1).opcode := A_MOV;
  4244. taicpu(hp1).ops := 2;
  4245. taicpu(hp1).condition := C_None;
  4246. taicpu(hp1).opsize := S_B;
  4247. taicpu(hp1).loadreg(1,taicpu(hp1).oper[0]^.reg);
  4248. taicpu(hp1).loadconst(0, 0);
  4249. end;
  4250. end;
  4251. C_BE, C_NA:
  4252. begin
  4253. { Will only branch if equal to zero }
  4254. DebugMsg(SPeepholeOptimization + 'Cmpcc2Testcc - condition BE/NA --> E', hp1);
  4255. taicpu(hp1).condition := C_E;
  4256. end;
  4257. C_A, C_NBE:
  4258. begin
  4259. { Will only branch if not equal to zero }
  4260. DebugMsg(SPeepholeOptimization + 'Cmpcc2Testcc - condition A/NBE --> NE', hp1);
  4261. taicpu(hp1).condition := C_NE;
  4262. end;
  4263. C_AE, C_NB, C_NC, C_NO:
  4264. begin
  4265. { Will always branch }
  4266. DebugMsg(SPeepholeOptimization + 'Cmpcc2Testcc - condition AE/NB/NC/NO --> Always', hp1);
  4267. if taicpu(hp1).opcode = A_Jcc then
  4268. begin
  4269. MakeUnconditional(taicpu(hp1));
  4270. { Any jumps/set that follow will now be dead code }
  4271. RemoveDeadCodeAfterJump(taicpu(hp1));
  4272. Break;
  4273. end
  4274. else
  4275. begin
  4276. { Convert "set(c) %reg" instruction to "movb 1,%reg" }
  4277. taicpu(hp1).opcode := A_MOV;
  4278. taicpu(hp1).ops := 2;
  4279. taicpu(hp1).condition := C_None;
  4280. taicpu(hp1).opsize := S_B;
  4281. taicpu(hp1).loadreg(1,taicpu(hp1).oper[0]^.reg);
  4282. taicpu(hp1).loadconst(0, 1);
  4283. end;
  4284. end;
  4285. C_None:
  4286. InternalError(2020012201);
  4287. C_P, C_PE, C_NP, C_PO:
  4288. { We can't handle parity checks and they should never be generated
  4289. after a general-purpose CMP (it's used in some floating-point
  4290. comparisons that don't use CMP) }
  4291. InternalError(2020012202);
  4292. else
  4293. { Zero/Equality, Sign, their complements and all of the
  4294. signed comparisons do not need to be converted };
  4295. end;
  4296. hp2 := hp1;
  4297. end;
  4298. { Convert the instruction to a TEST }
  4299. taicpu(p).opcode := A_TEST;
  4300. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  4301. Result := True;
  4302. Exit;
  4303. end
  4304. else if (taicpu(p).oper[0]^.val = 1) and
  4305. GetNextInstruction(p, hp1) and
  4306. MatchInstruction(hp1,A_Jcc,A_SETcc,[]) and
  4307. (taicpu(hp1).condition in [C_L, C_NGE]) then
  4308. begin
  4309. { Convert; To:
  4310. cmp $1,r/m cmp $0,r/m
  4311. jl @lbl jle @lbl
  4312. }
  4313. DebugMsg(SPeepholeOptimization + 'Cmp1Jl2Cmp0Jle', p);
  4314. taicpu(p).oper[0]^.val := 0;
  4315. taicpu(hp1).condition := C_LE;
  4316. { If the instruction is now "cmp $0,%reg", convert it to a
  4317. TEST (and effectively do the work of the "cmp $0,%reg" in
  4318. the block above)
  4319. If it's a reference, we can get away with not setting
  4320. Result to True because he haven't evaluated the jump
  4321. in this pass yet.
  4322. }
  4323. if (taicpu(p).oper[1]^.typ = top_reg) then
  4324. begin
  4325. taicpu(p).opcode := A_TEST;
  4326. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  4327. Result := True;
  4328. end;
  4329. Exit;
  4330. end
  4331. else if (taicpu(p).oper[1]^.typ = top_reg) then
  4332. begin
  4333. { cmp register,$8000 neg register
  4334. je target --> jo target
  4335. .... only if register is deallocated before jump.}
  4336. case Taicpu(p).opsize of
  4337. S_B: v:=$80;
  4338. S_W: v:=$8000;
  4339. S_L: v:=qword($80000000);
  4340. { S_Q will never happen: cmp with 64 bit constants is not possible }
  4341. S_Q:
  4342. Exit;
  4343. else
  4344. internalerror(2013112905);
  4345. end;
  4346. if (taicpu(p).oper[0]^.val=v) and
  4347. GetNextInstruction(p, hp1) and
  4348. MatchInstruction(hp1,A_Jcc,A_SETcc,[]) and
  4349. (Taicpu(hp1).condition in [C_E,C_NE]) then
  4350. begin
  4351. TransferUsedRegs(TmpUsedRegs);
  4352. UpdateUsedRegs(TmpUsedRegs,tai(p.next));
  4353. if not(RegInUsedRegs(Taicpu(p).oper[1]^.reg, TmpUsedRegs)) then
  4354. begin
  4355. DebugMsg(SPeepholeOptimization + 'CmpJe2NegJo done',p);
  4356. Taicpu(p).opcode:=A_NEG;
  4357. Taicpu(p).loadoper(0,Taicpu(p).oper[1]^);
  4358. Taicpu(p).clearop(1);
  4359. Taicpu(p).ops:=1;
  4360. if Taicpu(hp1).condition=C_E then
  4361. Taicpu(hp1).condition:=C_O
  4362. else
  4363. Taicpu(hp1).condition:=C_NO;
  4364. Result:=true;
  4365. exit;
  4366. end;
  4367. end;
  4368. end;
  4369. end;
  4370. if (taicpu(p).oper[1]^.typ = top_reg) and
  4371. GetNextInstruction(p, hp1) and
  4372. MatchInstruction(hp1,A_MOV,[]) and
  4373. not RegInInstruction(taicpu(p).oper[1]^.reg, hp1) and
  4374. (
  4375. (taicpu(p).oper[0]^.typ <> top_reg) or
  4376. not RegInInstruction(taicpu(p).oper[0]^.reg, hp1)
  4377. ) then
  4378. begin
  4379. { If we have something like:
  4380. cmp ###,%reg1
  4381. mov 0,%reg2
  4382. And no registers are shared, move the MOV command to before the
  4383. comparison as this means it can be optimised without worrying
  4384. about the FLAGS register. (This combination is generated by
  4385. "J(c)Mov1JmpMov0 -> Set(~c)", among other things).
  4386. }
  4387. SwapMovCmp(p, hp1);
  4388. Result := True;
  4389. Exit;
  4390. end;
  4391. end;
  4392. function TX86AsmOptimizer.OptPass1PXor(var p: tai): boolean;
  4393. var
  4394. hp1: tai;
  4395. begin
  4396. {
  4397. remove the second (v)pxor from
  4398. pxor reg,reg
  4399. ...
  4400. pxor reg,reg
  4401. }
  4402. Result:=false;
  4403. if MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^) and
  4404. MatchOpType(taicpu(p),top_reg,top_reg) and
  4405. GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
  4406. MatchInstruction(hp1,taicpu(p).opcode,[taicpu(p).opsize]) and
  4407. MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[0]^) and
  4408. MatchOperand(taicpu(hp1).oper[0]^,taicpu(hp1).oper[1]^) then
  4409. begin
  4410. DebugMsg(SPeepholeOptimization + 'PXorPXor2PXor done',hp1);
  4411. RemoveInstruction(hp1);
  4412. Result:=true;
  4413. Exit;
  4414. end
  4415. {
  4416. replace
  4417. pxor reg1,reg1
  4418. movapd/s reg1,reg2
  4419. dealloc reg1
  4420. by
  4421. pxor reg2,reg2
  4422. }
  4423. else if GetNextInstruction(p,hp1) and
  4424. { we mix single and double opperations here because we assume that the compiler
  4425. generates vmovapd only after double operations and vmovaps only after single operations }
  4426. MatchInstruction(hp1,A_MOVAPD,A_MOVAPS,[S_NO]) and
  4427. MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^) and
  4428. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) and
  4429. (taicpu(p).oper[0]^.typ=top_reg) then
  4430. begin
  4431. TransferUsedRegs(TmpUsedRegs);
  4432. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  4433. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  4434. begin
  4435. taicpu(p).loadoper(0,taicpu(hp1).oper[1]^);
  4436. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  4437. DebugMsg(SPeepholeOptimization + 'PXorMovapd2PXor done',p);
  4438. RemoveInstruction(hp1);
  4439. result:=true;
  4440. end;
  4441. end;
  4442. end;
  4443. function TX86AsmOptimizer.OptPass1VPXor(var p: tai): boolean;
  4444. var
  4445. hp1: tai;
  4446. begin
  4447. {
  4448. remove the second (v)pxor from
  4449. (v)pxor reg,reg
  4450. ...
  4451. (v)pxor reg,reg
  4452. }
  4453. Result:=false;
  4454. if MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^,taicpu(p).oper[2]^) and
  4455. MatchOpType(taicpu(p),top_reg,top_reg,top_reg) and
  4456. GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
  4457. MatchInstruction(hp1,taicpu(p).opcode,[taicpu(p).opsize]) and
  4458. MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[0]^) and
  4459. MatchOperand(taicpu(hp1).oper[0]^,taicpu(hp1).oper[1]^,taicpu(hp1).oper[2]^) then
  4460. begin
  4461. DebugMsg(SPeepholeOptimization + 'VPXorVPXor2PXor done',hp1);
  4462. RemoveInstruction(hp1);
  4463. Result:=true;
  4464. Exit;
  4465. end
  4466. else
  4467. Result:=OptPass1VOP(p);
  4468. end;
  4469. function TX86AsmOptimizer.OptPass1Imul(var p: tai): boolean;
  4470. var
  4471. hp1 : tai;
  4472. begin
  4473. result:=false;
  4474. { replace
  4475. IMul const,%mreg1,%mreg2
  4476. Mov %reg2,%mreg3
  4477. dealloc %mreg3
  4478. by
  4479. Imul const,%mreg1,%mreg23
  4480. }
  4481. if (taicpu(p).ops=3) and
  4482. GetNextInstruction(p,hp1) and
  4483. MatchInstruction(hp1,A_MOV,[taicpu(p).opsize]) and
  4484. MatchOperand(taicpu(p).oper[2]^,taicpu(hp1).oper[0]^) and
  4485. (taicpu(hp1).oper[1]^.typ=top_reg) then
  4486. begin
  4487. TransferUsedRegs(TmpUsedRegs);
  4488. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  4489. if not(RegUsedAfterInstruction(taicpu(hp1).oper[0]^.reg,hp1,TmpUsedRegs)) then
  4490. begin
  4491. taicpu(p).loadoper(2,taicpu(hp1).oper[1]^);
  4492. DebugMsg(SPeepholeOptimization + 'ImulMov2Imul done',p);
  4493. RemoveInstruction(hp1);
  4494. result:=true;
  4495. end;
  4496. end;
  4497. end;
  4498. function TX86AsmOptimizer.OptPass1Jcc(var p : tai) : boolean;
  4499. var
  4500. hp1, hp2, hp3, hp4, hp5: tai;
  4501. ThisReg: TRegister;
  4502. begin
  4503. Result := False;
  4504. if not GetNextInstruction(p,hp1) or (hp1.typ <> ait_instruction) then
  4505. Exit;
  4506. {
  4507. convert
  4508. j<c> .L1
  4509. mov 1,reg
  4510. jmp .L2
  4511. .L1
  4512. mov 0,reg
  4513. .L2
  4514. into
  4515. mov 0,reg
  4516. set<not(c)> reg
  4517. take care of alignment and that the mov 0,reg is not converted into a xor as this
  4518. would destroy the flag contents
  4519. Use MOVZX if size is preferred, since while mov 0,reg is bigger, it can be
  4520. executed at the same time as a previous comparison.
  4521. set<not(c)> reg
  4522. movzx reg, reg
  4523. }
  4524. if MatchInstruction(hp1,A_MOV,[]) and
  4525. (taicpu(hp1).oper[0]^.typ = top_const) and
  4526. (
  4527. (
  4528. (taicpu(hp1).oper[1]^.typ = top_reg)
  4529. {$ifdef i386}
  4530. { Under i386, ESI, EDI, EBP and ESP
  4531. don't have an 8-bit representation }
  4532. and not (getsupreg(taicpu(hp1).oper[1]^.reg) in [RS_ESI, RS_EDI, RS_EBP, RS_ESP])
  4533. {$endif i386}
  4534. ) or (
  4535. {$ifdef i386}
  4536. (taicpu(hp1).oper[1]^.typ <> top_reg) and
  4537. {$endif i386}
  4538. (taicpu(hp1).opsize = S_B)
  4539. )
  4540. ) and
  4541. GetNextInstruction(hp1,hp2) and
  4542. MatchInstruction(hp2,A_JMP,[]) and (taicpu(hp2).oper[0]^.ref^.refaddr=addr_full) and
  4543. GetNextInstruction(hp2,hp3) and
  4544. SkipAligns(hp3, hp3) and
  4545. (hp3.typ=ait_label) and
  4546. (tasmlabel(taicpu(p).oper[0]^.ref^.symbol)=tai_label(hp3).labsym) and
  4547. GetNextInstruction(hp3,hp4) and
  4548. MatchInstruction(hp4,A_MOV,[taicpu(hp1).opsize]) and
  4549. (taicpu(hp4).oper[0]^.typ = top_const) and
  4550. (
  4551. ((taicpu(hp1).oper[0]^.val = 0) and (taicpu(hp4).oper[0]^.val = 1)) or
  4552. ((taicpu(hp1).oper[0]^.val = 1) and (taicpu(hp4).oper[0]^.val = 0))
  4553. ) and
  4554. MatchOperand(taicpu(hp1).oper[1]^,taicpu(hp4).oper[1]^) and
  4555. GetNextInstruction(hp4,hp5) and
  4556. SkipAligns(hp5, hp5) and
  4557. (hp5.typ=ait_label) and
  4558. (tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol)=tai_label(hp5).labsym) then
  4559. begin
  4560. if (taicpu(hp1).oper[0]^.val = 1) and (taicpu(hp4).oper[0]^.val = 0) then
  4561. taicpu(p).condition := inverse_cond(taicpu(p).condition);
  4562. tai_label(hp3).labsym.DecRefs;
  4563. { If this isn't the only reference to the middle label, we can
  4564. still make a saving - only that the first jump and everything
  4565. that follows will remain. }
  4566. if (tai_label(hp3).labsym.getrefs = 0) then
  4567. begin
  4568. if (taicpu(hp1).oper[0]^.val = 1) and (taicpu(hp4).oper[0]^.val = 0) then
  4569. DebugMsg(SPeepholeOptimization + 'J(c)Mov1JmpMov0 -> Set(~c)',p)
  4570. else
  4571. DebugMsg(SPeepholeOptimization + 'J(c)Mov0JmpMov1 -> Set(c)',p);
  4572. { remove jump, first label and second MOV (also catching any aligns) }
  4573. repeat
  4574. if not GetNextInstruction(hp2, hp3) then
  4575. InternalError(2021040810);
  4576. RemoveInstruction(hp2);
  4577. hp2 := hp3;
  4578. until hp2 = hp5;
  4579. { Don't decrement reference count before the removal loop
  4580. above, otherwise GetNextInstruction won't stop on the
  4581. the label }
  4582. tai_label(hp5).labsym.DecRefs;
  4583. end
  4584. else
  4585. begin
  4586. if (taicpu(hp1).oper[0]^.val = 1) and (taicpu(hp4).oper[0]^.val = 0) then
  4587. DebugMsg(SPeepholeOptimization + 'J(c)Mov1JmpMov0 -> Set(~c) (partial)',p)
  4588. else
  4589. DebugMsg(SPeepholeOptimization + 'J(c)Mov0JmpMov1 -> Set(c) (partial)',p);
  4590. end;
  4591. taicpu(p).opcode:=A_SETcc;
  4592. taicpu(p).opsize:=S_B;
  4593. taicpu(p).is_jmp:=False;
  4594. if taicpu(hp1).opsize=S_B then
  4595. begin
  4596. taicpu(p).loadoper(0, taicpu(hp1).oper[1]^);
  4597. RemoveInstruction(hp1);
  4598. end
  4599. else
  4600. begin
  4601. { Will be a register because the size can't be S_B otherwise }
  4602. ThisReg := newreg(R_INTREGISTER,getsupreg(taicpu(hp1).oper[1]^.reg), R_SUBL);
  4603. taicpu(p).loadreg(0, ThisReg);
  4604. if (cs_opt_size in current_settings.optimizerswitches) and IsMOVZXAcceptable then
  4605. begin
  4606. case taicpu(hp1).opsize of
  4607. S_W:
  4608. taicpu(hp1).opsize := S_BW;
  4609. S_L:
  4610. taicpu(hp1).opsize := S_BL;
  4611. {$ifdef x86_64}
  4612. S_Q:
  4613. begin
  4614. taicpu(hp1).opsize := S_BL;
  4615. { Change the destination register to 32-bit }
  4616. taicpu(hp1).loadreg(1, newreg(R_INTREGISTER,getsupreg(ThisReg), R_SUBD));
  4617. end;
  4618. {$endif x86_64}
  4619. else
  4620. InternalError(2021040820);
  4621. end;
  4622. taicpu(hp1).opcode := A_MOVZX;
  4623. taicpu(hp1).loadreg(0, ThisReg);
  4624. end
  4625. else
  4626. begin
  4627. AllocRegBetween(NR_FLAGS,p,hp1,UsedRegs);
  4628. { hp1 is already a MOV instruction with the correct register }
  4629. taicpu(hp1).loadconst(0, 0);
  4630. { Inserting it right before p will guarantee that the flags are also tracked }
  4631. asml.Remove(hp1);
  4632. asml.InsertBefore(hp1, p);
  4633. end;
  4634. end;
  4635. Result:=true;
  4636. exit;
  4637. end
  4638. end;
  4639. function TX86AsmOptimizer.CheckJumpMovTransferOpt(var p: tai; hp1: tai; LoopCount: Integer; out Count: Integer): Boolean;
  4640. var
  4641. hp2, hp3, first_assignment: tai;
  4642. IncCount, OperIdx: Integer;
  4643. OrigLabel: TAsmLabel;
  4644. begin
  4645. Count := 0;
  4646. Result := False;
  4647. first_assignment := nil;
  4648. if (LoopCount >= 20) then
  4649. begin
  4650. { Guard against infinite loops }
  4651. Exit;
  4652. end;
  4653. if (taicpu(p).oper[0]^.typ <> top_ref) or
  4654. (taicpu(p).oper[0]^.ref^.refaddr <> addr_full) or
  4655. (taicpu(p).oper[0]^.ref^.base <> NR_NO) or
  4656. (taicpu(p).oper[0]^.ref^.index <> NR_NO) or
  4657. not (taicpu(p).oper[0]^.ref^.symbol is TAsmLabel) then
  4658. Exit;
  4659. OrigLabel := TAsmLabel(taicpu(p).oper[0]^.ref^.symbol);
  4660. {
  4661. change
  4662. jmp .L1
  4663. ...
  4664. .L1:
  4665. mov ##, ## ( multiple movs possible )
  4666. jmp/ret
  4667. into
  4668. mov ##, ##
  4669. jmp/ret
  4670. }
  4671. if not Assigned(hp1) then
  4672. begin
  4673. hp1 := GetLabelWithSym(OrigLabel);
  4674. if not Assigned(hp1) or not SkipLabels(hp1, hp1) then
  4675. Exit;
  4676. end;
  4677. hp2 := hp1;
  4678. while Assigned(hp2) do
  4679. begin
  4680. if Assigned(hp2) and (hp2.typ in [ait_label, ait_align]) then
  4681. SkipLabels(hp2,hp2);
  4682. if not Assigned(hp2) or (hp2.typ <> ait_instruction) then
  4683. Break;
  4684. case taicpu(hp2).opcode of
  4685. A_MOVSS:
  4686. begin
  4687. if taicpu(hp2).ops = 0 then
  4688. { Wrong MOVSS }
  4689. Break;
  4690. Inc(Count);
  4691. if Count >= 5 then
  4692. { Too many to be worthwhile }
  4693. Break;
  4694. GetNextInstruction(hp2, hp2);
  4695. Continue;
  4696. end;
  4697. A_MOV,
  4698. A_MOVD,
  4699. A_MOVQ,
  4700. A_MOVSX,
  4701. {$ifdef x86_64}
  4702. A_MOVSXD,
  4703. {$endif x86_64}
  4704. A_MOVZX,
  4705. A_MOVAPS,
  4706. A_MOVUPS,
  4707. A_MOVSD,
  4708. A_MOVAPD,
  4709. A_MOVUPD,
  4710. A_MOVDQA,
  4711. A_MOVDQU,
  4712. A_VMOVSS,
  4713. A_VMOVAPS,
  4714. A_VMOVUPS,
  4715. A_VMOVSD,
  4716. A_VMOVAPD,
  4717. A_VMOVUPD,
  4718. A_VMOVDQA,
  4719. A_VMOVDQU:
  4720. begin
  4721. Inc(Count);
  4722. if Count >= 5 then
  4723. { Too many to be worthwhile }
  4724. Break;
  4725. GetNextInstruction(hp2, hp2);
  4726. Continue;
  4727. end;
  4728. A_JMP:
  4729. begin
  4730. { Guard against infinite loops }
  4731. if taicpu(hp2).oper[0]^.ref^.symbol = OrigLabel then
  4732. Exit;
  4733. { Analyse this jump first in case it also duplicates assignments }
  4734. if CheckJumpMovTransferOpt(hp2, nil, LoopCount + 1, IncCount) then
  4735. begin
  4736. { Something did change! }
  4737. Result := True;
  4738. Inc(Count, IncCount);
  4739. if Count >= 5 then
  4740. begin
  4741. { Too many to be worthwhile }
  4742. Exit;
  4743. end;
  4744. if MatchInstruction(hp2, [A_JMP, A_RET], []) then
  4745. Break;
  4746. end;
  4747. Result := True;
  4748. Break;
  4749. end;
  4750. A_RET:
  4751. begin
  4752. Result := True;
  4753. Break;
  4754. end;
  4755. else
  4756. Break;
  4757. end;
  4758. end;
  4759. if Result then
  4760. begin
  4761. { A count of zero can happen when CheckJumpMovTransferOpt is called recursively }
  4762. if Count = 0 then
  4763. begin
  4764. Result := False;
  4765. Exit;
  4766. end;
  4767. hp3 := p;
  4768. DebugMsg(SPeepholeOptimization + 'Duplicated ' + debug_tostr(Count) + ' assignment(s) and redirected jump', p);
  4769. while True do
  4770. begin
  4771. if Assigned(hp1) and (hp1.typ in [ait_label, ait_align]) then
  4772. SkipLabels(hp1,hp1);
  4773. if (hp1.typ <> ait_instruction) then
  4774. InternalError(2021040720);
  4775. case taicpu(hp1).opcode of
  4776. A_JMP:
  4777. begin
  4778. { Change the original jump to the new destination }
  4779. OrigLabel.decrefs;
  4780. taicpu(hp1).oper[0]^.ref^.symbol.increfs;
  4781. taicpu(p).loadref(0, taicpu(hp1).oper[0]^.ref^);
  4782. { Set p to the first duplicated assignment so it can get optimised if needs be }
  4783. if not Assigned(first_assignment) then
  4784. InternalError(2021040810)
  4785. else
  4786. p := first_assignment;
  4787. Exit;
  4788. end;
  4789. A_RET:
  4790. begin
  4791. { Now change the jump into a RET instruction }
  4792. ConvertJumpToRET(p, hp1);
  4793. { Set p to the first duplicated assignment so it can get optimised if needs be }
  4794. if not Assigned(first_assignment) then
  4795. InternalError(2021040811)
  4796. else
  4797. p := first_assignment;
  4798. Exit;
  4799. end;
  4800. else
  4801. begin
  4802. { Duplicate the MOV instruction }
  4803. hp3:=tai(hp1.getcopy);
  4804. if first_assignment = nil then
  4805. first_assignment := hp3;
  4806. asml.InsertBefore(hp3, p);
  4807. { Make sure the compiler knows about any final registers written here }
  4808. for OperIdx := 0 to taicpu(hp3).ops - 1 do
  4809. with taicpu(hp3).oper[OperIdx]^ do
  4810. begin
  4811. case typ of
  4812. top_ref:
  4813. begin
  4814. if (ref^.base <> NR_NO) and
  4815. (getsupreg(ref^.base) <> RS_ESP) and
  4816. (getsupreg(ref^.base) <> RS_EBP)
  4817. {$ifdef x86_64} and (ref^.base <> NR_RIP) {$endif x86_64}
  4818. then
  4819. AllocRegBetween(ref^.base, hp3, tai(p.Next), UsedRegs);
  4820. if (ref^.index <> NR_NO) and
  4821. (getsupreg(ref^.index) <> RS_ESP) and
  4822. (getsupreg(ref^.index) <> RS_EBP)
  4823. {$ifdef x86_64} and (ref^.index <> NR_RIP) {$endif x86_64} and
  4824. (ref^.index <> ref^.base) then
  4825. AllocRegBetween(ref^.index, hp3, tai(p.Next), UsedRegs);
  4826. end;
  4827. top_reg:
  4828. AllocRegBetween(reg, hp3, tai(p.Next), UsedRegs);
  4829. else
  4830. ;
  4831. end;
  4832. end;
  4833. end;
  4834. end;
  4835. if not GetNextInstruction(hp1, hp1) then
  4836. { Should have dropped out earlier }
  4837. InternalError(2021040710);
  4838. end;
  4839. end;
  4840. end;
  4841. procedure TX86AsmOptimizer.SwapMovCmp(var p, hp1: tai);
  4842. var
  4843. hp2: tai;
  4844. X: Integer;
  4845. begin
  4846. asml.Remove(hp1);
  4847. { Try to insert after the last instructions where the FLAGS register is not yet in use }
  4848. if not GetLastInstruction(p, hp2) then
  4849. asml.InsertBefore(hp1, p)
  4850. else
  4851. asml.InsertAfter(hp1, hp2);
  4852. DebugMsg(SPeepholeOptimization + 'Swapped ' + debug_op2str(taicpu(p).opcode) + ' and mov instructions to improve optimisation potential', hp1);
  4853. for X := 0 to 1 do
  4854. case taicpu(hp1).oper[X]^.typ of
  4855. top_reg:
  4856. AllocRegBetween(taicpu(hp1).oper[X]^.reg, hp1, p, UsedRegs);
  4857. top_ref:
  4858. begin
  4859. if taicpu(hp1).oper[X]^.ref^.base <> NR_NO then
  4860. AllocRegBetween(taicpu(hp1).oper[X]^.ref^.base, hp1, p, UsedRegs);
  4861. if taicpu(hp1).oper[X]^.ref^.index <> NR_NO then
  4862. AllocRegBetween(taicpu(hp1).oper[X]^.ref^.index, hp1, p, UsedRegs);
  4863. end;
  4864. else
  4865. ;
  4866. end;
  4867. end;
  4868. function TX86AsmOptimizer.OptPass2MOV(var p : tai) : boolean;
  4869. function IsXCHGAcceptable: Boolean; inline;
  4870. begin
  4871. { Always accept if optimising for size }
  4872. Result := (cs_opt_size in current_settings.optimizerswitches) or
  4873. (
  4874. {$ifdef x86_64}
  4875. { XCHG takes 3 cycles on AMD Athlon64 }
  4876. (current_settings.optimizecputype >= cpu_core_i)
  4877. {$else x86_64}
  4878. { From the Pentium M onwards, XCHG only has a latency of 2 rather
  4879. than 3, so it becomes a saving compared to three MOVs with two of
  4880. them able to execute simultaneously. [Kit] }
  4881. (current_settings.optimizecputype >= cpu_PentiumM)
  4882. {$endif x86_64}
  4883. );
  4884. end;
  4885. var
  4886. NewRef: TReference;
  4887. hp1, hp2, hp3, hp4: Tai;
  4888. {$ifndef x86_64}
  4889. OperIdx: Integer;
  4890. {$endif x86_64}
  4891. NewInstr : Taicpu;
  4892. NewAligh : Tai_align;
  4893. DestLabel: TAsmLabel;
  4894. begin
  4895. Result:=false;
  4896. { This optimisation adds an instruction, so only do it for speed }
  4897. if not (cs_opt_size in current_settings.optimizerswitches) and
  4898. MatchOpType(taicpu(p), top_const, top_reg) and
  4899. (taicpu(p).oper[0]^.val = 0) then
  4900. begin
  4901. { To avoid compiler warning }
  4902. DestLabel := nil;
  4903. if (p.typ <> ait_instruction) or (taicpu(p).oper[1]^.typ <> top_reg) then
  4904. InternalError(2021040750);
  4905. if not GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[1]^.reg) then
  4906. Exit;
  4907. case hp1.typ of
  4908. ait_label:
  4909. begin
  4910. { Change:
  4911. mov $0,%reg mov $0,%reg
  4912. @Lbl1: @Lbl1:
  4913. test %reg,%reg / cmp $0,%reg test %reg,%reg / mov $0,%reg
  4914. je @Lbl2 jne @Lbl2
  4915. To: To:
  4916. mov $0,%reg mov $0,%reg
  4917. jmp @Lbl2 jmp @Lbl3
  4918. (align) (align)
  4919. @Lbl1: @Lbl1:
  4920. test %reg,%reg / cmp $0,%reg test %reg,%reg / cmp $0,%reg
  4921. je @Lbl2 je @Lbl2
  4922. @Lbl3: <-- Only if label exists
  4923. (Not if it's optimised for size)
  4924. }
  4925. if not GetNextInstruction(hp1, hp2) then
  4926. Exit;
  4927. if not (cs_opt_size in current_settings.optimizerswitches) and
  4928. (hp2.typ = ait_instruction) and
  4929. (
  4930. { Register sizes must exactly match }
  4931. (
  4932. (taicpu(hp2).opcode = A_CMP) and
  4933. MatchOperand(taicpu(hp2).oper[0]^, 0) and
  4934. MatchOperand(taicpu(hp2).oper[1]^, taicpu(p).oper[1]^.reg)
  4935. ) or (
  4936. (taicpu(hp2).opcode = A_TEST) and
  4937. MatchOperand(taicpu(hp2).oper[0]^, taicpu(p).oper[1]^.reg) and
  4938. MatchOperand(taicpu(hp2).oper[1]^, taicpu(p).oper[1]^.reg)
  4939. )
  4940. ) and GetNextInstruction(hp2, hp3) and
  4941. (hp3.typ = ait_instruction) and
  4942. (taicpu(hp3).opcode = A_JCC) and
  4943. (taicpu(hp3).oper[0]^.typ=top_ref) and (taicpu(hp3).oper[0]^.ref^.refaddr=addr_full) and (taicpu(hp3).oper[0]^.ref^.base=NR_NO) and
  4944. (taicpu(hp3).oper[0]^.ref^.index=NR_NO) and (taicpu(hp3).oper[0]^.ref^.symbol is tasmlabel) then
  4945. begin
  4946. { Check condition of jump }
  4947. { Always true? }
  4948. if condition_in(C_E, taicpu(hp3).condition) then
  4949. begin
  4950. { Copy label symbol and obtain matching label entry for the
  4951. conditional jump, as this will be our destination}
  4952. DestLabel := tasmlabel(taicpu(hp3).oper[0]^.ref^.symbol);
  4953. DebugMsg(SPeepholeOptimization + 'Mov0LblCmp0Je -> Mov0JmpLblCmp0Je', p);
  4954. Result := True;
  4955. end
  4956. { Always false? }
  4957. else if condition_in(C_NE, taicpu(hp3).condition) and GetNextInstruction(hp3, hp2) then
  4958. begin
  4959. { This is only worth it if there's a jump to take }
  4960. case hp2.typ of
  4961. ait_instruction:
  4962. begin
  4963. if taicpu(hp2).opcode = A_JMP then
  4964. begin
  4965. DestLabel := tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol);
  4966. { An unconditional jump follows the conditional jump which will always be false,
  4967. so use this jump's destination for the new jump }
  4968. DebugMsg(SPeepholeOptimization + 'Mov0LblCmp0Jne -> Mov0JmpLblCmp0Jne (with JMP)', p);
  4969. Result := True;
  4970. end
  4971. else if taicpu(hp2).opcode = A_JCC then
  4972. begin
  4973. DestLabel := tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol);
  4974. if condition_in(C_E, taicpu(hp2).condition) then
  4975. begin
  4976. { A second conditional jump follows the conditional jump which will always be false,
  4977. while the second jump is always True, so use this jump's destination for the new jump }
  4978. DebugMsg(SPeepholeOptimization + 'Mov0LblCmp0Jne -> Mov0JmpLblCmp0Jne (with second Jcc)', p);
  4979. Result := True;
  4980. end;
  4981. { Don't risk it if the jump isn't always true (Result remains False) }
  4982. end;
  4983. end;
  4984. else
  4985. { If anything else don't optimise };
  4986. end;
  4987. end;
  4988. if Result then
  4989. begin
  4990. { Just so we have something to insert as a paremeter}
  4991. reference_reset(NewRef, 1, []);
  4992. NewInstr := taicpu.op_ref(A_JMP, S_NO, NewRef);
  4993. { Now actually load the correct parameter }
  4994. NewInstr.loadsymbol(0, DestLabel, 0);
  4995. { Get instruction before original label (may not be p under -O3) }
  4996. if not GetLastInstruction(hp1, hp2) then
  4997. { Shouldn't fail here }
  4998. InternalError(2021040701);
  4999. DestLabel.increfs;
  5000. AsmL.InsertAfter(NewInstr, hp2);
  5001. { Add new alignment field }
  5002. (* AsmL.InsertAfter(
  5003. cai_align.create_max(
  5004. current_settings.alignment.jumpalign,
  5005. current_settings.alignment.jumpalignskipmax
  5006. ),
  5007. NewInstr
  5008. ); *)
  5009. end;
  5010. Exit;
  5011. end;
  5012. end;
  5013. else
  5014. ;
  5015. end;
  5016. end;
  5017. if not GetNextInstruction(p, hp1) then
  5018. Exit;
  5019. if MatchInstruction(hp1, A_JMP, [S_NO]) then
  5020. begin
  5021. { Sometimes the MOVs that OptPass2JMP produces can be improved
  5022. further, but we can't just put this jump optimisation in pass 1
  5023. because it tends to perform worse when conditional jumps are
  5024. nearby (e.g. when converting CMOV instructions). [Kit] }
  5025. if OptPass2JMP(hp1) then
  5026. { call OptPass1MOV once to potentially merge any MOVs that were created }
  5027. Result := OptPass1MOV(p)
  5028. { OptPass2MOV will now exit but will be called again if OptPass1MOV
  5029. returned True and the instruction is still a MOV, thus checking
  5030. the optimisations below }
  5031. { If OptPass2JMP returned False, no optimisations were done to
  5032. the jump and there are no further optimisations that can be done
  5033. to the MOV instruction on this pass }
  5034. end
  5035. else if MatchOpType(taicpu(p),top_reg,top_reg) and
  5036. (taicpu(p).opsize in [S_L{$ifdef x86_64}, S_Q{$endif x86_64}]) and
  5037. MatchInstruction(hp1,A_ADD,A_SUB,[taicpu(p).opsize]) and
  5038. MatchOpType(taicpu(hp1),top_const,top_reg) and
  5039. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) and
  5040. { be lazy, checking separately for sub would be slightly better }
  5041. (abs(taicpu(hp1).oper[0]^.val)<=$7fffffff) then
  5042. begin
  5043. { Change:
  5044. movl/q %reg1,%reg2 movl/q %reg1,%reg2
  5045. addl/q $x,%reg2 subl/q $x,%reg2
  5046. To:
  5047. leal/q x(%reg1),%reg2 leal/q -x(%reg1),%reg2
  5048. }
  5049. TransferUsedRegs(TmpUsedRegs);
  5050. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  5051. UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
  5052. if not GetNextInstruction(hp1, hp2) or
  5053. (
  5054. { The FLAGS register isn't always tracked properly, so do not
  5055. perform this optimisation if a conditional statement follows }
  5056. not RegReadByInstruction(NR_DEFAULTFLAGS, hp2) and
  5057. not RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp2, TmpUsedRegs)
  5058. ) then
  5059. begin
  5060. reference_reset(NewRef, 1, []);
  5061. NewRef.base := taicpu(p).oper[0]^.reg;
  5062. NewRef.scalefactor := 1;
  5063. if taicpu(hp1).opcode = A_ADD then
  5064. begin
  5065. DebugMsg(SPeepholeOptimization + 'MovAdd2Lea', p);
  5066. NewRef.offset := taicpu(hp1).oper[0]^.val;
  5067. end
  5068. else
  5069. begin
  5070. DebugMsg(SPeepholeOptimization + 'MovSub2Lea', p);
  5071. NewRef.offset := -taicpu(hp1).oper[0]^.val;
  5072. end;
  5073. taicpu(p).opcode := A_LEA;
  5074. taicpu(p).loadref(0, NewRef);
  5075. RemoveInstruction(hp1);
  5076. Result := True;
  5077. Exit;
  5078. end;
  5079. end
  5080. else if MatchOpType(taicpu(p),top_reg,top_reg) and
  5081. {$ifdef x86_64}
  5082. MatchInstruction(hp1,A_MOVZX,A_MOVSX,A_MOVSXD,[]) and
  5083. {$else x86_64}
  5084. MatchInstruction(hp1,A_MOVZX,A_MOVSX,[]) and
  5085. {$endif x86_64}
  5086. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  5087. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  5088. { mov reg1, reg2 mov reg1, reg2
  5089. movzx/sx reg2, reg3 to movzx/sx reg1, reg3}
  5090. begin
  5091. taicpu(hp1).oper[0]^.reg := taicpu(p).oper[0]^.reg;
  5092. DebugMsg(SPeepholeOptimization + 'mov %reg1,%reg2; movzx/sx %reg2,%reg3 -> mov %reg1,%reg2;movzx/sx %reg1,%reg3',p);
  5093. { Don't remove the MOV command without first checking that reg2 isn't used afterwards,
  5094. or unless supreg(reg3) = supreg(reg2)). [Kit] }
  5095. TransferUsedRegs(TmpUsedRegs);
  5096. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  5097. if (getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) or
  5098. not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs)
  5099. then
  5100. begin
  5101. RemoveCurrentP(p, hp1);
  5102. Result:=true;
  5103. end;
  5104. exit;
  5105. end
  5106. else if MatchOpType(taicpu(p),top_reg,top_reg) and
  5107. IsXCHGAcceptable and
  5108. { XCHG doesn't support 8-byte registers }
  5109. (taicpu(p).opsize <> S_B) and
  5110. MatchInstruction(hp1, A_MOV, []) and
  5111. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  5112. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[0]^.reg) and
  5113. GetNextInstruction(hp1, hp2) and
  5114. MatchInstruction(hp2, A_MOV, []) and
  5115. { Don't need to call MatchOpType for hp2 because the operand matches below cover for it }
  5116. MatchOperand(taicpu(hp2).oper[0]^, taicpu(p).oper[1]^.reg) and
  5117. MatchOperand(taicpu(hp2).oper[1]^, taicpu(hp1).oper[0]^.reg) then
  5118. begin
  5119. { mov %reg1,%reg2
  5120. mov %reg3,%reg1 -> xchg %reg3,%reg1
  5121. mov %reg2,%reg3
  5122. (%reg2 not used afterwards)
  5123. Note that xchg takes 3 cycles to execute, and generally mov's take
  5124. only one cycle apiece, but the first two mov's can be executed in
  5125. parallel, only taking 2 cycles overall. Older processors should
  5126. therefore only optimise for size. [Kit]
  5127. }
  5128. TransferUsedRegs(TmpUsedRegs);
  5129. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  5130. UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
  5131. if not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp2, TmpUsedRegs) then
  5132. begin
  5133. DebugMsg(SPeepholeOptimization + 'MovMovMov2XChg', p);
  5134. AllocRegBetween(taicpu(hp2).oper[1]^.reg, p, hp1, UsedRegs);
  5135. taicpu(hp1).opcode := A_XCHG;
  5136. RemoveCurrentP(p, hp1);
  5137. RemoveInstruction(hp2);
  5138. Result := True;
  5139. Exit;
  5140. end;
  5141. end
  5142. else if MatchOpType(taicpu(p),top_reg,top_reg) and
  5143. MatchInstruction(hp1, A_SAR, []) then
  5144. begin
  5145. if MatchOperand(taicpu(hp1).oper[0]^, 31) then
  5146. begin
  5147. { the use of %edx also covers the opsize being S_L }
  5148. if MatchOperand(taicpu(hp1).oper[1]^, NR_EDX) then
  5149. begin
  5150. { Note it has to be specifically "movl %eax,%edx", and those specific sub-registers }
  5151. if (taicpu(p).oper[0]^.reg = NR_EAX) and
  5152. (taicpu(p).oper[1]^.reg = NR_EDX) then
  5153. begin
  5154. { Change:
  5155. movl %eax,%edx
  5156. sarl $31,%edx
  5157. To:
  5158. cltd
  5159. }
  5160. DebugMsg(SPeepholeOptimization + 'MovSar2Cltd', p);
  5161. RemoveInstruction(hp1);
  5162. taicpu(p).opcode := A_CDQ;
  5163. taicpu(p).opsize := S_NO;
  5164. taicpu(p).clearop(1);
  5165. taicpu(p).clearop(0);
  5166. taicpu(p).ops:=0;
  5167. Result := True;
  5168. end
  5169. else if (cs_opt_size in current_settings.optimizerswitches) and
  5170. (taicpu(p).oper[0]^.reg = NR_EDX) and
  5171. (taicpu(p).oper[1]^.reg = NR_EAX) then
  5172. begin
  5173. { Change:
  5174. movl %edx,%eax
  5175. sarl $31,%edx
  5176. To:
  5177. movl %edx,%eax
  5178. cltd
  5179. Note that this creates a dependency between the two instructions,
  5180. so only perform if optimising for size.
  5181. }
  5182. DebugMsg(SPeepholeOptimization + 'MovSar2MovCltd', p);
  5183. taicpu(hp1).opcode := A_CDQ;
  5184. taicpu(hp1).opsize := S_NO;
  5185. taicpu(hp1).clearop(1);
  5186. taicpu(hp1).clearop(0);
  5187. taicpu(hp1).ops:=0;
  5188. end;
  5189. {$ifndef x86_64}
  5190. end
  5191. { Don't bother if CMOV is supported, because a more optimal
  5192. sequence would have been generated for the Abs() intrinsic }
  5193. else if not(CPUX86_HAS_CMOV in cpu_capabilities[current_settings.cputype]) and
  5194. { the use of %eax also covers the opsize being S_L }
  5195. MatchOperand(taicpu(hp1).oper[1]^, NR_EAX) and
  5196. (taicpu(p).oper[0]^.reg = NR_EAX) and
  5197. (taicpu(p).oper[1]^.reg = NR_EDX) and
  5198. GetNextInstruction(hp1, hp2) and
  5199. MatchInstruction(hp2, A_XOR, [S_L]) and
  5200. MatchOperand(taicpu(hp2).oper[0]^, NR_EAX) and
  5201. MatchOperand(taicpu(hp2).oper[1]^, NR_EDX) and
  5202. GetNextInstruction(hp2, hp3) and
  5203. MatchInstruction(hp3, A_SUB, [S_L]) and
  5204. MatchOperand(taicpu(hp3).oper[0]^, NR_EAX) and
  5205. MatchOperand(taicpu(hp3).oper[1]^, NR_EDX) then
  5206. begin
  5207. { Change:
  5208. movl %eax,%edx
  5209. sarl $31,%eax
  5210. xorl %eax,%edx
  5211. subl %eax,%edx
  5212. (Instruction that uses %edx)
  5213. (%eax deallocated)
  5214. (%edx deallocated)
  5215. To:
  5216. cltd
  5217. xorl %edx,%eax <-- Note the registers have swapped
  5218. subl %edx,%eax
  5219. (Instruction that uses %eax) <-- %eax rather than %edx
  5220. }
  5221. TransferUsedRegs(TmpUsedRegs);
  5222. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  5223. UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
  5224. UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
  5225. if not RegUsedAfterInstruction(NR_EAX, hp3, TmpUsedRegs) then
  5226. begin
  5227. if GetNextInstruction(hp3, hp4) and
  5228. not RegModifiedByInstruction(NR_EDX, hp4) and
  5229. not RegUsedAfterInstruction(NR_EDX, hp4, TmpUsedRegs) then
  5230. begin
  5231. DebugMsg(SPeepholeOptimization + 'abs() intrinsic optimisation', p);
  5232. taicpu(p).opcode := A_CDQ;
  5233. taicpu(p).clearop(1);
  5234. taicpu(p).clearop(0);
  5235. taicpu(p).ops:=0;
  5236. RemoveInstruction(hp1);
  5237. taicpu(hp2).loadreg(0, NR_EDX);
  5238. taicpu(hp2).loadreg(1, NR_EAX);
  5239. taicpu(hp3).loadreg(0, NR_EDX);
  5240. taicpu(hp3).loadreg(1, NR_EAX);
  5241. AllocRegBetween(NR_EAX, hp3, hp4, TmpUsedRegs);
  5242. { Convert references in the following instruction (hp4) from %edx to %eax }
  5243. for OperIdx := 0 to taicpu(hp4).ops - 1 do
  5244. with taicpu(hp4).oper[OperIdx]^ do
  5245. case typ of
  5246. top_reg:
  5247. if getsupreg(reg) = RS_EDX then
  5248. reg := newreg(R_INTREGISTER,RS_EAX,getsubreg(reg));
  5249. top_ref:
  5250. begin
  5251. if getsupreg(reg) = RS_EDX then
  5252. ref^.base := newreg(R_INTREGISTER,RS_EAX,getsubreg(reg));
  5253. if getsupreg(reg) = RS_EDX then
  5254. ref^.index := newreg(R_INTREGISTER,RS_EAX,getsubreg(reg));
  5255. end;
  5256. else
  5257. ;
  5258. end;
  5259. end;
  5260. end;
  5261. {$else x86_64}
  5262. end;
  5263. end
  5264. else if MatchOperand(taicpu(hp1).oper[0]^, 63) and
  5265. { the use of %rdx also covers the opsize being S_Q }
  5266. MatchOperand(taicpu(hp1).oper[1]^, NR_RDX) then
  5267. begin
  5268. { Note it has to be specifically "movq %rax,%rdx", and those specific sub-registers }
  5269. if (taicpu(p).oper[0]^.reg = NR_RAX) and
  5270. (taicpu(p).oper[1]^.reg = NR_RDX) then
  5271. begin
  5272. { Change:
  5273. movq %rax,%rdx
  5274. sarq $63,%rdx
  5275. To:
  5276. cqto
  5277. }
  5278. DebugMsg(SPeepholeOptimization + 'MovSar2Cqto', p);
  5279. RemoveInstruction(hp1);
  5280. taicpu(p).opcode := A_CQO;
  5281. taicpu(p).opsize := S_NO;
  5282. taicpu(p).clearop(1);
  5283. taicpu(p).clearop(0);
  5284. taicpu(p).ops:=0;
  5285. Result := True;
  5286. end
  5287. else if (cs_opt_size in current_settings.optimizerswitches) and
  5288. (taicpu(p).oper[0]^.reg = NR_RDX) and
  5289. (taicpu(p).oper[1]^.reg = NR_RAX) then
  5290. begin
  5291. { Change:
  5292. movq %rdx,%rax
  5293. sarq $63,%rdx
  5294. To:
  5295. movq %rdx,%rax
  5296. cqto
  5297. Note that this creates a dependency between the two instructions,
  5298. so only perform if optimising for size.
  5299. }
  5300. DebugMsg(SPeepholeOptimization + 'MovSar2MovCqto', p);
  5301. taicpu(hp1).opcode := A_CQO;
  5302. taicpu(hp1).opsize := S_NO;
  5303. taicpu(hp1).clearop(1);
  5304. taicpu(hp1).clearop(0);
  5305. taicpu(hp1).ops:=0;
  5306. {$endif x86_64}
  5307. end;
  5308. end;
  5309. end
  5310. else if MatchInstruction(hp1, A_MOV, []) and
  5311. (taicpu(hp1).oper[1]^.typ = top_reg) then
  5312. { Though "GetNextInstruction" could be factored out, along with
  5313. the instructions that depend on hp2, it is an expensive call that
  5314. should be delayed for as long as possible, hence we do cheaper
  5315. checks first that are likely to be False. [Kit] }
  5316. begin
  5317. if MatchOperand(taicpu(p).oper[1]^, NR_EDX) and
  5318. (
  5319. (
  5320. (taicpu(hp1).oper[1]^.reg = NR_EAX) and
  5321. (
  5322. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) or
  5323. MatchOperand(taicpu(hp1).oper[0]^, NR_EDX)
  5324. )
  5325. ) or
  5326. (
  5327. (taicpu(hp1).oper[1]^.reg = NR_EDX) and
  5328. (
  5329. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) or
  5330. MatchOperand(taicpu(hp1).oper[0]^, NR_EAX)
  5331. )
  5332. )
  5333. ) and
  5334. GetNextInstruction(hp1, hp2) and
  5335. MatchInstruction(hp2, A_SAR, []) and
  5336. MatchOperand(taicpu(hp2).oper[0]^, 31) then
  5337. begin
  5338. if MatchOperand(taicpu(hp2).oper[1]^, NR_EDX) then
  5339. begin
  5340. { Change:
  5341. movl r/m,%edx movl r/m,%eax movl r/m,%edx movl r/m,%eax
  5342. movl %edx,%eax or movl %eax,%edx or movl r/m,%eax or movl r/m,%edx
  5343. sarl $31,%edx sarl $31,%edx sarl $31,%edx sarl $31,%edx
  5344. To:
  5345. movl r/m,%eax <- Note the change in register
  5346. cltd
  5347. }
  5348. DebugMsg(SPeepholeOptimization + 'MovMovSar2MovCltd', p);
  5349. AllocRegBetween(NR_EAX, p, hp1, UsedRegs);
  5350. taicpu(p).loadreg(1, NR_EAX);
  5351. taicpu(hp1).opcode := A_CDQ;
  5352. taicpu(hp1).clearop(1);
  5353. taicpu(hp1).clearop(0);
  5354. taicpu(hp1).ops:=0;
  5355. RemoveInstruction(hp2);
  5356. (*
  5357. {$ifdef x86_64}
  5358. end
  5359. else if MatchOperand(taicpu(hp2).oper[1]^, NR_RDX) and
  5360. { This code sequence does not get generated - however it might become useful
  5361. if and when 128-bit signed integer types make an appearance, so the code
  5362. is kept here for when it is eventually needed. [Kit] }
  5363. (
  5364. (
  5365. (taicpu(hp1).oper[1]^.reg = NR_RAX) and
  5366. (
  5367. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) or
  5368. MatchOperand(taicpu(hp1).oper[0]^, NR_RDX)
  5369. )
  5370. ) or
  5371. (
  5372. (taicpu(hp1).oper[1]^.reg = NR_RDX) and
  5373. (
  5374. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) or
  5375. MatchOperand(taicpu(hp1).oper[0]^, NR_RAX)
  5376. )
  5377. )
  5378. ) and
  5379. GetNextInstruction(hp1, hp2) and
  5380. MatchInstruction(hp2, A_SAR, [S_Q]) and
  5381. MatchOperand(taicpu(hp2).oper[0]^, 63) and
  5382. MatchOperand(taicpu(hp2).oper[1]^, NR_RDX) then
  5383. begin
  5384. { Change:
  5385. movq r/m,%rdx movq r/m,%rax movq r/m,%rdx movq r/m,%rax
  5386. movq %rdx,%rax or movq %rax,%rdx or movq r/m,%rax or movq r/m,%rdx
  5387. sarq $63,%rdx sarq $63,%rdx sarq $63,%rdx sarq $63,%rdx
  5388. To:
  5389. movq r/m,%rax <- Note the change in register
  5390. cqto
  5391. }
  5392. DebugMsg(SPeepholeOptimization + 'MovMovSar2MovCqto', p);
  5393. AllocRegBetween(NR_RAX, p, hp1, UsedRegs);
  5394. taicpu(p).loadreg(1, NR_RAX);
  5395. taicpu(hp1).opcode := A_CQO;
  5396. taicpu(hp1).clearop(1);
  5397. taicpu(hp1).clearop(0);
  5398. taicpu(hp1).ops:=0;
  5399. RemoveInstruction(hp2);
  5400. {$endif x86_64}
  5401. *)
  5402. end;
  5403. end;
  5404. {$ifdef x86_64}
  5405. end
  5406. else if (taicpu(p).opsize = S_L) and
  5407. (taicpu(p).oper[1]^.typ = top_reg) and
  5408. (
  5409. MatchInstruction(hp1, A_MOV,[]) and
  5410. (taicpu(hp1).opsize = S_L) and
  5411. (taicpu(hp1).oper[1]^.typ = top_reg)
  5412. ) and (
  5413. GetNextInstruction(hp1, hp2) and
  5414. (tai(hp2).typ=ait_instruction) and
  5415. (taicpu(hp2).opsize = S_Q) and
  5416. (
  5417. (
  5418. MatchInstruction(hp2, A_ADD,[]) and
  5419. (taicpu(hp2).opsize = S_Q) and
  5420. (taicpu(hp2).oper[0]^.typ = top_reg) and (taicpu(hp2).oper[1]^.typ = top_reg) and
  5421. (
  5422. (
  5423. (getsupreg(taicpu(hp2).oper[0]^.reg) = getsupreg(taicpu(p).oper[1]^.reg)) and
  5424. (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg))
  5425. ) or (
  5426. (getsupreg(taicpu(hp2).oper[0]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
  5427. (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg))
  5428. )
  5429. )
  5430. ) or (
  5431. MatchInstruction(hp2, A_LEA,[]) and
  5432. (taicpu(hp2).oper[0]^.ref^.offset = 0) and
  5433. (taicpu(hp2).oper[0]^.ref^.scalefactor <= 1) and
  5434. (
  5435. (
  5436. (getsupreg(taicpu(hp2).oper[0]^.ref^.base) = getsupreg(taicpu(p).oper[1]^.reg)) and
  5437. (getsupreg(taicpu(hp2).oper[0]^.ref^.index) = getsupreg(taicpu(hp1).oper[1]^.reg))
  5438. ) or (
  5439. (getsupreg(taicpu(hp2).oper[0]^.ref^.base) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
  5440. (getsupreg(taicpu(hp2).oper[0]^.ref^.index) = getsupreg(taicpu(p).oper[1]^.reg))
  5441. )
  5442. ) and (
  5443. (
  5444. (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg))
  5445. ) or (
  5446. (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg))
  5447. )
  5448. )
  5449. )
  5450. )
  5451. ) and (
  5452. GetNextInstruction(hp2, hp3) and
  5453. MatchInstruction(hp3, A_SHR,[]) and
  5454. (taicpu(hp3).opsize = S_Q) and
  5455. (taicpu(hp3).oper[0]^.typ = top_const) and (taicpu(hp2).oper[1]^.typ = top_reg) and
  5456. (taicpu(hp3).oper[0]^.val = 1) and
  5457. (taicpu(hp3).oper[1]^.reg = taicpu(hp2).oper[1]^.reg)
  5458. ) then
  5459. begin
  5460. { Change movl x, reg1d movl x, reg1d
  5461. movl y, reg2d movl y, reg2d
  5462. addq reg2q,reg1q or leaq (reg1q,reg2q),reg1q
  5463. shrq $1, reg1q shrq $1, reg1q
  5464. ( reg1d and reg2d can be switched around in the first two instructions )
  5465. To movl x, reg1d
  5466. addl y, reg1d
  5467. rcrl $1, reg1d
  5468. This corresponds to the common expression (x + y) shr 1, where
  5469. x and y are Cardinals (replacing "shr 1" with "div 2" produces
  5470. smaller code, but won't account for x + y causing an overflow). [Kit]
  5471. }
  5472. if (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) then
  5473. { Change first MOV command to have the same register as the final output }
  5474. taicpu(p).oper[1]^.reg := taicpu(hp1).oper[1]^.reg
  5475. else
  5476. taicpu(hp1).oper[1]^.reg := taicpu(p).oper[1]^.reg;
  5477. { Change second MOV command to an ADD command. This is easier than
  5478. converting the existing command because it means we don't have to
  5479. touch 'y', which might be a complicated reference, and also the
  5480. fact that the third command might either be ADD or LEA. [Kit] }
  5481. taicpu(hp1).opcode := A_ADD;
  5482. { Delete old ADD/LEA instruction }
  5483. RemoveInstruction(hp2);
  5484. { Convert "shrq $1, reg1q" to "rcr $1, reg1d" }
  5485. taicpu(hp3).opcode := A_RCR;
  5486. taicpu(hp3).changeopsize(S_L);
  5487. setsubreg(taicpu(hp3).oper[1]^.reg, R_SUBD);
  5488. {$endif x86_64}
  5489. end;
  5490. end;
  5491. function TX86AsmOptimizer.OptPass2Movx(var p : tai) : boolean;
  5492. var
  5493. ThisReg: TRegister;
  5494. MinSize, MaxSize, TrySmaller, TargetSize: TOpSize;
  5495. TargetSubReg: TSubRegister;
  5496. hp1, hp2: tai;
  5497. RegInUse, RegChanged, p_removed: Boolean;
  5498. { Store list of found instructions so we don't have to call
  5499. GetNextInstructionUsingReg multiple times }
  5500. InstrList: array of taicpu;
  5501. InstrMax, Index: Integer;
  5502. UpperLimit, TrySmallerLimit: TCgInt;
  5503. PreMessage: string;
  5504. { Data flow analysis }
  5505. TestValMin, TestValMax: TCgInt;
  5506. SmallerOverflow: Boolean;
  5507. begin
  5508. Result := False;
  5509. p_removed := False;
  5510. { This is anything but quick! }
  5511. if not(cs_opt_level2 in current_settings.optimizerswitches) then
  5512. Exit;
  5513. SetLength(InstrList, 0);
  5514. InstrMax := -1;
  5515. ThisReg := taicpu(p).oper[1]^.reg;
  5516. case taicpu(p).opsize of
  5517. S_BW, S_BL:
  5518. begin
  5519. {$if defined(i386) or defined(i8086)}
  5520. { If the target size is 8-bit, make sure we can actually encode it }
  5521. if not (GetSupReg(ThisReg) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX]) then
  5522. Exit;
  5523. {$endif i386 or i8086}
  5524. UpperLimit := $FF;
  5525. MinSize := S_B;
  5526. if taicpu(p).opsize = S_BW then
  5527. MaxSize := S_W
  5528. else
  5529. MaxSize := S_L;
  5530. end;
  5531. S_WL:
  5532. begin
  5533. UpperLimit := $FFFF;
  5534. MinSize := S_W;
  5535. MaxSize := S_L;
  5536. end
  5537. else
  5538. InternalError(2020112301);
  5539. end;
  5540. TestValMin := 0;
  5541. TestValMax := UpperLimit;
  5542. TrySmallerLimit := UpperLimit;
  5543. TrySmaller := S_NO;
  5544. SmallerOverflow := False;
  5545. RegChanged := False;
  5546. hp1 := p;
  5547. while GetNextInstructionUsingReg(hp1, hp1, ThisReg) and
  5548. (hp1.typ = ait_instruction) and
  5549. (
  5550. { Under -O1 and -O2, GetNextInstructionUsingReg may return an
  5551. instruction that doesn't actually contain ThisReg }
  5552. (cs_opt_level3 in current_settings.optimizerswitches) or
  5553. RegInInstruction(ThisReg, hp1)
  5554. ) do
  5555. begin
  5556. case taicpu(hp1).opcode of
  5557. A_INC,A_DEC:
  5558. begin
  5559. { Has to be an exact match on the register }
  5560. if not MatchOperand(taicpu(hp1).oper[0]^, ThisReg) then
  5561. Break;
  5562. if taicpu(hp1).opcode = A_INC then
  5563. begin
  5564. Inc(TestValMin);
  5565. Inc(TestValMax);
  5566. end
  5567. else
  5568. begin
  5569. Dec(TestValMin);
  5570. Dec(TestValMax);
  5571. end;
  5572. end;
  5573. A_CMP:
  5574. begin
  5575. if (taicpu(hp1).oper[1]^.typ <> top_reg) or
  5576. { Has to be an exact match on the register }
  5577. (taicpu(hp1).oper[1]^.reg <> ThisReg) or
  5578. (taicpu(hp1).oper[0]^.typ <> top_const) or
  5579. { Make sure the comparison value is not smaller than the
  5580. smallest allowed signed value for the minimum size (e.g.
  5581. -128 for 8-bit) }
  5582. not (
  5583. ((taicpu(hp1).oper[0]^.val and UpperLimit) = taicpu(hp1).oper[0]^.val) or
  5584. { Is it in the negative range? }
  5585. (((not taicpu(hp1).oper[0]^.val) and (UpperLimit shr 1)) = (not taicpu(hp1).oper[0]^.val))
  5586. ) then
  5587. Break;
  5588. TestValMin := TestValMin - taicpu(hp1).oper[0]^.val;
  5589. TestValMax := TestValMax - taicpu(hp1).oper[0]^.val;
  5590. if (TestValMin < TrySmallerLimit) or (TestValMax < TrySmallerLimit) or
  5591. (TestValMin > UpperLimit) or (TestValMax > UpperLimit) then
  5592. { Overflow }
  5593. Break;
  5594. { Check to see if the active register is used afterwards }
  5595. TransferUsedRegs(TmpUsedRegs);
  5596. IncludeRegInUsedRegs(ThisReg, TmpUsedRegs);
  5597. if not RegUsedAfterInstruction(ThisReg, hp1, TmpUsedRegs) then
  5598. begin
  5599. case MinSize of
  5600. S_B:
  5601. TargetSubReg := R_SUBL;
  5602. S_W:
  5603. TargetSubReg := R_SUBW;
  5604. else
  5605. InternalError(2021051002);
  5606. end;
  5607. { Update the register to its new size }
  5608. setsubreg(ThisReg, TargetSubReg);
  5609. taicpu(hp1).oper[1]^.reg := ThisReg;
  5610. taicpu(hp1).opsize := MinSize;
  5611. { Convert the input MOVZX to a MOV }
  5612. if (taicpu(p).oper[0]^.typ = top_reg) and
  5613. SuperRegistersEqual(taicpu(p).oper[0]^.reg, ThisReg) then
  5614. begin
  5615. { Or remove it completely! }
  5616. DebugMsg(SPeepholeOptimization + 'Movzx2Nop 1a', p);
  5617. RemoveCurrentP(p);
  5618. p_removed := True;
  5619. end
  5620. else
  5621. begin
  5622. DebugMsg(SPeepholeOptimization + 'Movzx2Mov 1a', p);
  5623. taicpu(p).opcode := A_MOV;
  5624. taicpu(p).oper[1]^.reg := ThisReg;
  5625. taicpu(p).opsize := MinSize;
  5626. end;
  5627. if (InstrMax >= 0) then
  5628. begin
  5629. for Index := 0 to InstrMax do
  5630. begin
  5631. { If p_removed is true, then the original MOV/Z was removed
  5632. and removing the AND instruction may not be safe if it
  5633. appears first }
  5634. if (InstrList[Index].oper[InstrList[Index].ops - 1]^.typ <> top_reg) then
  5635. InternalError(2020112311);
  5636. if InstrList[Index].oper[0]^.typ = top_reg then
  5637. InstrList[Index].oper[0]^.reg := ThisReg;
  5638. InstrList[Index].oper[InstrList[Index].ops - 1]^.reg := ThisReg;
  5639. InstrList[Index].opsize := MinSize;
  5640. end;
  5641. end;
  5642. Result := True;
  5643. Exit;
  5644. end;
  5645. end;
  5646. { OR and XOR are not included because they can too easily fool
  5647. the data flow analysis (they can cause non-linear behaviour) }
  5648. A_ADD,A_SUB,A_AND,A_SHL,A_SHR:
  5649. begin
  5650. if
  5651. (taicpu(hp1).oper[1]^.typ <> top_reg) or
  5652. { Has to be an exact match on the register }
  5653. (taicpu(hp1).oper[1]^.reg <> ThisReg) or not
  5654. (
  5655. (
  5656. (taicpu(hp1).oper[0]^.typ = top_const) and
  5657. (
  5658. (
  5659. (taicpu(hp1).opcode = A_SHL) and
  5660. (
  5661. ((MinSize = S_B) and (taicpu(hp1).oper[0]^.val < 8)) or
  5662. ((MinSize = S_W) and (taicpu(hp1).oper[0]^.val < 16)) or
  5663. ((MinSize = S_L) and (taicpu(hp1).oper[0]^.val < 32))
  5664. )
  5665. ) or (
  5666. (taicpu(hp1).opcode <> A_SHL) and
  5667. (
  5668. ((taicpu(hp1).oper[0]^.val and UpperLimit) = taicpu(hp1).oper[0]^.val) or
  5669. { Is it in the negative range? }
  5670. (((not taicpu(hp1).oper[0]^.val) and (UpperLimit shr 1)) = (not taicpu(hp1).oper[0]^.val))
  5671. )
  5672. )
  5673. )
  5674. ) or (
  5675. MatchOperand(taicpu(hp1).oper[0]^, taicpu(hp1).oper[1]^.reg) and
  5676. ((taicpu(hp1).opcode = A_ADD) or (taicpu(hp1).opcode = A_AND) or (taicpu(hp1).opcode = A_SUB))
  5677. )
  5678. ) then
  5679. Break;
  5680. case taicpu(hp1).opcode of
  5681. A_ADD:
  5682. if (taicpu(hp1).oper[0]^.typ = top_reg) then
  5683. begin
  5684. TestValMin := TestValMin * 2;
  5685. TestValMax := TestValMax * 2;
  5686. end
  5687. else
  5688. begin
  5689. TestValMin := TestValMin + taicpu(hp1).oper[0]^.val;
  5690. TestValMax := TestValMax + taicpu(hp1).oper[0]^.val;
  5691. end;
  5692. A_SUB:
  5693. if (taicpu(hp1).oper[0]^.typ = top_reg) then
  5694. begin
  5695. TestValMin := 0;
  5696. TestValMax := 0;
  5697. end
  5698. else
  5699. begin
  5700. TestValMin := TestValMin - taicpu(hp1).oper[0]^.val;
  5701. TestValMax := TestValMax - taicpu(hp1).oper[0]^.val;
  5702. end;
  5703. A_AND:
  5704. if (taicpu(hp1).oper[0]^.typ = top_const) then
  5705. begin
  5706. { we might be able to go smaller if AND appears first }
  5707. if InstrMax = -1 then
  5708. case MinSize of
  5709. S_B:
  5710. ;
  5711. S_W:
  5712. if ((taicpu(hp1).oper[0]^.val and $FF) = taicpu(hp1).oper[0]^.val) or
  5713. ((not(taicpu(hp1).oper[0]^.val) and $7F) = (not taicpu(hp1).oper[0]^.val)) then
  5714. begin
  5715. TrySmaller := S_B;
  5716. TrySmallerLimit := $FF;
  5717. end;
  5718. S_L:
  5719. if ((taicpu(hp1).oper[0]^.val and $FF) = taicpu(hp1).oper[0]^.val) or
  5720. ((not(taicpu(hp1).oper[0]^.val) and $7F) = (not taicpu(hp1).oper[0]^.val)) then
  5721. begin
  5722. TrySmaller := S_B;
  5723. TrySmallerLimit := $FF;
  5724. end
  5725. else if ((taicpu(hp1).oper[0]^.val and $FFFF) = taicpu(hp1).oper[0]^.val) or
  5726. ((not(taicpu(hp1).oper[0]^.val) and $7FFF) = (not taicpu(hp1).oper[0]^.val)) then
  5727. begin
  5728. TrySmaller := S_W;
  5729. TrySmallerLimit := $FFFF;
  5730. end;
  5731. else
  5732. InternalError(2020112320);
  5733. end;
  5734. TestValMin := TestValMin and taicpu(hp1).oper[0]^.val;
  5735. TestValMax := TestValMax and taicpu(hp1).oper[0]^.val;
  5736. end;
  5737. A_SHL:
  5738. begin
  5739. TestValMin := TestValMin shl taicpu(hp1).oper[0]^.val;
  5740. TestValMax := TestValMax shl taicpu(hp1).oper[0]^.val;
  5741. end;
  5742. A_SHR:
  5743. begin
  5744. { we might be able to go smaller if SHR appears first }
  5745. if InstrMax = -1 then
  5746. case MinSize of
  5747. S_B:
  5748. ;
  5749. S_W:
  5750. if (taicpu(hp1).oper[0]^.val >= 8) then
  5751. begin
  5752. TrySmaller := S_B;
  5753. TrySmallerLimit := $FF;
  5754. end;
  5755. S_L:
  5756. if (taicpu(hp1).oper[0]^.val >= 24) then
  5757. begin
  5758. TrySmaller := S_B;
  5759. TrySmallerLimit := $FF;
  5760. end
  5761. else if (taicpu(hp1).oper[0]^.val >= 16) then
  5762. begin
  5763. TrySmaller := S_W;
  5764. TrySmallerLimit := $FFFF;
  5765. end;
  5766. else
  5767. InternalError(2020112321);
  5768. end;
  5769. TestValMin := TestValMin shr taicpu(hp1).oper[0]^.val;
  5770. TestValMax := TestValMax shr taicpu(hp1).oper[0]^.val;
  5771. end;
  5772. else
  5773. InternalError(2020112303);
  5774. end;
  5775. end;
  5776. (*
  5777. A_IMUL:
  5778. case taicpu(hp1).ops of
  5779. 2:
  5780. begin
  5781. if not MatchOpType(hp1, top_reg, top_reg) or
  5782. { Has to be an exact match on the register }
  5783. (taicpu(hp1).oper[0]^.reg <> ThisReg) or
  5784. (taicpu(hp1).oper[1]^.reg <> ThisReg) then
  5785. Break;
  5786. TestValMin := TestValMin * TestValMin;
  5787. TestValMax := TestValMax * TestValMax;
  5788. end;
  5789. 3:
  5790. begin
  5791. if not MatchOpType(hp1, top_const, top_reg, top_reg) or
  5792. { Has to be an exact match on the register }
  5793. (taicpu(hp1).oper[1]^.reg <> ThisReg) or
  5794. (taicpu(hp1).oper[2]^.reg <> ThisReg) or
  5795. ((taicpu(hp1).oper[0]^.val and UpperLimit) = taicpu(hp1).oper[0]^.val) or
  5796. { Is it in the negative range? }
  5797. (((not taicpu(hp1).oper[0]^.val) and (UpperLimit shr 1)) = (not taicpu(hp1).oper[0]^.val)) then
  5798. Break;
  5799. TestValMin := TestValMin * taicpu(hp1).oper[0]^.val;
  5800. TestValMax := TestValMax * taicpu(hp1).oper[0]^.val;
  5801. end;
  5802. else
  5803. Break;
  5804. end;
  5805. A_IDIV:
  5806. case taicpu(hp1).ops of
  5807. 3:
  5808. begin
  5809. if not MatchOpType(hp1, top_const, top_reg, top_reg) or
  5810. { Has to be an exact match on the register }
  5811. (taicpu(hp1).oper[1]^.reg <> ThisReg) or
  5812. (taicpu(hp1).oper[2]^.reg <> ThisReg) or
  5813. ((taicpu(hp1).oper[0]^.val and UpperLimit) = taicpu(hp1).oper[0]^.val) or
  5814. { Is it in the negative range? }
  5815. (((not taicpu(hp1).oper[0]^.val) and (UpperLimit shr 1)) = (not taicpu(hp1).oper[0]^.val)) then
  5816. Break;
  5817. TestValMin := TestValMin div taicpu(hp1).oper[0]^.val;
  5818. TestValMax := TestValMax div taicpu(hp1).oper[0]^.val;
  5819. end;
  5820. else
  5821. Break;
  5822. end;
  5823. *)
  5824. A_MOVZX:
  5825. begin
  5826. if not MatchOpType(taicpu(hp1), top_reg, top_reg) then
  5827. Break;
  5828. if not SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, ThisReg) then
  5829. begin
  5830. { Because hp1 was obtained via GetNextInstructionUsingReg
  5831. and ThisReg doesn't appear in the first operand, it
  5832. must appear in the second operand and hence gets
  5833. overwritten }
  5834. if (InstrMax = -1) and
  5835. Reg1WriteOverwritesReg2Entirely(taicpu(hp1).oper[1]^.reg, ThisReg) then
  5836. begin
  5837. { The two MOVZX instructions are adjacent, so remove the first one }
  5838. DebugMsg(SPeepholeOptimization + 'Movzx2Nop 5', p);
  5839. RemoveCurrentP(p);
  5840. Result := True;
  5841. Exit;
  5842. end;
  5843. Break;
  5844. end;
  5845. { The objective here is to try to find a combination that
  5846. removes one of the MOV/Z instructions. }
  5847. case taicpu(hp1).opsize of
  5848. S_WL:
  5849. if (MinSize in [S_B, S_W]) then
  5850. begin
  5851. TargetSize := S_L;
  5852. TargetSubReg := R_SUBD;
  5853. end
  5854. else if ((TrySmaller in [S_B, S_W]) and not SmallerOverflow) then
  5855. begin
  5856. TargetSize := TrySmaller;
  5857. if TrySmaller = S_B then
  5858. TargetSubReg := R_SUBL
  5859. else
  5860. TargetSubReg := R_SUBW;
  5861. end
  5862. else
  5863. Break;
  5864. S_BW:
  5865. if (MinSize in [S_B, S_W]) then
  5866. begin
  5867. TargetSize := S_W;
  5868. TargetSubReg := R_SUBW;
  5869. end
  5870. else if ((TrySmaller = S_B) and not SmallerOverflow) then
  5871. begin
  5872. TargetSize := S_B;
  5873. TargetSubReg := R_SUBL;
  5874. end
  5875. else
  5876. Break;
  5877. S_BL:
  5878. if (MinSize in [S_B, S_W]) then
  5879. begin
  5880. TargetSize := S_L;
  5881. TargetSubReg := R_SUBD;
  5882. end
  5883. else if ((TrySmaller = S_B) and not SmallerOverflow) then
  5884. begin
  5885. TargetSize := S_B;
  5886. TargetSubReg := R_SUBL;
  5887. end
  5888. else
  5889. Break;
  5890. else
  5891. InternalError(2020112302);
  5892. end;
  5893. { Update the register to its new size }
  5894. setsubreg(ThisReg, TargetSubReg);
  5895. if TargetSize = MinSize then
  5896. begin
  5897. { Convert the input MOVZX to a MOV }
  5898. if (taicpu(p).oper[0]^.typ = top_reg) and
  5899. SuperRegistersEqual(taicpu(p).oper[0]^.reg, ThisReg) then
  5900. begin
  5901. { Or remove it completely! }
  5902. DebugMsg(SPeepholeOptimization + 'Movzx2Nop 1', p);
  5903. RemoveCurrentP(p);
  5904. p_removed := True;
  5905. end
  5906. else
  5907. begin
  5908. DebugMsg(SPeepholeOptimization + 'Movzx2Mov 1', p);
  5909. taicpu(p).opcode := A_MOV;
  5910. taicpu(p).oper[1]^.reg := ThisReg;
  5911. taicpu(p).opsize := TargetSize;
  5912. end;
  5913. Result := True;
  5914. end
  5915. else if TargetSize <> MaxSize then
  5916. begin
  5917. case MaxSize of
  5918. S_L:
  5919. if TargetSize = S_W then
  5920. begin
  5921. DebugMsg(SPeepholeOptimization + 'movzbl2movzbw', p);
  5922. taicpu(p).opsize := S_BW;
  5923. taicpu(p).oper[1]^.reg := ThisReg;
  5924. Result := True;
  5925. end
  5926. else
  5927. InternalError(2020112341);
  5928. S_W:
  5929. if TargetSize = S_L then
  5930. begin
  5931. DebugMsg(SPeepholeOptimization + 'movzbw2movzbl', p);
  5932. taicpu(p).opsize := S_BL;
  5933. taicpu(p).oper[1]^.reg := ThisReg;
  5934. Result := True;
  5935. end
  5936. else
  5937. InternalError(2020112342);
  5938. else
  5939. ;
  5940. end;
  5941. end;
  5942. if (MaxSize = TargetSize) or
  5943. ((TargetSize = S_L) and (taicpu(hp1).opsize in [S_L, S_BL, S_WL])) or
  5944. ((TargetSize = S_W) and (taicpu(hp1).opsize in [S_W, S_BW])) then
  5945. begin
  5946. { Convert the output MOVZX to a MOV }
  5947. if SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, ThisReg) then
  5948. begin
  5949. { Or remove it completely! }
  5950. DebugMsg(SPeepholeOptimization + 'Movzx2Nop 2', hp1);
  5951. { Be careful; if p = hp1 and p was also removed, p
  5952. will become a dangling pointer }
  5953. if p = hp1 then
  5954. RemoveCurrentp(p) { p = hp1 and will then become the next instruction }
  5955. else
  5956. RemoveInstruction(hp1);
  5957. end
  5958. else
  5959. begin
  5960. taicpu(hp1).opcode := A_MOV;
  5961. taicpu(hp1).oper[0]^.reg := ThisReg;
  5962. taicpu(hp1).opsize := TargetSize;
  5963. { Check to see if the active register is used afterwards;
  5964. if not, we can change it and make a saving. }
  5965. RegInUse := False;
  5966. TransferUsedRegs(TmpUsedRegs);
  5967. { The target register may be marked as in use to cross
  5968. a jump to a distant label, so exclude it }
  5969. ExcludeRegFromUsedRegs(taicpu(hp1).oper[1]^.reg, TmpUsedRegs);
  5970. hp2 := p;
  5971. repeat
  5972. UpdateUsedRegs(TmpUsedRegs, tai(hp2.next));
  5973. { Explicitly check for the excluded register (don't include the first
  5974. instruction as it may be reading from here }
  5975. if ((p <> hp2) and (RegInInstruction(taicpu(hp1).oper[1]^.reg, hp2))) or
  5976. RegInUsedRegs(taicpu(hp1).oper[1]^.reg, TmpUsedRegs) then
  5977. begin
  5978. RegInUse := True;
  5979. Break;
  5980. end;
  5981. if not GetNextInstruction(hp2, hp2) then
  5982. InternalError(2020112340);
  5983. until (hp2 = hp1);
  5984. if not RegInUse and not RegUsedAfterInstruction(ThisReg, hp1, TmpUsedRegs) then
  5985. begin
  5986. DebugMsg(SPeepholeOptimization + 'Simplified register usage so ' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' = ' + debug_regname(taicpu(p).oper[1]^.reg), p);
  5987. ThisReg := taicpu(hp1).oper[1]^.reg;
  5988. RegChanged := True;
  5989. TransferUsedRegs(TmpUsedRegs);
  5990. AllocRegBetween(ThisReg, p, hp1, TmpUsedRegs);
  5991. DebugMsg(SPeepholeOptimization + 'Movzx2Nop 3', hp1);
  5992. if p = hp1 then
  5993. RemoveCurrentp(p) { p = hp1 and will then become the next instruction }
  5994. else
  5995. RemoveInstruction(hp1);
  5996. { Instruction will become "mov %reg,%reg" }
  5997. if not p_removed and (taicpu(p).opcode = A_MOV) and
  5998. MatchOperand(taicpu(p).oper[0]^, ThisReg) then
  5999. begin
  6000. DebugMsg(SPeepholeOptimization + 'Movzx2Nop 6', p);
  6001. RemoveCurrentP(p);
  6002. p_removed := True;
  6003. end
  6004. else
  6005. taicpu(p).oper[1]^.reg := ThisReg;
  6006. Result := True;
  6007. end
  6008. else
  6009. DebugMsg(SPeepholeOptimization + 'Movzx2Mov 2', hp1);
  6010. end;
  6011. end
  6012. else
  6013. InternalError(2020112330);
  6014. { Now go through every instruction we found and change the
  6015. size. If TargetSize = MaxSize, then almost no changes are
  6016. needed and Result can remain False if it hasn't been set
  6017. yet.
  6018. If RegChanged is True, then the register requires changing
  6019. and so the point about TargetSize = MaxSize doesn't apply. }
  6020. if ((TargetSize <> MaxSize) or RegChanged) and (InstrMax >= 0) then
  6021. begin
  6022. for Index := 0 to InstrMax do
  6023. begin
  6024. { If p_removed is true, then the original MOV/Z was removed
  6025. and removing the AND instruction may not be safe if it
  6026. appears first }
  6027. if (InstrList[Index].oper[InstrList[Index].ops - 1]^.typ <> top_reg) then
  6028. InternalError(2020112310);
  6029. if InstrList[Index].oper[0]^.typ = top_reg then
  6030. InstrList[Index].oper[0]^.reg := ThisReg;
  6031. InstrList[Index].oper[InstrList[Index].ops - 1]^.reg := ThisReg;
  6032. InstrList[Index].opsize := TargetSize;
  6033. end;
  6034. Result := True;
  6035. end;
  6036. Exit;
  6037. end;
  6038. else
  6039. { This includes ADC, SBB, IDIV and SAR }
  6040. Break;
  6041. end;
  6042. if (TestValMin < 0) or (TestValMax < 0) or
  6043. (TestValMin > UpperLimit) or (TestValMax > UpperLimit) then
  6044. { Overflow }
  6045. Break
  6046. else if not SmallerOverflow and (TrySmaller <> S_NO) and
  6047. ((TestValMin > TrySmallerLimit) or (TestValMax > TrySmallerLimit)) then
  6048. SmallerOverflow := True;
  6049. { Contains highest index (so instruction count - 1) }
  6050. Inc(InstrMax);
  6051. if InstrMax > High(InstrList) then
  6052. SetLength(InstrList, InstrMax + LIST_STEP_SIZE);
  6053. InstrList[InstrMax] := taicpu(hp1);
  6054. end;
  6055. end;
  6056. function TX86AsmOptimizer.OptPass2Imul(var p : tai) : boolean;
  6057. var
  6058. hp1 : tai;
  6059. begin
  6060. Result:=false;
  6061. if (taicpu(p).ops >= 2) and
  6062. ((taicpu(p).oper[0]^.typ = top_const) or
  6063. ((taicpu(p).oper[0]^.typ = top_ref) and (taicpu(p).oper[0]^.ref^.refaddr=addr_full))) and
  6064. (taicpu(p).oper[1]^.typ = top_reg) and
  6065. ((taicpu(p).ops = 2) or
  6066. ((taicpu(p).oper[2]^.typ = top_reg) and
  6067. (taicpu(p).oper[2]^.reg = taicpu(p).oper[1]^.reg))) and
  6068. GetLastInstruction(p,hp1) and
  6069. MatchInstruction(hp1,A_MOV,[]) and
  6070. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  6071. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  6072. begin
  6073. TransferUsedRegs(TmpUsedRegs);
  6074. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,p,TmpUsedRegs)) or
  6075. ((taicpu(p).ops = 3) and (taicpu(p).oper[1]^.reg=taicpu(p).oper[2]^.reg)) then
  6076. { change
  6077. mov reg1,reg2
  6078. imul y,reg2 to imul y,reg1,reg2 }
  6079. begin
  6080. taicpu(p).ops := 3;
  6081. taicpu(p).loadreg(2,taicpu(p).oper[1]^.reg);
  6082. taicpu(p).loadreg(1,taicpu(hp1).oper[0]^.reg);
  6083. DebugMsg(SPeepholeOptimization + 'MovImul2Imul done',p);
  6084. RemoveInstruction(hp1);
  6085. result:=true;
  6086. end;
  6087. end;
  6088. end;
  6089. procedure TX86AsmOptimizer.ConvertJumpToRET(const p: tai; const ret_p: tai);
  6090. var
  6091. ThisLabel: TAsmLabel;
  6092. begin
  6093. ThisLabel := tasmlabel(taicpu(p).oper[0]^.ref^.symbol);
  6094. ThisLabel.decrefs;
  6095. taicpu(p).opcode := A_RET;
  6096. taicpu(p).is_jmp := false;
  6097. taicpu(p).ops := taicpu(ret_p).ops;
  6098. case taicpu(ret_p).ops of
  6099. 0:
  6100. taicpu(p).clearop(0);
  6101. 1:
  6102. taicpu(p).loadconst(0,taicpu(ret_p).oper[0]^.val);
  6103. else
  6104. internalerror(2016041301);
  6105. end;
  6106. { If the original label is now dead, it might turn out that the label
  6107. immediately follows p. As a result, everything beyond it, which will
  6108. be just some final register configuration and a RET instruction, is
  6109. now dead code. [Kit] }
  6110. { NOTE: This is much faster than introducing a OptPass2RET routine and
  6111. running RemoveDeadCodeAfterJump for each RET instruction, because
  6112. this optimisation rarely happens and most RETs appear at the end of
  6113. routines where there is nothing that can be stripped. [Kit] }
  6114. if not ThisLabel.is_used then
  6115. RemoveDeadCodeAfterJump(p);
  6116. end;
  6117. function TX86AsmOptimizer.OptPass2SETcc(var p: tai): boolean;
  6118. var
  6119. hp1,hp2,next: tai; SetC, JumpC: TAsmCond;
  6120. Unconditional, PotentialModified: Boolean;
  6121. OperPtr: POper;
  6122. NewRef: TReference;
  6123. InstrList: array of taicpu;
  6124. InstrMax, Index: Integer;
  6125. const
  6126. {$ifdef DEBUG_AOPTCPU}
  6127. SNoFlags: shortstring = ' so the flags aren''t modified';
  6128. {$else DEBUG_AOPTCPU}
  6129. SNoFlags = '';
  6130. {$endif DEBUG_AOPTCPU}
  6131. begin
  6132. Result:=false;
  6133. if MatchOpType(taicpu(p),top_reg) and GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) then
  6134. begin
  6135. if MatchInstruction(hp1, A_TEST, [S_B]) and
  6136. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  6137. (taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
  6138. (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
  6139. GetNextInstruction(hp1, hp2) and
  6140. MatchInstruction(hp2, A_Jcc, []) then
  6141. { Change from: To:
  6142. set(C) %reg j(~C) label
  6143. test %reg,%reg/cmp $0,%reg
  6144. je label
  6145. set(C) %reg j(C) label
  6146. test %reg,%reg/cmp $0,%reg
  6147. jne label
  6148. }
  6149. begin
  6150. { Before we do anything else, we need to check the instructions
  6151. in between SETcc and TEST to make sure they don't modify the
  6152. FLAGS register - if -O2 or under, there won't be any
  6153. instructions between SET and TEST }
  6154. TransferUsedRegs(TmpUsedRegs);
  6155. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  6156. if (cs_opt_level3 in current_settings.optimizerswitches) then
  6157. begin
  6158. next := p;
  6159. SetLength(InstrList, 0);
  6160. InstrMax := -1;
  6161. PotentialModified := False;
  6162. { Make a note of every instruction that modifies the FLAGS
  6163. register }
  6164. while GetNextInstruction(next, next) and (next <> hp1) do
  6165. begin
  6166. if next.typ <> ait_instruction then
  6167. { GetNextInstructionUsingReg should have returned False }
  6168. InternalError(2021051701);
  6169. if RegModifiedByInstruction(NR_DEFAULTFLAGS, next) then
  6170. begin
  6171. case taicpu(next).opcode of
  6172. A_SETcc,
  6173. A_CMOVcc,
  6174. A_Jcc:
  6175. begin
  6176. if PotentialModified then
  6177. { Not safe because the flags were modified earlier }
  6178. Exit
  6179. else
  6180. { Condition is the same as the initial SETcc, so this is safe
  6181. (don't add to instruction list though) }
  6182. Continue;
  6183. end;
  6184. A_ADD:
  6185. begin
  6186. if (taicpu(next).opsize = S_B) or
  6187. { LEA doesn't support 8-bit operands }
  6188. (taicpu(next).oper[1]^.typ <> top_reg) or
  6189. { Must write to a register }
  6190. (taicpu(next).oper[0]^.typ = top_ref) then
  6191. { Require a constant or a register }
  6192. Exit;
  6193. PotentialModified := True;
  6194. end;
  6195. A_SUB:
  6196. begin
  6197. if (taicpu(next).opsize = S_B) or
  6198. { LEA doesn't support 8-bit operands }
  6199. (taicpu(next).oper[1]^.typ <> top_reg) or
  6200. { Must write to a register }
  6201. (taicpu(next).oper[0]^.typ <> top_const) or
  6202. (taicpu(next).oper[0]^.val = $80000000) then
  6203. { Can't subtract a register with LEA - also
  6204. check that the value isn't -2^31, as this
  6205. can't be negated }
  6206. Exit;
  6207. PotentialModified := True;
  6208. end;
  6209. A_SAL,
  6210. A_SHL:
  6211. begin
  6212. if (taicpu(next).opsize = S_B) or
  6213. { LEA doesn't support 8-bit operands }
  6214. (taicpu(next).oper[1]^.typ <> top_reg) or
  6215. { Must write to a register }
  6216. (taicpu(next).oper[0]^.typ <> top_const) or
  6217. (taicpu(next).oper[0]^.val < 0) or
  6218. (taicpu(next).oper[0]^.val > 3) then
  6219. Exit;
  6220. PotentialModified := True;
  6221. end;
  6222. A_IMUL:
  6223. begin
  6224. if (taicpu(next).ops <> 3) or
  6225. (taicpu(next).oper[1]^.typ <> top_reg) or
  6226. { Must write to a register }
  6227. (taicpu(next).oper[2]^.val in [2,3,4,5,8,9]) then
  6228. { We can convert "imul x,%reg1,%reg2" (where x = 2, 4 or 8)
  6229. to "lea (%reg1,x),%reg2". If x = 3, 5 or 9, we can
  6230. change this to "lea (%reg1,%reg1,(x-1)),%reg2" }
  6231. Exit
  6232. else
  6233. PotentialModified := True;
  6234. end;
  6235. else
  6236. { Don't know how to change this, so abort }
  6237. Exit;
  6238. end;
  6239. { Contains highest index (so instruction count - 1) }
  6240. Inc(InstrMax);
  6241. if InstrMax > High(InstrList) then
  6242. SetLength(InstrList, InstrMax + LIST_STEP_SIZE);
  6243. InstrList[InstrMax] := taicpu(next);
  6244. end;
  6245. UpdateUsedRegs(TmpUsedRegs, tai(next.next));
  6246. end;
  6247. if not Assigned(next) or (next <> hp1) then
  6248. { It should be equal to hp1 }
  6249. InternalError(2021051702);
  6250. { Cycle through each instruction and check to see if we can
  6251. change them to versions that don't modify the flags }
  6252. if (InstrMax >= 0) then
  6253. begin
  6254. for Index := 0 to InstrMax do
  6255. case InstrList[Index].opcode of
  6256. A_ADD:
  6257. begin
  6258. DebugMsg(SPeepholeOptimization + 'ADD -> LEA' + SNoFlags, InstrList[Index]);
  6259. InstrList[Index].opcode := A_LEA;
  6260. reference_reset(NewRef, 1, []);
  6261. NewRef.base := InstrList[Index].oper[1]^.reg;
  6262. if InstrList[Index].oper[0]^.typ = top_reg then
  6263. begin
  6264. NewRef.index := InstrList[Index].oper[0]^.reg;
  6265. NewRef.scalefactor := 1;
  6266. end
  6267. else
  6268. NewRef.offset := InstrList[Index].oper[0]^.val;
  6269. InstrList[Index].loadref(0, NewRef);
  6270. end;
  6271. A_SUB:
  6272. begin
  6273. DebugMsg(SPeepholeOptimization + 'SUB -> LEA' + SNoFlags, InstrList[Index]);
  6274. InstrList[Index].opcode := A_LEA;
  6275. reference_reset(NewRef, 1, []);
  6276. NewRef.base := InstrList[Index].oper[1]^.reg;
  6277. NewRef.offset := -InstrList[Index].oper[0]^.val;
  6278. InstrList[Index].loadref(0, NewRef);
  6279. end;
  6280. A_SHL,
  6281. A_SAL:
  6282. begin
  6283. DebugMsg(SPeepholeOptimization + 'SHL -> LEA' + SNoFlags, InstrList[Index]);
  6284. InstrList[Index].opcode := A_LEA;
  6285. reference_reset(NewRef, 1, []);
  6286. NewRef.index := InstrList[Index].oper[1]^.reg;
  6287. NewRef.scalefactor := 1 shl (InstrList[Index].oper[0]^.val);
  6288. InstrList[Index].loadref(0, NewRef);
  6289. end;
  6290. A_IMUL:
  6291. begin
  6292. DebugMsg(SPeepholeOptimization + 'IMUL -> LEA' + SNoFlags, InstrList[Index]);
  6293. InstrList[Index].opcode := A_LEA;
  6294. reference_reset(NewRef, 1, []);
  6295. NewRef.index := InstrList[Index].oper[1]^.reg;
  6296. case InstrList[Index].oper[0]^.val of
  6297. 2, 4, 8:
  6298. NewRef.scalefactor := InstrList[Index].oper[0]^.val;
  6299. else {3, 5 and 9}
  6300. begin
  6301. NewRef.scalefactor := InstrList[Index].oper[0]^.val - 1;
  6302. NewRef.base := InstrList[Index].oper[1]^.reg;
  6303. end;
  6304. end;
  6305. InstrList[Index].loadref(0, NewRef);
  6306. end;
  6307. else
  6308. InternalError(2021051710);
  6309. end;
  6310. end;
  6311. { Mark the FLAGS register as used across this whole block }
  6312. AllocRegBetween(NR_DEFAULTFLAGS, p, hp1, UsedRegs);
  6313. end;
  6314. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  6315. JumpC := taicpu(hp2).condition;
  6316. Unconditional := False;
  6317. if conditions_equal(JumpC, C_E) then
  6318. SetC := inverse_cond(taicpu(p).condition)
  6319. else if conditions_equal(JumpC, C_NE) then
  6320. SetC := taicpu(p).condition
  6321. else
  6322. { We've got something weird here (and inefficent) }
  6323. begin
  6324. DebugMsg('DEBUG: Inefficient jump - check code generation', p);
  6325. SetC := C_NONE;
  6326. { JAE/JNB will always branch (use 'condition_in', since C_AE <> C_NB normally) }
  6327. if condition_in(C_AE, JumpC) then
  6328. Unconditional := True
  6329. else
  6330. { Not sure what to do with this jump - drop out }
  6331. Exit;
  6332. end;
  6333. RemoveInstruction(hp1);
  6334. if Unconditional then
  6335. MakeUnconditional(taicpu(hp2))
  6336. else
  6337. begin
  6338. if SetC = C_NONE then
  6339. InternalError(2018061402);
  6340. taicpu(hp2).SetCondition(SetC);
  6341. end;
  6342. if not RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp2, TmpUsedRegs) then
  6343. begin
  6344. RemoveCurrentp(p, hp2);
  6345. DebugMsg(SPeepholeOptimization + 'SETcc/TEST/Jcc -> Jcc',p);
  6346. end
  6347. else
  6348. DebugMsg(SPeepholeOptimization + 'SETcc/TEST/Jcc -> SETcc/Jcc',p);
  6349. Result := True;
  6350. end
  6351. else if
  6352. { Make sure the instructions are adjacent }
  6353. (
  6354. not (cs_opt_level3 in current_settings.optimizerswitches) or
  6355. GetNextInstruction(p, hp1)
  6356. ) and
  6357. MatchInstruction(hp1, A_MOV, [S_B]) and
  6358. { Writing to memory is allowed }
  6359. MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^.reg) then
  6360. begin
  6361. {
  6362. Watch out for sequences such as:
  6363. set(c)b %regb
  6364. movb %regb,(ref)
  6365. movb $0,1(ref)
  6366. movb $0,2(ref)
  6367. movb $0,3(ref)
  6368. Much more efficient to turn it into:
  6369. movl $0,%regl
  6370. set(c)b %regb
  6371. movl %regl,(ref)
  6372. Or:
  6373. set(c)b %regb
  6374. movzbl %regb,%regl
  6375. movl %regl,(ref)
  6376. }
  6377. if (taicpu(hp1).oper[1]^.typ = top_ref) and
  6378. GetNextInstruction(hp1, hp2) and
  6379. MatchInstruction(hp2, A_MOV, [S_B]) and
  6380. (taicpu(hp2).oper[1]^.typ = top_ref) and
  6381. CheckMemoryWrite(taicpu(hp1), taicpu(hp2)) then
  6382. begin
  6383. { Don't do anything else except set Result to True }
  6384. end
  6385. else
  6386. begin
  6387. if taicpu(p).oper[0]^.typ = top_reg then
  6388. begin
  6389. TransferUsedRegs(TmpUsedRegs);
  6390. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  6391. end;
  6392. { If it's not a register, it's a memory address }
  6393. if (taicpu(p).oper[0]^.typ <> top_reg) or RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp1, TmpUsedRegs) then
  6394. begin
  6395. { Even if the register is still in use, we can minimise the
  6396. pipeline stall by changing the MOV into another SETcc. }
  6397. taicpu(hp1).opcode := A_SETcc;
  6398. taicpu(hp1).condition := taicpu(p).condition;
  6399. if taicpu(hp1).oper[1]^.typ = top_ref then
  6400. begin
  6401. { Swapping the operand pointers like this is probably a
  6402. bit naughty, but it is far faster than using loadoper
  6403. to transfer the reference from oper[1] to oper[0] if
  6404. you take into account the extra procedure calls and
  6405. the memory allocation and deallocation required }
  6406. OperPtr := taicpu(hp1).oper[1];
  6407. taicpu(hp1).oper[1] := taicpu(hp1).oper[0];
  6408. taicpu(hp1).oper[0] := OperPtr;
  6409. end
  6410. else
  6411. taicpu(hp1).oper[0]^.reg := taicpu(hp1).oper[1]^.reg;
  6412. taicpu(hp1).clearop(1);
  6413. taicpu(hp1).ops := 1;
  6414. DebugMsg(SPeepholeOptimization + 'SETcc/Mov -> SETcc/SETcc',p);
  6415. end
  6416. else
  6417. begin
  6418. if taicpu(hp1).oper[1]^.typ = top_reg then
  6419. AllocRegBetween(taicpu(hp1).oper[1]^.reg,p,hp1,UsedRegs);
  6420. taicpu(p).loadoper(0, taicpu(hp1).oper[1]^);
  6421. RemoveInstruction(hp1);
  6422. DebugMsg(SPeepholeOptimization + 'SETcc/Mov -> SETcc',p);
  6423. end
  6424. end;
  6425. Result := True;
  6426. end;
  6427. end;
  6428. end;
  6429. function TX86AsmOptimizer.OptPass2Jmp(var p : tai) : boolean;
  6430. var
  6431. hp1: tai;
  6432. Count: Integer;
  6433. OrigLabel: TAsmLabel;
  6434. begin
  6435. result := False;
  6436. { Sometimes, the optimisations below can permit this }
  6437. RemoveDeadCodeAfterJump(p);
  6438. if (taicpu(p).oper[0]^.typ=top_ref) and (taicpu(p).oper[0]^.ref^.refaddr=addr_full) and (taicpu(p).oper[0]^.ref^.base=NR_NO) and
  6439. (taicpu(p).oper[0]^.ref^.index=NR_NO) and (taicpu(p).oper[0]^.ref^.symbol is tasmlabel) then
  6440. begin
  6441. OrigLabel := TAsmLabel(taicpu(p).oper[0]^.ref^.symbol);
  6442. { Also a side-effect of optimisations }
  6443. if CollapseZeroDistJump(p, OrigLabel) then
  6444. begin
  6445. Result := True;
  6446. Exit;
  6447. end;
  6448. hp1 := GetLabelWithSym(OrigLabel);
  6449. if (taicpu(p).condition=C_None) and assigned(hp1) and SkipLabels(hp1,hp1) and (hp1.typ = ait_instruction) then
  6450. begin
  6451. case taicpu(hp1).opcode of
  6452. A_RET:
  6453. {
  6454. change
  6455. jmp .L1
  6456. ...
  6457. .L1:
  6458. ret
  6459. into
  6460. ret
  6461. }
  6462. begin
  6463. ConvertJumpToRET(p, hp1);
  6464. result:=true;
  6465. end;
  6466. { Check any kind of direct assignment instruction }
  6467. A_MOV,
  6468. A_MOVD,
  6469. A_MOVQ,
  6470. A_MOVSX,
  6471. {$ifdef x86_64}
  6472. A_MOVSXD,
  6473. {$endif x86_64}
  6474. A_MOVZX,
  6475. A_MOVAPS,
  6476. A_MOVUPS,
  6477. A_MOVSD,
  6478. A_MOVAPD,
  6479. A_MOVUPD,
  6480. A_MOVDQA,
  6481. A_MOVDQU,
  6482. A_VMOVSS,
  6483. A_VMOVAPS,
  6484. A_VMOVUPS,
  6485. A_VMOVSD,
  6486. A_VMOVAPD,
  6487. A_VMOVUPD,
  6488. A_VMOVDQA,
  6489. A_VMOVDQU:
  6490. if ((current_settings.optimizerswitches * [cs_opt_level3, cs_opt_size]) <> [cs_opt_size]) and
  6491. CheckJumpMovTransferOpt(p, hp1, 0, Count) then
  6492. begin
  6493. Result := True;
  6494. Exit;
  6495. end;
  6496. else
  6497. ;
  6498. end;
  6499. end;
  6500. end;
  6501. end;
  6502. class function TX86AsmOptimizer.CanBeCMOV(p : tai) : boolean;
  6503. begin
  6504. CanBeCMOV:=assigned(p) and
  6505. MatchInstruction(p,A_MOV,[S_W,S_L,S_Q]) and
  6506. { we can't use cmov ref,reg because
  6507. ref could be nil and cmov still throws an exception
  6508. if ref=nil but the mov isn't done (FK)
  6509. or ((taicpu(p).oper[0]^.typ = top_ref) and
  6510. (taicpu(p).oper[0]^.ref^.refaddr = addr_no))
  6511. }
  6512. (taicpu(p).oper[1]^.typ = top_reg) and
  6513. (
  6514. (taicpu(p).oper[0]^.typ = top_reg) or
  6515. { allow references, but only pure symbols or got rel. addressing with RIP as based,
  6516. it is not expected that this can cause a seg. violation }
  6517. (
  6518. (taicpu(p).oper[0]^.typ = top_ref) and
  6519. IsRefSafe(taicpu(p).oper[0]^.ref)
  6520. )
  6521. );
  6522. end;
  6523. function TX86AsmOptimizer.OptPass2Jcc(var p : tai) : boolean;
  6524. var
  6525. hp1,hp2: tai;
  6526. {$ifndef i8086}
  6527. hp3,hp4,hpmov2, hp5: tai;
  6528. l : Longint;
  6529. condition : TAsmCond;
  6530. {$endif i8086}
  6531. carryadd_opcode : TAsmOp;
  6532. symbol: TAsmSymbol;
  6533. reg: tsuperregister;
  6534. increg, tmpreg: TRegister;
  6535. begin
  6536. result:=false;
  6537. if GetNextInstruction(p,hp1) and (hp1.typ=ait_instruction) then
  6538. begin
  6539. symbol := TAsmLabel(taicpu(p).oper[0]^.ref^.symbol);
  6540. if (
  6541. (
  6542. ((Taicpu(hp1).opcode=A_ADD) or (Taicpu(hp1).opcode=A_SUB)) and
  6543. MatchOptype(Taicpu(hp1),top_const,top_reg) and
  6544. (Taicpu(hp1).oper[0]^.val=1)
  6545. ) or
  6546. ((Taicpu(hp1).opcode=A_INC) or (Taicpu(hp1).opcode=A_DEC))
  6547. ) and
  6548. GetNextInstruction(hp1,hp2) and
  6549. SkipAligns(hp2, hp2) and
  6550. (hp2.typ = ait_label) and
  6551. (Tasmlabel(symbol) = Tai_label(hp2).labsym) then
  6552. { jb @@1 cmc
  6553. inc/dec operand --> adc/sbb operand,0
  6554. @@1:
  6555. ... and ...
  6556. jnb @@1
  6557. inc/dec operand --> adc/sbb operand,0
  6558. @@1: }
  6559. begin
  6560. if Taicpu(p).condition in [C_NAE,C_B,C_C] then
  6561. begin
  6562. case taicpu(hp1).opcode of
  6563. A_INC,
  6564. A_ADD:
  6565. carryadd_opcode:=A_ADC;
  6566. A_DEC,
  6567. A_SUB:
  6568. carryadd_opcode:=A_SBB;
  6569. else
  6570. InternalError(2021011001);
  6571. end;
  6572. Taicpu(p).clearop(0);
  6573. Taicpu(p).ops:=0;
  6574. Taicpu(p).is_jmp:=false;
  6575. Taicpu(p).opcode:=A_CMC;
  6576. Taicpu(p).condition:=C_NONE;
  6577. DebugMsg(SPeepholeOptimization+'JccAdd/Inc/Dec2CmcAdc/Sbb',p);
  6578. Taicpu(hp1).ops:=2;
  6579. if (Taicpu(hp1).opcode=A_ADD) or (Taicpu(hp1).opcode=A_SUB) then
  6580. Taicpu(hp1).loadoper(1,Taicpu(hp1).oper[1]^)
  6581. else
  6582. Taicpu(hp1).loadoper(1,Taicpu(hp1).oper[0]^);
  6583. Taicpu(hp1).loadconst(0,0);
  6584. Taicpu(hp1).opcode:=carryadd_opcode;
  6585. result:=true;
  6586. exit;
  6587. end
  6588. else if Taicpu(p).condition in [C_AE,C_NB,C_NC] then
  6589. begin
  6590. case taicpu(hp1).opcode of
  6591. A_INC,
  6592. A_ADD:
  6593. carryadd_opcode:=A_ADC;
  6594. A_DEC,
  6595. A_SUB:
  6596. carryadd_opcode:=A_SBB;
  6597. else
  6598. InternalError(2021011002);
  6599. end;
  6600. Taicpu(hp1).ops:=2;
  6601. DebugMsg(SPeepholeOptimization+'JccAdd/Inc/Dec2Adc/Sbb',p);
  6602. if (Taicpu(hp1).opcode=A_ADD) or (Taicpu(hp1).opcode=A_SUB) then
  6603. Taicpu(hp1).loadoper(1,Taicpu(hp1).oper[1]^)
  6604. else
  6605. Taicpu(hp1).loadoper(1,Taicpu(hp1).oper[0]^);
  6606. Taicpu(hp1).loadconst(0,0);
  6607. Taicpu(hp1).opcode:=carryadd_opcode;
  6608. RemoveCurrentP(p, hp1);
  6609. result:=true;
  6610. exit;
  6611. end
  6612. {
  6613. jcc @@1 setcc tmpreg
  6614. inc/dec/add/sub operand -> (movzx tmpreg)
  6615. @@1: add/sub tmpreg,operand
  6616. While this increases code size slightly, it makes the code much faster if the
  6617. jump is unpredictable
  6618. }
  6619. else if not(cs_opt_size in current_settings.optimizerswitches) then
  6620. begin
  6621. { search for an available register which is volatile }
  6622. for reg in tcpuregisterset do
  6623. begin
  6624. if
  6625. {$if defined(i386) or defined(i8086)}
  6626. { Only use registers whose lowest 8-bits can Be accessed }
  6627. (reg in [RS_EAX,RS_EBX,RS_ECX,RS_EDX]) and
  6628. {$endif i386 or i8086}
  6629. (reg in paramanager.get_volatile_registers_int(current_procinfo.procdef.proccalloption)) and
  6630. not(reg in UsedRegs[R_INTREGISTER].GetUsedRegs)
  6631. { We don't need to check if tmpreg is in hp1 or not, because
  6632. it will be marked as in use at p (if not, this is
  6633. indictive of a compiler bug). }
  6634. then
  6635. begin
  6636. TAsmLabel(symbol).decrefs;
  6637. increg := newreg(R_INTREGISTER,reg,R_SUBL);
  6638. Taicpu(p).clearop(0);
  6639. Taicpu(p).ops:=1;
  6640. Taicpu(p).is_jmp:=false;
  6641. Taicpu(p).opcode:=A_SETcc;
  6642. DebugMsg(SPeepholeOptimization+'JccAdd2SetccAdd',p);
  6643. Taicpu(p).condition:=inverse_cond(Taicpu(p).condition);
  6644. Taicpu(p).loadreg(0,increg);
  6645. if getsubreg(Taicpu(hp1).oper[1]^.reg)<>R_SUBL then
  6646. begin
  6647. case getsubreg(Taicpu(hp1).oper[1]^.reg) of
  6648. R_SUBW:
  6649. begin
  6650. tmpreg := newreg(R_INTREGISTER,reg,R_SUBW);
  6651. hp2:=Taicpu.op_reg_reg(A_MOVZX,S_BW,increg,tmpreg);
  6652. end;
  6653. R_SUBD:
  6654. begin
  6655. tmpreg := newreg(R_INTREGISTER,reg,R_SUBD);
  6656. hp2:=Taicpu.op_reg_reg(A_MOVZX,S_BL,increg,tmpreg);
  6657. end;
  6658. {$ifdef x86_64}
  6659. R_SUBQ:
  6660. begin
  6661. { MOVZX doesn't have a 64-bit variant, because
  6662. the 32-bit version implicitly zeroes the
  6663. upper 32-bits of the destination register }
  6664. hp2:=Taicpu.op_reg_reg(A_MOVZX,S_BL,increg,
  6665. newreg(R_INTREGISTER,reg,R_SUBD));
  6666. tmpreg := newreg(R_INTREGISTER,reg,R_SUBQ);
  6667. end;
  6668. {$endif x86_64}
  6669. else
  6670. Internalerror(2020030601);
  6671. end;
  6672. taicpu(hp2).fileinfo:=taicpu(hp1).fileinfo;
  6673. asml.InsertAfter(hp2,p);
  6674. end
  6675. else
  6676. tmpreg := increg;
  6677. if (Taicpu(hp1).opcode=A_INC) or (Taicpu(hp1).opcode=A_DEC) then
  6678. begin
  6679. Taicpu(hp1).ops:=2;
  6680. Taicpu(hp1).loadoper(1,Taicpu(hp1).oper[0]^)
  6681. end;
  6682. Taicpu(hp1).loadreg(0,tmpreg);
  6683. AllocRegBetween(tmpreg,p,hp1,UsedRegs);
  6684. Result := True;
  6685. { p is no longer a Jcc instruction, so exit }
  6686. Exit;
  6687. end;
  6688. end;
  6689. end;
  6690. end;
  6691. { Detect the following:
  6692. jmp<cond> @Lbl1
  6693. jmp @Lbl2
  6694. ...
  6695. @Lbl1:
  6696. ret
  6697. Change to:
  6698. jmp<inv_cond> @Lbl2
  6699. ret
  6700. }
  6701. if MatchInstruction(hp1,A_JMP,[]) and (taicpu(hp1).oper[0]^.ref^.refaddr=addr_full) then
  6702. begin
  6703. hp2:=getlabelwithsym(TAsmLabel(symbol));
  6704. if Assigned(hp2) and SkipLabels(hp2,hp2) and
  6705. MatchInstruction(hp2,A_RET,[S_NO]) then
  6706. begin
  6707. taicpu(p).condition := inverse_cond(taicpu(p).condition);
  6708. { Change label address to that of the unconditional jump }
  6709. taicpu(p).loadoper(0, taicpu(hp1).oper[0]^);
  6710. TAsmLabel(symbol).DecRefs;
  6711. taicpu(hp1).opcode := A_RET;
  6712. taicpu(hp1).is_jmp := false;
  6713. taicpu(hp1).ops := taicpu(hp2).ops;
  6714. DebugMsg(SPeepholeOptimization+'JccJmpRet2J!ccRet',p);
  6715. case taicpu(hp2).ops of
  6716. 0:
  6717. taicpu(hp1).clearop(0);
  6718. 1:
  6719. taicpu(hp1).loadconst(0,taicpu(hp2).oper[0]^.val);
  6720. else
  6721. internalerror(2016041302);
  6722. end;
  6723. end;
  6724. {$ifndef i8086}
  6725. end
  6726. {
  6727. convert
  6728. j<c> .L1
  6729. mov 1,reg
  6730. jmp .L2
  6731. .L1
  6732. mov 0,reg
  6733. .L2
  6734. into
  6735. mov 0,reg
  6736. set<not(c)> reg
  6737. take care of alignment and that the mov 0,reg is not converted into a xor as this
  6738. would destroy the flag contents
  6739. }
  6740. else if MatchInstruction(hp1,A_MOV,[]) and
  6741. MatchOpType(taicpu(hp1),top_const,top_reg) and
  6742. {$ifdef i386}
  6743. (
  6744. { Under i386, ESI, EDI, EBP and ESP
  6745. don't have an 8-bit representation }
  6746. not (getsupreg(taicpu(hp1).oper[1]^.reg) in [RS_ESI, RS_EDI, RS_EBP, RS_ESP])
  6747. ) and
  6748. {$endif i386}
  6749. (taicpu(hp1).oper[0]^.val=1) and
  6750. GetNextInstruction(hp1,hp2) and
  6751. MatchInstruction(hp2,A_JMP,[]) and (taicpu(hp2).oper[0]^.ref^.refaddr=addr_full) and
  6752. GetNextInstruction(hp2,hp3) and
  6753. { skip align }
  6754. ((hp3.typ<>ait_align) or GetNextInstruction(hp3,hp3)) and
  6755. (hp3.typ=ait_label) and
  6756. (tasmlabel(taicpu(p).oper[0]^.ref^.symbol)=tai_label(hp3).labsym) and
  6757. (tai_label(hp3).labsym.getrefs=1) and
  6758. GetNextInstruction(hp3,hp4) and
  6759. MatchInstruction(hp4,A_MOV,[]) and
  6760. MatchOpType(taicpu(hp4),top_const,top_reg) and
  6761. (taicpu(hp4).oper[0]^.val=0) and
  6762. MatchOperand(taicpu(hp1).oper[1]^,taicpu(hp4).oper[1]^) and
  6763. GetNextInstruction(hp4,hp5) and
  6764. (hp5.typ=ait_label) and
  6765. (tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol)=tai_label(hp5).labsym) and
  6766. (tai_label(hp5).labsym.getrefs=1) then
  6767. begin
  6768. AllocRegBetween(NR_FLAGS,p,hp4,UsedRegs);
  6769. DebugMsg(SPeepholeOptimization+'JccMovJmpMov2MovSetcc',p);
  6770. { remove last label }
  6771. RemoveInstruction(hp5);
  6772. { remove second label }
  6773. RemoveInstruction(hp3);
  6774. { if align is present remove it }
  6775. if GetNextInstruction(hp2,hp3) and (hp3.typ=ait_align) then
  6776. RemoveInstruction(hp3);
  6777. { remove jmp }
  6778. RemoveInstruction(hp2);
  6779. if taicpu(hp1).opsize=S_B then
  6780. RemoveInstruction(hp1)
  6781. else
  6782. taicpu(hp1).loadconst(0,0);
  6783. taicpu(hp4).opcode:=A_SETcc;
  6784. taicpu(hp4).opsize:=S_B;
  6785. taicpu(hp4).condition:=inverse_cond(taicpu(p).condition);
  6786. taicpu(hp4).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(hp4).oper[1]^.reg),R_SUBL));
  6787. taicpu(hp4).opercnt:=1;
  6788. taicpu(hp4).ops:=1;
  6789. taicpu(hp4).freeop(1);
  6790. RemoveCurrentP(p);
  6791. Result:=true;
  6792. exit;
  6793. end
  6794. else if CPUX86_HAS_CMOV in cpu_capabilities[current_settings.cputype] then
  6795. begin
  6796. { check for
  6797. jCC xxx
  6798. <several movs>
  6799. xxx:
  6800. }
  6801. l:=0;
  6802. while assigned(hp1) and
  6803. CanBeCMOV(hp1) and
  6804. { stop on labels }
  6805. not(hp1.typ=ait_label) do
  6806. begin
  6807. inc(l);
  6808. GetNextInstruction(hp1,hp1);
  6809. end;
  6810. if assigned(hp1) then
  6811. begin
  6812. if FindLabel(tasmlabel(symbol),hp1) then
  6813. begin
  6814. if (l<=4) and (l>0) then
  6815. begin
  6816. condition:=inverse_cond(taicpu(p).condition);
  6817. GetNextInstruction(p,hp1);
  6818. repeat
  6819. if not Assigned(hp1) then
  6820. InternalError(2018062900);
  6821. taicpu(hp1).opcode:=A_CMOVcc;
  6822. taicpu(hp1).condition:=condition;
  6823. UpdateUsedRegs(hp1);
  6824. GetNextInstruction(hp1,hp1);
  6825. until not(CanBeCMOV(hp1));
  6826. { Remember what hp1 is in case there's multiple aligns to get rid of }
  6827. hp2 := hp1;
  6828. repeat
  6829. if not Assigned(hp2) then
  6830. InternalError(2018062910);
  6831. case hp2.typ of
  6832. ait_label:
  6833. { What we expected - break out of the loop (it won't be a dead label at the top of
  6834. a cluster because that was optimised at an earlier stage) }
  6835. Break;
  6836. ait_align:
  6837. { Go to the next entry until a label is found (may be multiple aligns before it) }
  6838. begin
  6839. hp2 := tai(hp2.Next);
  6840. Continue;
  6841. end;
  6842. else
  6843. begin
  6844. { Might be a comment or temporary allocation entry }
  6845. if not (hp2.typ in SkipInstr) then
  6846. InternalError(2018062911);
  6847. hp2 := tai(hp2.Next);
  6848. Continue;
  6849. end;
  6850. end;
  6851. until False;
  6852. { Now we can safely decrement the reference count }
  6853. tasmlabel(symbol).decrefs;
  6854. DebugMsg(SPeepholeOptimization+'JccMov2CMov',p);
  6855. { Remove the original jump }
  6856. RemoveInstruction(p); { Note, the choice to not use RemoveCurrentp is deliberate }
  6857. GetNextInstruction(hp2, p); { Instruction after the label }
  6858. { Remove the label if this is its final reference }
  6859. if (tasmlabel(symbol).getrefs=0) then
  6860. StripLabelFast(hp1);
  6861. if Assigned(p) then
  6862. begin
  6863. UpdateUsedRegs(p);
  6864. result:=true;
  6865. end;
  6866. exit;
  6867. end;
  6868. end
  6869. else
  6870. begin
  6871. { check further for
  6872. jCC xxx
  6873. <several movs 1>
  6874. jmp yyy
  6875. xxx:
  6876. <several movs 2>
  6877. yyy:
  6878. }
  6879. { hp2 points to jmp yyy }
  6880. hp2:=hp1;
  6881. { skip hp1 to xxx (or an align right before it) }
  6882. GetNextInstruction(hp1, hp1);
  6883. if assigned(hp2) and
  6884. assigned(hp1) and
  6885. (l<=3) and
  6886. (hp2.typ=ait_instruction) and
  6887. (taicpu(hp2).is_jmp) and
  6888. (taicpu(hp2).condition=C_None) and
  6889. { real label and jump, no further references to the
  6890. label are allowed }
  6891. (tasmlabel(symbol).getrefs=1) and
  6892. FindLabel(tasmlabel(symbol),hp1) then
  6893. begin
  6894. l:=0;
  6895. { skip hp1 to <several moves 2> }
  6896. if (hp1.typ = ait_align) then
  6897. GetNextInstruction(hp1, hp1);
  6898. GetNextInstruction(hp1, hpmov2);
  6899. hp1 := hpmov2;
  6900. while assigned(hp1) and
  6901. CanBeCMOV(hp1) do
  6902. begin
  6903. inc(l);
  6904. GetNextInstruction(hp1, hp1);
  6905. end;
  6906. { hp1 points to yyy (or an align right before it) }
  6907. hp3 := hp1;
  6908. if assigned(hp1) and
  6909. FindLabel(tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol),hp1) then
  6910. begin
  6911. condition:=inverse_cond(taicpu(p).condition);
  6912. GetNextInstruction(p,hp1);
  6913. repeat
  6914. taicpu(hp1).opcode:=A_CMOVcc;
  6915. taicpu(hp1).condition:=condition;
  6916. UpdateUsedRegs(hp1);
  6917. GetNextInstruction(hp1,hp1);
  6918. until not(assigned(hp1)) or
  6919. not(CanBeCMOV(hp1));
  6920. condition:=inverse_cond(condition);
  6921. hp1 := hpmov2;
  6922. { hp1 is now at <several movs 2> }
  6923. while Assigned(hp1) and CanBeCMOV(hp1) do
  6924. begin
  6925. taicpu(hp1).opcode:=A_CMOVcc;
  6926. taicpu(hp1).condition:=condition;
  6927. UpdateUsedRegs(hp1);
  6928. GetNextInstruction(hp1,hp1);
  6929. end;
  6930. hp1 := p;
  6931. { Get first instruction after label }
  6932. GetNextInstruction(hp3, p);
  6933. if assigned(p) and (hp3.typ = ait_align) then
  6934. GetNextInstruction(p, p);
  6935. { Don't dereference yet, as doing so will cause
  6936. GetNextInstruction to skip the label and
  6937. optional align marker. [Kit] }
  6938. GetNextInstruction(hp2, hp4);
  6939. DebugMsg(SPeepholeOptimization+'JccMovJmpMov2CMovCMov',hp1);
  6940. { remove jCC }
  6941. RemoveInstruction(hp1);
  6942. { Now we can safely decrement it }
  6943. tasmlabel(symbol).decrefs;
  6944. { Remove label xxx (it will have a ref of zero due to the initial check }
  6945. StripLabelFast(hp4);
  6946. { remove jmp }
  6947. symbol := taicpu(hp2).oper[0]^.ref^.symbol;
  6948. RemoveInstruction(hp2);
  6949. { As before, now we can safely decrement it }
  6950. tasmlabel(symbol).decrefs;
  6951. { Remove label yyy (and the optional alignment) if its reference falls to zero }
  6952. if tasmlabel(symbol).getrefs = 0 then
  6953. StripLabelFast(hp3);
  6954. if Assigned(p) then
  6955. begin
  6956. UpdateUsedRegs(p);
  6957. result:=true;
  6958. end;
  6959. exit;
  6960. end;
  6961. end;
  6962. end;
  6963. end;
  6964. {$endif i8086}
  6965. end;
  6966. end;
  6967. end;
  6968. function TX86AsmOptimizer.OptPass1Movx(var p : tai) : boolean;
  6969. var
  6970. hp1,hp2: tai;
  6971. reg_and_hp1_is_instr: Boolean;
  6972. begin
  6973. result:=false;
  6974. reg_and_hp1_is_instr:=(taicpu(p).oper[1]^.typ = top_reg) and
  6975. GetNextInstruction(p,hp1) and
  6976. (hp1.typ = ait_instruction);
  6977. if reg_and_hp1_is_instr and
  6978. (
  6979. (taicpu(hp1).opcode <> A_LEA) or
  6980. { If the LEA instruction can be converted into an arithmetic instruction,
  6981. it may be possible to then fold it. }
  6982. (
  6983. { If the flags register is in use, don't change the instruction
  6984. to an ADD otherwise this will scramble the flags. [Kit] }
  6985. not RegInUsedRegs(NR_DEFAULTFLAGS, UsedRegs) and
  6986. ConvertLEA(taicpu(hp1))
  6987. )
  6988. ) and
  6989. IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
  6990. GetNextInstruction(hp1,hp2) and
  6991. MatchInstruction(hp2,A_MOV,[]) and
  6992. (taicpu(hp2).oper[0]^.typ = top_reg) and
  6993. OpsEqual(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) and
  6994. ((taicpu(p).opsize in [S_BW,S_BL]) and (taicpu(hp2).opsize=S_B) or
  6995. (taicpu(p).opsize in [S_WL]) and (taicpu(hp2).opsize=S_W)) and
  6996. {$ifdef i386}
  6997. { not all registers have byte size sub registers on i386 }
  6998. ((taicpu(hp2).opsize<>S_B) or (getsupreg(taicpu(hp1).oper[0]^.reg) in [RS_EAX, RS_EBX, RS_ECX, RS_EDX])) and
  6999. {$endif i386}
  7000. (((taicpu(hp1).ops=2) and
  7001. (getsupreg(taicpu(hp2).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg))) or
  7002. ((taicpu(hp1).ops=1) and
  7003. (getsupreg(taicpu(hp2).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[0]^.reg)))) and
  7004. not(RegUsedAfterInstruction(taicpu(hp2).oper[0]^.reg,hp2,UsedRegs)) then
  7005. begin
  7006. { change movsX/movzX reg/ref, reg2
  7007. add/sub/or/... reg3/$const, reg2
  7008. mov reg2 reg/ref
  7009. to add/sub/or/... reg3/$const, reg/ref }
  7010. { by example:
  7011. movswl %si,%eax movswl %si,%eax p
  7012. decl %eax addl %edx,%eax hp1
  7013. movw %ax,%si movw %ax,%si hp2
  7014. ->
  7015. movswl %si,%eax movswl %si,%eax p
  7016. decw %eax addw %edx,%eax hp1
  7017. movw %ax,%si movw %ax,%si hp2
  7018. }
  7019. taicpu(hp1).changeopsize(taicpu(hp2).opsize);
  7020. {
  7021. ->
  7022. movswl %si,%eax movswl %si,%eax p
  7023. decw %si addw %dx,%si hp1
  7024. movw %ax,%si movw %ax,%si hp2
  7025. }
  7026. case taicpu(hp1).ops of
  7027. 1:
  7028. taicpu(hp1).loadoper(0,taicpu(hp2).oper[1]^);
  7029. 2:
  7030. begin
  7031. taicpu(hp1).loadoper(1,taicpu(hp2).oper[1]^);
  7032. if (taicpu(hp1).oper[0]^.typ = top_reg) then
  7033. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  7034. end;
  7035. else
  7036. internalerror(2008042702);
  7037. end;
  7038. {
  7039. ->
  7040. decw %si addw %dx,%si p
  7041. }
  7042. DebugMsg(SPeepholeOptimization + 'var3',p);
  7043. RemoveCurrentP(p, hp1);
  7044. RemoveInstruction(hp2);
  7045. end
  7046. else if reg_and_hp1_is_instr and
  7047. (taicpu(hp1).opcode = A_MOV) and
  7048. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  7049. (MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^)
  7050. {$ifdef x86_64}
  7051. { check for implicit extension to 64 bit }
  7052. or
  7053. ((taicpu(p).opsize in [S_BL,S_WL]) and
  7054. (taicpu(hp1).opsize=S_Q) and
  7055. SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[0]^.reg)
  7056. )
  7057. {$endif x86_64}
  7058. )
  7059. then
  7060. begin
  7061. { change
  7062. movx %reg1,%reg2
  7063. mov %reg2,%reg3
  7064. dealloc %reg2
  7065. into
  7066. movx %reg,%reg3
  7067. }
  7068. TransferUsedRegs(TmpUsedRegs);
  7069. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  7070. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  7071. begin
  7072. DebugMsg(SPeepholeOptimization + 'MovxMov2Movx',p);
  7073. {$ifdef x86_64}
  7074. if (taicpu(p).opsize in [S_BL,S_WL]) and
  7075. (taicpu(hp1).opsize=S_Q) then
  7076. taicpu(p).loadreg(1,newreg(R_INTREGISTER,getsupreg(taicpu(hp1).oper[1]^.reg),R_SUBD))
  7077. else
  7078. {$endif x86_64}
  7079. taicpu(p).loadreg(1,taicpu(hp1).oper[1]^.reg);
  7080. RemoveInstruction(hp1);
  7081. end;
  7082. end
  7083. else if reg_and_hp1_is_instr and
  7084. (taicpu(hp1).opcode = A_MOV) and
  7085. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  7086. (((taicpu(p).opsize in [S_BW,S_BL,S_WL{$ifdef x86_64},S_BQ,S_WQ,S_LQ{$endif x86_64}]) and
  7087. (taicpu(hp1).opsize=S_B)) or
  7088. ((taicpu(p).opsize in [S_WL{$ifdef x86_64},S_WQ,S_LQ{$endif x86_64}]) and
  7089. (taicpu(hp1).opsize=S_W))
  7090. {$ifdef x86_64}
  7091. or ((taicpu(p).opsize=S_LQ) and
  7092. (taicpu(hp1).opsize=S_L))
  7093. {$endif x86_64}
  7094. ) and
  7095. SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[0]^.reg) then
  7096. begin
  7097. { change
  7098. movx %reg1,%reg2
  7099. mov %reg2,%reg3
  7100. dealloc %reg2
  7101. into
  7102. mov %reg1,%reg3
  7103. if the second mov accesses only the bits stored in reg1
  7104. }
  7105. TransferUsedRegs(TmpUsedRegs);
  7106. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  7107. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  7108. begin
  7109. DebugMsg(SPeepholeOptimization + 'MovxMov2Mov',p);
  7110. if taicpu(p).oper[0]^.typ=top_reg then
  7111. begin
  7112. case taicpu(hp1).opsize of
  7113. S_B:
  7114. taicpu(hp1).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[0]^.reg),R_SUBL));
  7115. S_W:
  7116. taicpu(hp1).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[0]^.reg),R_SUBW));
  7117. S_L:
  7118. taicpu(hp1).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[0]^.reg),R_SUBD));
  7119. else
  7120. Internalerror(2020102301);
  7121. end;
  7122. AllocRegBetween(taicpu(hp1).oper[0]^.reg,p,hp1,UsedRegs);
  7123. end
  7124. else
  7125. taicpu(hp1).loadref(0,taicpu(p).oper[0]^.ref^);
  7126. RemoveCurrentP(p);
  7127. result:=true;
  7128. exit;
  7129. end;
  7130. end
  7131. else if reg_and_hp1_is_instr and
  7132. (taicpu(p).oper[0]^.typ = top_reg) and
  7133. (
  7134. (taicpu(hp1).opcode = A_SHL) or (taicpu(hp1).opcode = A_SAL)
  7135. ) and
  7136. (taicpu(hp1).oper[0]^.typ = top_const) and
  7137. SuperRegistersEqual(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^.reg) and
  7138. MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^.reg) and
  7139. { Minimum shift value allowed is the bit difference between the sizes }
  7140. (taicpu(hp1).oper[0]^.val >=
  7141. { Multiply by 8 because tcgsize2size returns bytes, not bits }
  7142. 8 * (
  7143. tcgsize2size[reg_cgsize(taicpu(p).oper[1]^.reg)] -
  7144. tcgsize2size[reg_cgsize(taicpu(p).oper[0]^.reg)]
  7145. )
  7146. ) then
  7147. begin
  7148. { For:
  7149. movsx/movzx %reg1,%reg1 (same register, just different sizes)
  7150. shl/sal ##, %reg1
  7151. Remove the movsx/movzx instruction if the shift overwrites the
  7152. extended bits of the register (e.g. movslq %eax,%rax; shlq $32,%rax
  7153. }
  7154. DebugMsg(SPeepholeOptimization + 'MovxShl2Shl',p);
  7155. RemoveCurrentP(p, hp1);
  7156. Result := True;
  7157. Exit;
  7158. end
  7159. else if reg_and_hp1_is_instr and
  7160. (taicpu(p).oper[0]^.typ = top_reg) and
  7161. (
  7162. ((taicpu(hp1).opcode = A_SHR) and (taicpu(p).opcode = A_MOVZX)) or
  7163. ((taicpu(hp1).opcode = A_SAR) and (taicpu(p).opcode <> A_MOVZX))
  7164. ) and
  7165. (taicpu(hp1).oper[0]^.typ = top_const) and
  7166. SuperRegistersEqual(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^.reg) and
  7167. MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^.reg) and
  7168. { Minimum shift value allowed is the bit size of the smallest register - 1 }
  7169. (taicpu(hp1).oper[0]^.val <
  7170. { Multiply by 8 because tcgsize2size returns bytes, not bits }
  7171. 8 * (
  7172. tcgsize2size[reg_cgsize(taicpu(p).oper[0]^.reg)]
  7173. )
  7174. ) then
  7175. begin
  7176. { For:
  7177. movsx %reg1,%reg1 movzx %reg1,%reg1 (same register, just different sizes)
  7178. sar ##, %reg1 shr ##, %reg1
  7179. Move the shift to before the movx instruction if the shift value
  7180. is not too large.
  7181. }
  7182. asml.Remove(hp1);
  7183. asml.InsertBefore(hp1, p);
  7184. taicpu(hp1).oper[1]^.reg := taicpu(p).oper[0]^.reg;
  7185. case taicpu(p).opsize of
  7186. s_BW, S_BL{$ifdef x86_64}, S_BQ{$endif}:
  7187. taicpu(hp1).opsize := S_B;
  7188. S_WL{$ifdef x86_64}, S_WQ{$endif}:
  7189. taicpu(hp1).opsize := S_W;
  7190. {$ifdef x86_64}
  7191. S_LQ:
  7192. taicpu(hp1).opsize := S_L;
  7193. {$endif}
  7194. else
  7195. InternalError(2020112401);
  7196. end;
  7197. if (taicpu(hp1).opcode = A_SHR) then
  7198. DebugMsg(SPeepholeOptimization + 'MovzShr2ShrMovz', hp1)
  7199. else
  7200. DebugMsg(SPeepholeOptimization + 'MovsSar2SarMovs', hp1);
  7201. Result := True;
  7202. end
  7203. else if taicpu(p).opcode=A_MOVZX then
  7204. begin
  7205. { removes superfluous And's after movzx's }
  7206. if reg_and_hp1_is_instr and
  7207. (taicpu(hp1).opcode = A_AND) and
  7208. MatchOpType(taicpu(hp1),top_const,top_reg) and
  7209. ((taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg)
  7210. {$ifdef x86_64}
  7211. { check for implicit extension to 64 bit }
  7212. or
  7213. ((taicpu(p).opsize in [S_BL,S_WL]) and
  7214. (taicpu(hp1).opsize=S_Q) and
  7215. SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[1]^.reg)
  7216. )
  7217. {$endif x86_64}
  7218. )
  7219. then
  7220. begin
  7221. case taicpu(p).opsize Of
  7222. S_BL, S_BW{$ifdef x86_64}, S_BQ{$endif x86_64}:
  7223. if (taicpu(hp1).oper[0]^.val = $ff) then
  7224. begin
  7225. DebugMsg(SPeepholeOptimization + 'MovzAnd2Movz1',p);
  7226. RemoveInstruction(hp1);
  7227. Result:=true;
  7228. exit;
  7229. end;
  7230. S_WL{$ifdef x86_64}, S_WQ{$endif x86_64}:
  7231. if (taicpu(hp1).oper[0]^.val = $ffff) then
  7232. begin
  7233. DebugMsg(SPeepholeOptimization + 'MovzAnd2Movz2',p);
  7234. RemoveInstruction(hp1);
  7235. Result:=true;
  7236. exit;
  7237. end;
  7238. {$ifdef x86_64}
  7239. S_LQ:
  7240. if (taicpu(hp1).oper[0]^.val = $ffffffff) then
  7241. begin
  7242. DebugMsg(SPeepholeOptimization + 'MovzAnd2Movz3',p);
  7243. RemoveInstruction(hp1);
  7244. Result:=true;
  7245. exit;
  7246. end;
  7247. {$endif x86_64}
  7248. else
  7249. ;
  7250. end;
  7251. { we cannot get rid of the and, but can we get rid of the movz ?}
  7252. if SuperRegistersEqual(taicpu(p).oper[0]^.reg,taicpu(p).oper[1]^.reg) then
  7253. begin
  7254. case taicpu(p).opsize Of
  7255. S_BL, S_BW{$ifdef x86_64}, S_BQ{$endif x86_64}:
  7256. if (taicpu(hp1).oper[0]^.val and $ff)=taicpu(hp1).oper[0]^.val then
  7257. begin
  7258. DebugMsg(SPeepholeOptimization + 'MovzAnd2And1',p);
  7259. RemoveCurrentP(p,hp1);
  7260. Result:=true;
  7261. exit;
  7262. end;
  7263. S_WL{$ifdef x86_64}, S_WQ{$endif x86_64}:
  7264. if (taicpu(hp1).oper[0]^.val and $ffff)=taicpu(hp1).oper[0]^.val then
  7265. begin
  7266. DebugMsg(SPeepholeOptimization + 'MovzAnd2And2',p);
  7267. RemoveCurrentP(p,hp1);
  7268. Result:=true;
  7269. exit;
  7270. end;
  7271. {$ifdef x86_64}
  7272. S_LQ:
  7273. if (taicpu(hp1).oper[0]^.val and $ffffffff)=taicpu(hp1).oper[0]^.val then
  7274. begin
  7275. DebugMsg(SPeepholeOptimization + 'MovzAnd2And3',p);
  7276. RemoveCurrentP(p,hp1);
  7277. Result:=true;
  7278. exit;
  7279. end;
  7280. {$endif x86_64}
  7281. else
  7282. ;
  7283. end;
  7284. end;
  7285. end;
  7286. { changes some movzx constructs to faster synonyms (all examples
  7287. are given with eax/ax, but are also valid for other registers)}
  7288. if MatchOpType(taicpu(p),top_reg,top_reg) then
  7289. begin
  7290. case taicpu(p).opsize of
  7291. { Technically, movzbw %al,%ax cannot be encoded in 32/64-bit mode
  7292. (the machine code is equivalent to movzbl %al,%eax), but the
  7293. code generator still generates that assembler instruction and
  7294. it is silently converted. This should probably be checked.
  7295. [Kit] }
  7296. S_BW:
  7297. begin
  7298. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  7299. (
  7300. not IsMOVZXAcceptable
  7301. { and $0xff,%ax has a smaller encoding but risks a partial write penalty }
  7302. or (
  7303. (cs_opt_size in current_settings.optimizerswitches) and
  7304. (taicpu(p).oper[1]^.reg = NR_AX)
  7305. )
  7306. ) then
  7307. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  7308. begin
  7309. DebugMsg(SPeepholeOptimization + 'var7',p);
  7310. taicpu(p).opcode := A_AND;
  7311. taicpu(p).changeopsize(S_W);
  7312. taicpu(p).loadConst(0,$ff);
  7313. Result := True;
  7314. end
  7315. else if not IsMOVZXAcceptable and
  7316. GetNextInstruction(p, hp1) and
  7317. (tai(hp1).typ = ait_instruction) and
  7318. (taicpu(hp1).opcode = A_AND) and
  7319. MatchOpType(taicpu(hp1),top_const,top_reg) and
  7320. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  7321. { Change "movzbw %reg1, %reg2; andw $const, %reg2"
  7322. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  7323. begin
  7324. DebugMsg(SPeepholeOptimization + 'var8',p);
  7325. taicpu(p).opcode := A_MOV;
  7326. taicpu(p).changeopsize(S_W);
  7327. setsubreg(taicpu(p).oper[0]^.reg,R_SUBW);
  7328. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  7329. Result := True;
  7330. end;
  7331. end;
  7332. {$ifndef i8086} { movzbl %al,%eax cannot be encoded in 16-bit mode (the machine code is equivalent to movzbw %al,%ax }
  7333. S_BL:
  7334. begin
  7335. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  7336. (
  7337. not IsMOVZXAcceptable
  7338. { and $0xff,%eax has a smaller encoding but risks a partial write penalty }
  7339. or (
  7340. (cs_opt_size in current_settings.optimizerswitches) and
  7341. (taicpu(p).oper[1]^.reg = NR_EAX)
  7342. )
  7343. ) then
  7344. { Change "movzbl %al, %eax" to "andl $0x0ffh, %eax" }
  7345. begin
  7346. DebugMsg(SPeepholeOptimization + 'var9',p);
  7347. taicpu(p).opcode := A_AND;
  7348. taicpu(p).changeopsize(S_L);
  7349. taicpu(p).loadConst(0,$ff);
  7350. Result := True;
  7351. end
  7352. else if not IsMOVZXAcceptable and
  7353. GetNextInstruction(p, hp1) and
  7354. (tai(hp1).typ = ait_instruction) and
  7355. (taicpu(hp1).opcode = A_AND) and
  7356. MatchOpType(taicpu(hp1),top_const,top_reg) and
  7357. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  7358. { Change "movzbl %reg1, %reg2; andl $const, %reg2"
  7359. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  7360. begin
  7361. DebugMsg(SPeepholeOptimization + 'var10',p);
  7362. taicpu(p).opcode := A_MOV;
  7363. taicpu(p).changeopsize(S_L);
  7364. { do not use R_SUBWHOLE
  7365. as movl %rdx,%eax
  7366. is invalid in assembler PM }
  7367. setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
  7368. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  7369. Result := True;
  7370. end;
  7371. end;
  7372. {$endif i8086}
  7373. S_WL:
  7374. if not IsMOVZXAcceptable then
  7375. begin
  7376. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) then
  7377. { Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax" }
  7378. begin
  7379. DebugMsg(SPeepholeOptimization + 'var11',p);
  7380. taicpu(p).opcode := A_AND;
  7381. taicpu(p).changeopsize(S_L);
  7382. taicpu(p).loadConst(0,$ffff);
  7383. Result := True;
  7384. end
  7385. else if GetNextInstruction(p, hp1) and
  7386. (tai(hp1).typ = ait_instruction) and
  7387. (taicpu(hp1).opcode = A_AND) and
  7388. (taicpu(hp1).oper[0]^.typ = top_const) and
  7389. (taicpu(hp1).oper[1]^.typ = top_reg) and
  7390. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  7391. { Change "movzwl %reg1, %reg2; andl $const, %reg2"
  7392. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  7393. begin
  7394. DebugMsg(SPeepholeOptimization + 'var12',p);
  7395. taicpu(p).opcode := A_MOV;
  7396. taicpu(p).changeopsize(S_L);
  7397. { do not use R_SUBWHOLE
  7398. as movl %rdx,%eax
  7399. is invalid in assembler PM }
  7400. setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
  7401. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  7402. Result := True;
  7403. end;
  7404. end;
  7405. else
  7406. InternalError(2017050705);
  7407. end;
  7408. end
  7409. else if not IsMOVZXAcceptable and (taicpu(p).oper[0]^.typ = top_ref) then
  7410. begin
  7411. if GetNextInstruction(p, hp1) and
  7412. (tai(hp1).typ = ait_instruction) and
  7413. (taicpu(hp1).opcode = A_AND) and
  7414. MatchOpType(taicpu(hp1),top_const,top_reg) and
  7415. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  7416. begin
  7417. //taicpu(p).opcode := A_MOV;
  7418. case taicpu(p).opsize Of
  7419. S_BL:
  7420. begin
  7421. DebugMsg(SPeepholeOptimization + 'var13',p);
  7422. taicpu(hp1).changeopsize(S_L);
  7423. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  7424. end;
  7425. S_WL:
  7426. begin
  7427. DebugMsg(SPeepholeOptimization + 'var14',p);
  7428. taicpu(hp1).changeopsize(S_L);
  7429. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  7430. end;
  7431. S_BW:
  7432. begin
  7433. DebugMsg(SPeepholeOptimization + 'var15',p);
  7434. taicpu(hp1).changeopsize(S_W);
  7435. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  7436. end;
  7437. else
  7438. Internalerror(2017050704)
  7439. end;
  7440. Result := True;
  7441. end;
  7442. end;
  7443. end;
  7444. end;
  7445. function TX86AsmOptimizer.OptPass1AND(var p : tai) : boolean;
  7446. var
  7447. hp1, hp2 : tai;
  7448. MaskLength : Cardinal;
  7449. MaskedBits : TCgInt;
  7450. begin
  7451. Result:=false;
  7452. { There are no optimisations for reference targets }
  7453. if (taicpu(p).oper[1]^.typ <> top_reg) then
  7454. Exit;
  7455. while GetNextInstruction(p, hp1) and
  7456. (hp1.typ = ait_instruction) do
  7457. begin
  7458. if (taicpu(p).oper[0]^.typ = top_const) then
  7459. begin
  7460. if (taicpu(hp1).opcode = A_AND) and
  7461. MatchOpType(taicpu(hp1),top_const,top_reg) and
  7462. (getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
  7463. { the second register must contain the first one, so compare their subreg types }
  7464. (getsubreg(taicpu(p).oper[1]^.reg)<=getsubreg(taicpu(hp1).oper[1]^.reg)) and
  7465. (abs(taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val)<$80000000) then
  7466. { change
  7467. and const1, reg
  7468. and const2, reg
  7469. to
  7470. and (const1 and const2), reg
  7471. }
  7472. begin
  7473. taicpu(hp1).loadConst(0, taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
  7474. DebugMsg(SPeepholeOptimization + 'AndAnd2And done',hp1);
  7475. RemoveCurrentP(p, hp1);
  7476. Result:=true;
  7477. exit;
  7478. end
  7479. else if (taicpu(hp1).opcode = A_MOVZX) and
  7480. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  7481. SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[1]^.reg) and
  7482. (getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
  7483. (((taicpu(p).opsize=S_W) and
  7484. (taicpu(hp1).opsize=S_BW)) or
  7485. ((taicpu(p).opsize=S_L) and
  7486. (taicpu(hp1).opsize in [S_WL,S_BL{$ifdef x86_64},S_BQ,S_WQ{$endif x86_64}]))
  7487. {$ifdef x86_64}
  7488. or
  7489. ((taicpu(p).opsize=S_Q) and
  7490. (taicpu(hp1).opsize in [S_BQ,S_WQ,S_BL,S_WL]))
  7491. {$endif x86_64}
  7492. ) then
  7493. begin
  7494. if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
  7495. ((taicpu(p).oper[0]^.val and $ff)=taicpu(p).oper[0]^.val)
  7496. ) or
  7497. (((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
  7498. ((taicpu(p).oper[0]^.val and $ffff)=taicpu(p).oper[0]^.val))
  7499. then
  7500. begin
  7501. { Unlike MOVSX, MOVZX doesn't actually have a version that zero-extends a
  7502. 32-bit register to a 64-bit register, or even a version called MOVZXD, so
  7503. code that tests for the presence of AND 0xffffffff followed by MOVZX is
  7504. wasted, and is indictive of a compiler bug if it were triggered. [Kit]
  7505. NOTE: To zero-extend from 32 bits to 64 bits, simply use the standard MOV.
  7506. }
  7507. DebugMsg(SPeepholeOptimization + 'AndMovzToAnd done',p);
  7508. RemoveInstruction(hp1);
  7509. { See if there are other optimisations possible }
  7510. Continue;
  7511. end;
  7512. end
  7513. else if (taicpu(hp1).opcode = A_SHL) and
  7514. MatchOpType(taicpu(hp1),top_const,top_reg) and
  7515. (getsupreg(taicpu(p).oper[1]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) then
  7516. begin
  7517. {$ifopt R+}
  7518. {$define RANGE_WAS_ON}
  7519. {$R-}
  7520. {$endif}
  7521. { get length of potential and mask }
  7522. MaskLength:=SizeOf(taicpu(p).oper[0]^.val)*8-BsrQWord(taicpu(p).oper[0]^.val)-1;
  7523. { really a mask? }
  7524. {$ifdef RANGE_WAS_ON}
  7525. {$R+}
  7526. {$endif}
  7527. if (((QWord(1) shl MaskLength)-1)=taicpu(p).oper[0]^.val) and
  7528. { unmasked part shifted out? }
  7529. ((MaskLength+taicpu(hp1).oper[0]^.val)>=topsize2memsize[taicpu(hp1).opsize]) then
  7530. begin
  7531. DebugMsg(SPeepholeOptimization + 'AndShlToShl done',p);
  7532. RemoveCurrentP(p, hp1);
  7533. Result:=true;
  7534. exit;
  7535. end;
  7536. end
  7537. else if (taicpu(hp1).opcode = A_SHR) and
  7538. MatchOpType(taicpu(hp1),top_const,top_reg) and
  7539. (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg) and
  7540. (taicpu(hp1).oper[0]^.val <= 63) then
  7541. begin
  7542. { Does SHR combined with the AND cover all the bits?
  7543. e.g. for "andb $252,%reg; shrb $2,%reg" - the "and" can be removed }
  7544. MaskedBits := taicpu(p).oper[0]^.val or ((TCgInt(1) shl taicpu(hp1).oper[0]^.val) - 1);
  7545. if ((taicpu(p).opsize = S_B) and ((MaskedBits and $FF) = $FF)) or
  7546. ((taicpu(p).opsize = S_W) and ((MaskedBits and $FFFF) = $FFFF)) or
  7547. ((taicpu(p).opsize = S_L) and ((MaskedBits and $FFFFFFFF) = $FFFFFFFF)) then
  7548. begin
  7549. DebugMsg(SPeepholeOptimization + 'AndShrToShr done', p);
  7550. RemoveCurrentP(p, hp1);
  7551. Result := True;
  7552. Exit;
  7553. end;
  7554. end
  7555. else if ((taicpu(hp1).opcode = A_MOVSX){$ifdef x86_64} or (taicpu(hp1).opcode = A_MOVSXD){$endif x86_64}) and
  7556. (taicpu(hp1).oper[0]^.typ = top_reg) and
  7557. SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then
  7558. begin
  7559. if SuperRegistersEqual(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[1]^.reg) and
  7560. (
  7561. (
  7562. (taicpu(hp1).opsize in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
  7563. ((taicpu(p).oper[0]^.val and $7F) = taicpu(p).oper[0]^.val)
  7564. ) or (
  7565. (taicpu(hp1).opsize in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
  7566. ((taicpu(p).oper[0]^.val and $7FFF) = taicpu(p).oper[0]^.val)
  7567. {$ifdef x86_64}
  7568. ) or (
  7569. (taicpu(hp1).opsize = S_LQ) and
  7570. ((taicpu(p).oper[0]^.val and $7fffffff) = taicpu(p).oper[0]^.val)
  7571. {$endif x86_64}
  7572. )
  7573. ) then
  7574. begin
  7575. if (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg){$ifdef x86_64} or (taicpu(hp1).opsize = S_LQ){$endif x86_64} then
  7576. begin
  7577. DebugMsg(SPeepholeOptimization + 'AndMovsxToAnd',p);
  7578. RemoveInstruction(hp1);
  7579. { See if there are other optimisations possible }
  7580. Continue;
  7581. end;
  7582. { The super-registers are the same though.
  7583. Note that this change by itself doesn't improve
  7584. code speed, but it opens up other optimisations. }
  7585. {$ifdef x86_64}
  7586. { Convert 64-bit register to 32-bit }
  7587. case taicpu(hp1).opsize of
  7588. S_BQ:
  7589. begin
  7590. taicpu(hp1).opsize := S_BL;
  7591. taicpu(hp1).oper[1]^.reg := newreg(R_INTREGISTER, getsupreg(taicpu(hp1).oper[1]^.reg), R_SUBD);
  7592. end;
  7593. S_WQ:
  7594. begin
  7595. taicpu(hp1).opsize := S_WL;
  7596. taicpu(hp1).oper[1]^.reg := newreg(R_INTREGISTER, getsupreg(taicpu(hp1).oper[1]^.reg), R_SUBD);
  7597. end
  7598. else
  7599. ;
  7600. end;
  7601. {$endif x86_64}
  7602. DebugMsg(SPeepholeOptimization + 'AndMovsxToAndMovzx', hp1);
  7603. taicpu(hp1).opcode := A_MOVZX;
  7604. { See if there are other optimisations possible }
  7605. Continue;
  7606. end;
  7607. end;
  7608. end;
  7609. if (taicpu(hp1).is_jmp) and
  7610. (taicpu(hp1).opcode<>A_JMP) and
  7611. not(RegInUsedRegs(taicpu(p).oper[1]^.reg,UsedRegs)) then
  7612. begin
  7613. { change
  7614. and x, reg
  7615. jxx
  7616. to
  7617. test x, reg
  7618. jxx
  7619. if reg is deallocated before the
  7620. jump, but only if it's a conditional jump (PFV)
  7621. }
  7622. taicpu(p).opcode := A_TEST;
  7623. Exit;
  7624. end;
  7625. Break;
  7626. end;
  7627. { Lone AND tests }
  7628. if (taicpu(p).oper[0]^.typ = top_const) then
  7629. begin
  7630. {
  7631. - Convert and $0xFF,reg to and reg,reg if reg is 8-bit
  7632. - Convert and $0xFFFF,reg to and reg,reg if reg is 16-bit
  7633. - Convert and $0xFFFFFFFF,reg to and reg,reg if reg is 32-bit
  7634. }
  7635. if ((taicpu(p).oper[0]^.val = $FF) and (taicpu(p).opsize = S_B)) or
  7636. ((taicpu(p).oper[0]^.val = $FFFF) and (taicpu(p).opsize = S_W)) or
  7637. ((taicpu(p).oper[0]^.val = $FFFFFFFF) and (taicpu(p).opsize = S_L)) then
  7638. begin
  7639. taicpu(p).loadreg(0, taicpu(p).oper[1]^.reg);
  7640. if taicpu(p).opsize = S_L then
  7641. begin
  7642. Include(OptsToCheck,aoc_MovAnd2Mov_3);
  7643. Result := True;
  7644. end;
  7645. end;
  7646. end;
  7647. { Backward check to determine necessity of and %reg,%reg }
  7648. if (taicpu(p).oper[0]^.typ = top_reg) and
  7649. (taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  7650. not RegInUsedRegs(NR_DEFAULTFLAGS, UsedRegs) and
  7651. GetLastInstruction(p, hp2) and
  7652. RegModifiedByInstruction(taicpu(p).oper[1]^.reg, hp2) and
  7653. { Check size of adjacent instruction to determine if the AND is
  7654. effectively a null operation }
  7655. (
  7656. (taicpu(p).opsize = taicpu(hp2).opsize) or
  7657. { Note: Don't include S_Q }
  7658. ((taicpu(p).opsize = S_L) and (taicpu(hp2).opsize in [S_BL, S_WL])) or
  7659. ((taicpu(p).opsize = S_W) and (taicpu(hp2).opsize in [S_BW, S_BL, S_WL, S_L])) or
  7660. ((taicpu(p).opsize = S_B) and (taicpu(hp2).opsize in [S_BW, S_BL, S_WL, S_W, S_L]))
  7661. ) then
  7662. begin
  7663. DebugMsg(SPeepholeOptimization + 'And2Nop', p);
  7664. { If GetNextInstruction returned False, hp1 will be nil }
  7665. RemoveCurrentP(p, hp1);
  7666. Result := True;
  7667. Exit;
  7668. end;
  7669. end;
  7670. function TX86AsmOptimizer.OptPass2ADD(var p : tai) : boolean;
  7671. var
  7672. hp1: tai; NewRef: TReference;
  7673. { This entire nested function is used in an if-statement below, but we
  7674. want to avoid all the used reg transfers and GetNextInstruction calls
  7675. until we really have to check }
  7676. function MemRegisterNotUsedLater: Boolean; inline;
  7677. var
  7678. hp2: tai;
  7679. begin
  7680. TransferUsedRegs(TmpUsedRegs);
  7681. hp2 := p;
  7682. repeat
  7683. UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
  7684. until not GetNextInstruction(hp2, hp2) or (hp2 = hp1);
  7685. Result := not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs);
  7686. end;
  7687. begin
  7688. Result := False;
  7689. if not GetNextInstruction(p, hp1) or (hp1.typ <> ait_instruction) then
  7690. Exit;
  7691. if (taicpu(p).opsize in [S_L{$ifdef x86_64}, S_Q{$endif}]) then
  7692. begin
  7693. { Change:
  7694. add %reg2,%reg1
  7695. mov/s/z #(%reg1),%reg1 (%reg1 superregisters must be the same)
  7696. To:
  7697. mov/s/z #(%reg1,%reg2),%reg1
  7698. }
  7699. if MatchOpType(taicpu(p), top_reg, top_reg) and
  7700. MatchInstruction(hp1, [A_MOV, A_MOVZX, A_MOVSX{$ifdef x86_64}, A_MOVSXD{$endif}], []) and
  7701. MatchOpType(taicpu(hp1), top_ref, top_reg) and
  7702. (taicpu(hp1).oper[0]^.ref^.scalefactor <= 1) and
  7703. (
  7704. (
  7705. (taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) and
  7706. (taicpu(hp1).oper[0]^.ref^.index = NR_NO)
  7707. ) or (
  7708. (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) and
  7709. (taicpu(hp1).oper[0]^.ref^.base = NR_NO)
  7710. )
  7711. ) and (
  7712. Reg1WriteOverwritesReg2Entirely(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[1]^.reg) or
  7713. (
  7714. { If the super registers ARE equal, then this MOV/S/Z does a partial write }
  7715. not SuperRegistersEqual(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[1]^.reg) and
  7716. MemRegisterNotUsedLater
  7717. )
  7718. ) then
  7719. begin
  7720. taicpu(hp1).oper[0]^.ref^.base := taicpu(p).oper[1]^.reg;
  7721. taicpu(hp1).oper[0]^.ref^.index := taicpu(p).oper[0]^.reg;
  7722. DebugMsg(SPeepholeOptimization + 'AddMov2Mov done', p);
  7723. RemoveCurrentp(p, hp1);
  7724. Result := True;
  7725. Exit;
  7726. end;
  7727. { Change:
  7728. addl/q $x,%reg1
  7729. movl/q %reg1,%reg2
  7730. To:
  7731. leal/q $x(%reg1),%reg2
  7732. addl/q $x,%reg1 (can be removed if %reg1 or the flags are not used afterwards)
  7733. Breaks the dependency chain.
  7734. }
  7735. if MatchOpType(taicpu(p),top_const,top_reg) and
  7736. MatchInstruction(hp1, A_MOV, [taicpu(p).opsize]) and
  7737. (taicpu(hp1).oper[1]^.typ = top_reg) and
  7738. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[1]^.reg) and
  7739. (
  7740. { Don't do AddMov2LeaAdd under -Os, but do allow AddMov2Lea }
  7741. not (cs_opt_size in current_settings.optimizerswitches) or
  7742. (
  7743. not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs) and
  7744. RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs)
  7745. )
  7746. ) then
  7747. begin
  7748. { Change the MOV instruction to a LEA instruction, and update the
  7749. first operand }
  7750. reference_reset(NewRef, 1, []);
  7751. NewRef.base := taicpu(p).oper[1]^.reg;
  7752. NewRef.scalefactor := 1;
  7753. NewRef.offset := taicpu(p).oper[0]^.val;
  7754. taicpu(hp1).opcode := A_LEA;
  7755. taicpu(hp1).loadref(0, NewRef);
  7756. TransferUsedRegs(TmpUsedRegs);
  7757. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  7758. if RegUsedAfterInstruction(NewRef.base, hp1, TmpUsedRegs) or
  7759. RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs) then
  7760. begin
  7761. { Move what is now the LEA instruction to before the SUB instruction }
  7762. Asml.Remove(hp1);
  7763. Asml.InsertBefore(hp1, p);
  7764. AllocRegBetween(taicpu(hp1).oper[1]^.reg, hp1, p, UsedRegs);
  7765. DebugMsg(SPeepholeOptimization + 'AddMov2LeaAdd', p);
  7766. p := hp1;
  7767. end
  7768. else
  7769. begin
  7770. { Since %reg1 or the flags aren't used afterwards, we can delete p completely }
  7771. RemoveCurrentP(p, hp1);
  7772. DebugMsg(SPeepholeOptimization + 'AddMov2Lea', p);
  7773. end;
  7774. Result := True;
  7775. end;
  7776. end;
  7777. end;
  7778. function TX86AsmOptimizer.OptPass2Lea(var p : tai) : Boolean;
  7779. begin
  7780. Result:=false;
  7781. if not (RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
  7782. begin
  7783. if MatchReference(taicpu(p).oper[0]^.ref^,taicpu(p).oper[1]^.reg,NR_INVALID) and
  7784. (taicpu(p).oper[0]^.ref^.index<>NR_NO) then
  7785. begin
  7786. taicpu(p).loadreg(1,taicpu(p).oper[0]^.ref^.base);
  7787. taicpu(p).loadreg(0,taicpu(p).oper[0]^.ref^.index);
  7788. taicpu(p).opcode:=A_ADD;
  7789. DebugMsg(SPeepholeOptimization + 'Lea2AddBase done',p);
  7790. result:=true;
  7791. end
  7792. else if MatchReference(taicpu(p).oper[0]^.ref^,NR_INVALID,taicpu(p).oper[1]^.reg) and
  7793. (taicpu(p).oper[0]^.ref^.base<>NR_NO) then
  7794. begin
  7795. taicpu(p).loadreg(1,taicpu(p).oper[0]^.ref^.index);
  7796. taicpu(p).loadreg(0,taicpu(p).oper[0]^.ref^.base);
  7797. taicpu(p).opcode:=A_ADD;
  7798. DebugMsg(SPeepholeOptimization + 'Lea2AddIndex done',p);
  7799. result:=true;
  7800. end;
  7801. end;
  7802. end;
  7803. function TX86AsmOptimizer.OptPass2SUB(var p: tai): Boolean;
  7804. var
  7805. hp1: tai; NewRef: TReference;
  7806. begin
  7807. { Change:
  7808. subl/q $x,%reg1
  7809. movl/q %reg1,%reg2
  7810. To:
  7811. leal/q $-x(%reg1),%reg2
  7812. subl/q $x,%reg1 (can be removed if %reg1 or the flags are not used afterwards)
  7813. Breaks the dependency chain and potentially permits the removal of
  7814. a CMP instruction if one follows.
  7815. }
  7816. Result := False;
  7817. if (taicpu(p).opsize in [S_L{$ifdef x86_64}, S_Q{$endif x86_64}]) and
  7818. MatchOpType(taicpu(p),top_const,top_reg) and
  7819. GetNextInstruction(p, hp1) and
  7820. MatchInstruction(hp1, A_MOV, [taicpu(p).opsize]) and
  7821. (taicpu(hp1).oper[1]^.typ = top_reg) and
  7822. MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[1]^.reg) and
  7823. (
  7824. { Don't do SubMov2LeaSub under -Os, but do allow SubMov2Lea }
  7825. not (cs_opt_size in current_settings.optimizerswitches) or
  7826. (
  7827. not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs) and
  7828. RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs)
  7829. )
  7830. ) then
  7831. begin
  7832. { Change the MOV instruction to a LEA instruction, and update the
  7833. first operand }
  7834. reference_reset(NewRef, 1, []);
  7835. NewRef.base := taicpu(p).oper[1]^.reg;
  7836. NewRef.scalefactor := 1;
  7837. NewRef.offset := -taicpu(p).oper[0]^.val;
  7838. taicpu(hp1).opcode := A_LEA;
  7839. taicpu(hp1).loadref(0, NewRef);
  7840. TransferUsedRegs(TmpUsedRegs);
  7841. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  7842. if RegUsedAfterInstruction(NewRef.base, hp1, TmpUsedRegs) or
  7843. RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs) then
  7844. begin
  7845. { Move what is now the LEA instruction to before the SUB instruction }
  7846. Asml.Remove(hp1);
  7847. Asml.InsertBefore(hp1, p);
  7848. AllocRegBetween(taicpu(hp1).oper[1]^.reg, hp1, p, UsedRegs);
  7849. DebugMsg(SPeepholeOptimization + 'SubMov2LeaSub', p);
  7850. p := hp1;
  7851. end
  7852. else
  7853. begin
  7854. { Since %reg1 or the flags aren't used afterwards, we can delete p completely }
  7855. RemoveCurrentP(p, hp1);
  7856. DebugMsg(SPeepholeOptimization + 'SubMov2Lea', p);
  7857. end;
  7858. Result := True;
  7859. end;
  7860. end;
  7861. function TX86AsmOptimizer.SkipSimpleInstructions(var hp1 : tai) : Boolean;
  7862. begin
  7863. { we can skip all instructions not messing with the stack pointer }
  7864. while assigned(hp1) and {MatchInstruction(hp1,[A_LEA,A_MOV,A_MOVQ,A_MOVSQ,A_MOVSX,A_MOVSXD,A_MOVZX,
  7865. A_AND,A_OR,A_XOR,A_ADD,A_SHR,A_SHL,A_IMUL,A_SETcc,A_SAR,A_SUB,A_TEST,A_CMOVcc,
  7866. A_MOVSS,A_MOVSD,A_MOVAPS,A_MOVUPD,A_MOVAPD,A_MOVUPS,
  7867. A_VMOVSS,A_VMOVSD,A_VMOVAPS,A_VMOVUPD,A_VMOVAPD,A_VMOVUPS],[]) and}
  7868. ({(taicpu(hp1).ops=0) or }
  7869. ({(MatchOpType(taicpu(hp1),top_reg,top_reg) or MatchOpType(taicpu(hp1),top_const,top_reg) or
  7870. (MatchOpType(taicpu(hp1),top_ref,top_reg))
  7871. ) and }
  7872. not(RegInInstruction(NR_STACK_POINTER_REG,hp1)) { and not(RegInInstruction(NR_FRAME_POINTER_REG,hp1))}
  7873. )
  7874. ) do
  7875. GetNextInstruction(hp1,hp1);
  7876. Result:=assigned(hp1);
  7877. end;
  7878. function TX86AsmOptimizer.PostPeepholeOptLea(var p : tai) : Boolean;
  7879. var
  7880. hp1, hp2, hp3, hp4, hp5: tai;
  7881. begin
  7882. Result:=false;
  7883. hp5:=nil;
  7884. { replace
  7885. leal(q) x(<stackpointer>),<stackpointer>
  7886. call procname
  7887. leal(q) -x(<stackpointer>),<stackpointer>
  7888. ret
  7889. by
  7890. jmp procname
  7891. but do it only on level 4 because it destroys stack back traces
  7892. }
  7893. if (cs_opt_level4 in current_settings.optimizerswitches) and
  7894. MatchOpType(taicpu(p),top_ref,top_reg) and
  7895. (taicpu(p).oper[0]^.ref^.base=NR_STACK_POINTER_REG) and
  7896. (taicpu(p).oper[0]^.ref^.index=NR_NO) and
  7897. { the -8 or -24 are not required, but bail out early if possible,
  7898. higher values are unlikely }
  7899. ((taicpu(p).oper[0]^.ref^.offset=-8) or
  7900. (taicpu(p).oper[0]^.ref^.offset=-24)) and
  7901. (taicpu(p).oper[0]^.ref^.symbol=nil) and
  7902. (taicpu(p).oper[0]^.ref^.relsymbol=nil) and
  7903. (taicpu(p).oper[0]^.ref^.segment=NR_NO) and
  7904. (taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG) and
  7905. GetNextInstruction(p, hp1) and
  7906. { Take a copy of hp1 }
  7907. SetAndTest(hp1, hp4) and
  7908. { trick to skip label }
  7909. ((hp1.typ=ait_instruction) or GetNextInstruction(hp1, hp1)) and
  7910. SkipSimpleInstructions(hp1) and
  7911. MatchInstruction(hp1,A_CALL,[S_NO]) and
  7912. GetNextInstruction(hp1, hp2) and
  7913. MatchInstruction(hp2,A_LEA,[taicpu(p).opsize]) and
  7914. MatchOpType(taicpu(hp2),top_ref,top_reg) and
  7915. (taicpu(hp2).oper[0]^.ref^.offset=-taicpu(p).oper[0]^.ref^.offset) and
  7916. (taicpu(hp2).oper[0]^.ref^.base=NR_STACK_POINTER_REG) and
  7917. (taicpu(hp2).oper[0]^.ref^.index=NR_NO) and
  7918. (taicpu(hp2).oper[0]^.ref^.symbol=nil) and
  7919. (taicpu(hp2).oper[0]^.ref^.relsymbol=nil) and
  7920. (taicpu(hp2).oper[0]^.ref^.segment=NR_NO) and
  7921. (taicpu(hp2).oper[1]^.reg=NR_STACK_POINTER_REG) and
  7922. GetNextInstruction(hp2, hp3) and
  7923. { trick to skip label }
  7924. ((hp3.typ=ait_instruction) or GetNextInstruction(hp3, hp3)) and
  7925. (MatchInstruction(hp3,A_RET,[S_NO]) or
  7926. (MatchInstruction(hp3,A_VZEROUPPER,[S_NO]) and
  7927. SetAndTest(hp3,hp5) and
  7928. GetNextInstruction(hp3,hp3) and
  7929. MatchInstruction(hp3,A_RET,[S_NO])
  7930. )
  7931. ) and
  7932. (taicpu(hp3).ops=0) then
  7933. begin
  7934. taicpu(hp1).opcode := A_JMP;
  7935. taicpu(hp1).is_jmp := true;
  7936. DebugMsg(SPeepholeOptimization + 'LeaCallLeaRet2Jmp done',p);
  7937. RemoveCurrentP(p, hp4);
  7938. RemoveInstruction(hp2);
  7939. RemoveInstruction(hp3);
  7940. if Assigned(hp5) then
  7941. begin
  7942. AsmL.Remove(hp5);
  7943. ASmL.InsertBefore(hp5,hp1)
  7944. end;
  7945. Result:=true;
  7946. end;
  7947. end;
  7948. function TX86AsmOptimizer.PostPeepholeOptPush(var p : tai) : Boolean;
  7949. {$ifdef x86_64}
  7950. var
  7951. hp1, hp2, hp3, hp4, hp5: tai;
  7952. {$endif x86_64}
  7953. begin
  7954. Result:=false;
  7955. {$ifdef x86_64}
  7956. hp5:=nil;
  7957. { replace
  7958. push %rax
  7959. call procname
  7960. pop %rcx
  7961. ret
  7962. by
  7963. jmp procname
  7964. but do it only on level 4 because it destroys stack back traces
  7965. It depends on the fact, that the sequence push rax/pop rcx is used for stack alignment as rcx is volatile
  7966. for all supported calling conventions
  7967. }
  7968. if (cs_opt_level4 in current_settings.optimizerswitches) and
  7969. MatchOpType(taicpu(p),top_reg) and
  7970. (taicpu(p).oper[0]^.reg=NR_RAX) and
  7971. GetNextInstruction(p, hp1) and
  7972. { Take a copy of hp1 }
  7973. SetAndTest(hp1, hp4) and
  7974. { trick to skip label }
  7975. ((hp1.typ=ait_instruction) or GetNextInstruction(hp1, hp1)) and
  7976. SkipSimpleInstructions(hp1) and
  7977. MatchInstruction(hp1,A_CALL,[S_NO]) and
  7978. GetNextInstruction(hp1, hp2) and
  7979. MatchInstruction(hp2,A_POP,[taicpu(p).opsize]) and
  7980. MatchOpType(taicpu(hp2),top_reg) and
  7981. (taicpu(hp2).oper[0]^.reg=NR_RCX) and
  7982. GetNextInstruction(hp2, hp3) and
  7983. { trick to skip label }
  7984. ((hp3.typ=ait_instruction) or GetNextInstruction(hp3, hp3)) and
  7985. (MatchInstruction(hp3,A_RET,[S_NO]) or
  7986. (MatchInstruction(hp3,A_VZEROUPPER,[S_NO]) and
  7987. SetAndTest(hp3,hp5) and
  7988. GetNextInstruction(hp3,hp3) and
  7989. MatchInstruction(hp3,A_RET,[S_NO])
  7990. )
  7991. ) and
  7992. (taicpu(hp3).ops=0) then
  7993. begin
  7994. taicpu(hp1).opcode := A_JMP;
  7995. taicpu(hp1).is_jmp := true;
  7996. DebugMsg(SPeepholeOptimization + 'PushCallPushRet2Jmp done',p);
  7997. RemoveCurrentP(p, hp4);
  7998. RemoveInstruction(hp2);
  7999. RemoveInstruction(hp3);
  8000. if Assigned(hp5) then
  8001. begin
  8002. AsmL.Remove(hp5);
  8003. ASmL.InsertBefore(hp5,hp1)
  8004. end;
  8005. Result:=true;
  8006. end;
  8007. {$endif x86_64}
  8008. end;
  8009. function TX86AsmOptimizer.PostPeepholeOptMov(var p : tai) : Boolean;
  8010. var
  8011. Value, RegName: string;
  8012. begin
  8013. Result:=false;
  8014. if (taicpu(p).oper[1]^.typ = top_reg) and (taicpu(p).oper[0]^.typ = top_const) then
  8015. begin
  8016. case taicpu(p).oper[0]^.val of
  8017. 0:
  8018. { Don't make this optimisation if the CPU flags are required, since XOR scrambles them }
  8019. if not (RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
  8020. begin
  8021. { change "mov $0,%reg" into "xor %reg,%reg" }
  8022. taicpu(p).opcode := A_XOR;
  8023. taicpu(p).loadReg(0,taicpu(p).oper[1]^.reg);
  8024. Result := True;
  8025. end;
  8026. $1..$FFFFFFFF:
  8027. begin
  8028. { Code size reduction by J. Gareth "Kit" Moreton }
  8029. { change 64-bit register to 32-bit register to reduce code size (upper 32 bits will be set to zero) }
  8030. case taicpu(p).opsize of
  8031. S_Q:
  8032. begin
  8033. RegName := debug_regname(taicpu(p).oper[1]^.reg); { 64-bit register name }
  8034. Value := debug_tostr(taicpu(p).oper[0]^.val);
  8035. { The actual optimization }
  8036. setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
  8037. taicpu(p).changeopsize(S_L);
  8038. DebugMsg(SPeepholeOptimization + 'movq $' + Value + ',' + RegName + ' -> movl $' + Value + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' (immediate can be represented with just 32 bits)', p);
  8039. Result := True;
  8040. end;
  8041. else
  8042. { Do nothing };
  8043. end;
  8044. end;
  8045. -1:
  8046. { Don't make this optimisation if the CPU flags are required, since OR scrambles them }
  8047. if (cs_opt_size in current_settings.optimizerswitches) and
  8048. (taicpu(p).opsize <> S_B) and
  8049. not (RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
  8050. begin
  8051. { change "mov $-1,%reg" into "or $-1,%reg" }
  8052. { NOTES:
  8053. - No size saving is made when changing a Word-sized assignment unless the register is AX (smaller encoding)
  8054. - This operation creates a false dependency on the register, so only do it when optimising for size
  8055. - It is possible to set memory operands using this method, but this creates an even greater false dependency, so don't do this at all
  8056. }
  8057. taicpu(p).opcode := A_OR;
  8058. Result := True;
  8059. end;
  8060. end;
  8061. end;
  8062. end;
  8063. function TX86AsmOptimizer.PostPeepholeOptAnd(var p : tai) : boolean;
  8064. var
  8065. hp1: tai;
  8066. begin
  8067. { Detect:
  8068. andw x, %ax (0 <= x < $8000)
  8069. ...
  8070. movzwl %ax,%eax
  8071. Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
  8072. }
  8073. Result := False; if MatchOpType(taicpu(p), top_const, top_reg) and
  8074. (taicpu(p).oper[1]^.reg = NR_AX) and { This is also enough to determine that opsize = S_W }
  8075. ((taicpu(p).oper[0]^.val and $7FFF) = taicpu(p).oper[0]^.val) and
  8076. GetNextInstructionUsingReg(p, hp1, NR_EAX) and
  8077. MatchInstruction(hp1, A_MOVZX, [S_WL]) and
  8078. MatchOperand(taicpu(hp1).oper[0]^, NR_AX) and
  8079. MatchOperand(taicpu(hp1).oper[1]^, NR_EAX) then
  8080. begin
  8081. DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via AndMovz2AndCwtl)', hp1);
  8082. taicpu(hp1).opcode := A_CWDE;
  8083. taicpu(hp1).clearop(0);
  8084. taicpu(hp1).clearop(1);
  8085. taicpu(hp1).ops := 0;
  8086. { A change was made, but not with p, so move forward 1 }
  8087. p := tai(p.Next);
  8088. Result := True;
  8089. end;
  8090. end;
  8091. function TX86AsmOptimizer.PostPeepholeOptMOVSX(var p : tai) : boolean;
  8092. begin
  8093. Result := False;
  8094. if not MatchOpType(taicpu(p), top_reg, top_reg) then
  8095. Exit;
  8096. { Convert:
  8097. movswl %ax,%eax -> cwtl
  8098. movslq %eax,%rax -> cdqe
  8099. NOTE: Don't convert movswl %al,%ax to cbw, because cbw and cwde
  8100. refer to the same opcode and depends only on the assembler's
  8101. current operand-size attribute. [Kit]
  8102. }
  8103. with taicpu(p) do
  8104. case opsize of
  8105. S_WL:
  8106. if (oper[0]^.reg = NR_AX) and (oper[1]^.reg = NR_EAX) then
  8107. begin
  8108. DebugMsg(SPeepholeOptimization + 'Converted movswl %ax,%eax to cwtl', p);
  8109. opcode := A_CWDE;
  8110. clearop(0);
  8111. clearop(1);
  8112. ops := 0;
  8113. Result := True;
  8114. end;
  8115. {$ifdef x86_64}
  8116. S_LQ:
  8117. if (oper[0]^.reg = NR_EAX) and (oper[1]^.reg = NR_RAX) then
  8118. begin
  8119. DebugMsg(SPeepholeOptimization + 'Converted movslq %eax,%rax to cltq', p);
  8120. opcode := A_CDQE;
  8121. clearop(0);
  8122. clearop(1);
  8123. ops := 0;
  8124. Result := True;
  8125. end;
  8126. {$endif x86_64}
  8127. else
  8128. ;
  8129. end;
  8130. end;
  8131. function TX86AsmOptimizer.PostPeepholeOptShr(var p : tai) : boolean;
  8132. var
  8133. hp1: tai;
  8134. begin
  8135. { Detect:
  8136. shr x, %ax (x > 0)
  8137. ...
  8138. movzwl %ax,%eax
  8139. Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
  8140. }
  8141. Result := False;
  8142. if MatchOpType(taicpu(p), top_const, top_reg) and
  8143. (taicpu(p).oper[1]^.reg = NR_AX) and { This is also enough to determine that opsize = S_W }
  8144. (taicpu(p).oper[0]^.val > 0) and
  8145. GetNextInstructionUsingReg(p, hp1, NR_EAX) and
  8146. MatchInstruction(hp1, A_MOVZX, [S_WL]) and
  8147. MatchOperand(taicpu(hp1).oper[0]^, NR_AX) and
  8148. MatchOperand(taicpu(hp1).oper[1]^, NR_EAX) then
  8149. begin
  8150. DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via ShrMovz2ShrCwtl)', hp1);
  8151. taicpu(hp1).opcode := A_CWDE;
  8152. taicpu(hp1).clearop(0);
  8153. taicpu(hp1).clearop(1);
  8154. taicpu(hp1).ops := 0;
  8155. { A change was made, but not with p, so move forward 1 }
  8156. p := tai(p.Next);
  8157. Result := True;
  8158. end;
  8159. end;
  8160. function TX86AsmOptimizer.PostPeepholeOptCmp(var p : tai) : Boolean;
  8161. begin
  8162. Result:=false;
  8163. { change "cmp $0, %reg" to "test %reg, %reg" }
  8164. if MatchOpType(taicpu(p),top_const,top_reg) and
  8165. (taicpu(p).oper[0]^.val = 0) then
  8166. begin
  8167. taicpu(p).opcode := A_TEST;
  8168. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  8169. Result:=true;
  8170. end;
  8171. end;
  8172. function TX86AsmOptimizer.PostPeepholeOptTestOr(var p : tai) : Boolean;
  8173. var
  8174. IsTestConstX : Boolean;
  8175. hp1,hp2 : tai;
  8176. begin
  8177. Result:=false;
  8178. { removes the line marked with (x) from the sequence
  8179. and/or/xor/add/sub/... $x, %y
  8180. test/or %y, %y | test $-1, %y (x)
  8181. j(n)z _Label
  8182. as the first instruction already adjusts the ZF
  8183. %y operand may also be a reference }
  8184. IsTestConstX:=(taicpu(p).opcode=A_TEST) and
  8185. MatchOperand(taicpu(p).oper[0]^,-1);
  8186. if (OpsEqual(taicpu(p).oper[0]^,taicpu(p).oper[1]^) or IsTestConstX) and
  8187. GetLastInstruction(p, hp1) and
  8188. (tai(hp1).typ = ait_instruction) and
  8189. GetNextInstruction(p,hp2) and
  8190. MatchInstruction(hp2,A_SETcc,A_Jcc,A_CMOVcc,[]) then
  8191. case taicpu(hp1).opcode Of
  8192. A_ADD, A_SUB, A_OR, A_XOR, A_AND:
  8193. begin
  8194. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) and
  8195. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  8196. { and in case of carry for A(E)/B(E)/C/NC }
  8197. ((taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) or
  8198. ((taicpu(hp1).opcode <> A_ADD) and
  8199. (taicpu(hp1).opcode <> A_SUB))) then
  8200. begin
  8201. RemoveCurrentP(p, hp2);
  8202. Result:=true;
  8203. Exit;
  8204. end;
  8205. end;
  8206. A_SHL, A_SAL, A_SHR, A_SAR:
  8207. begin
  8208. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) and
  8209. { SHL/SAL/SHR/SAR with a value of 0 do not change the flags }
  8210. { therefore, it's only safe to do this optimization for }
  8211. { shifts by a (nonzero) constant }
  8212. (taicpu(hp1).oper[0]^.typ = top_const) and
  8213. (taicpu(hp1).oper[0]^.val <> 0) and
  8214. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  8215. { and in case of carry for A(E)/B(E)/C/NC }
  8216. (taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) then
  8217. begin
  8218. RemoveCurrentP(p, hp2);
  8219. Result:=true;
  8220. Exit;
  8221. end;
  8222. end;
  8223. A_DEC, A_INC, A_NEG:
  8224. begin
  8225. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) and
  8226. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  8227. { and in case of carry for A(E)/B(E)/C/NC }
  8228. (taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) then
  8229. begin
  8230. case taicpu(hp1).opcode of
  8231. A_DEC, A_INC:
  8232. { replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag }
  8233. begin
  8234. case taicpu(hp1).opcode Of
  8235. A_DEC: taicpu(hp1).opcode := A_SUB;
  8236. A_INC: taicpu(hp1).opcode := A_ADD;
  8237. else
  8238. ;
  8239. end;
  8240. taicpu(hp1).loadoper(1,taicpu(hp1).oper[0]^);
  8241. taicpu(hp1).loadConst(0,1);
  8242. taicpu(hp1).ops:=2;
  8243. end;
  8244. else
  8245. ;
  8246. end;
  8247. RemoveCurrentP(p, hp2);
  8248. Result:=true;
  8249. Exit;
  8250. end;
  8251. end
  8252. else
  8253. ;
  8254. end; { case }
  8255. { change "test $-1,%reg" into "test %reg,%reg" }
  8256. if IsTestConstX and (taicpu(p).oper[1]^.typ=top_reg) then
  8257. taicpu(p).loadoper(0,taicpu(p).oper[1]^);
  8258. { Change "or %reg,%reg" to "test %reg,%reg" as OR generates a false dependency }
  8259. if MatchInstruction(p, A_OR, []) and
  8260. { Can only match if they're both registers }
  8261. MatchOperand(taicpu(p).oper[0]^, taicpu(p).oper[1]^) then
  8262. begin
  8263. DebugMsg(SPeepholeOptimization + 'or %reg,%reg -> test %reg,%reg to remove false dependency (Or2Test)', p);
  8264. taicpu(p).opcode := A_TEST;
  8265. { No need to set Result to True, as we've done all the optimisations we can }
  8266. end;
  8267. end;
  8268. function TX86AsmOptimizer.PostPeepholeOptCall(var p : tai) : Boolean;
  8269. var
  8270. hp1,hp3 : tai;
  8271. {$ifndef x86_64}
  8272. hp2 : taicpu;
  8273. {$endif x86_64}
  8274. begin
  8275. Result:=false;
  8276. hp3:=nil;
  8277. {$ifndef x86_64}
  8278. { don't do this on modern CPUs, this really hurts them due to
  8279. broken call/ret pairing }
  8280. if (current_settings.optimizecputype < cpu_Pentium2) and
  8281. not(cs_create_pic in current_settings.moduleswitches) and
  8282. GetNextInstruction(p, hp1) and
  8283. MatchInstruction(hp1,A_JMP,[S_NO]) and
  8284. MatchOpType(taicpu(hp1),top_ref) and
  8285. (taicpu(hp1).oper[0]^.ref^.refaddr=addr_full) then
  8286. begin
  8287. hp2 := taicpu.Op_sym(A_PUSH,S_L,taicpu(hp1).oper[0]^.ref^.symbol);
  8288. InsertLLItem(p.previous, p, hp2);
  8289. taicpu(p).opcode := A_JMP;
  8290. taicpu(p).is_jmp := true;
  8291. RemoveInstruction(hp1);
  8292. Result:=true;
  8293. end
  8294. else
  8295. {$endif x86_64}
  8296. { replace
  8297. call procname
  8298. ret
  8299. by
  8300. jmp procname
  8301. but do it only on level 4 because it destroys stack back traces
  8302. else if the subroutine is marked as no return, remove the ret
  8303. }
  8304. if ((cs_opt_level4 in current_settings.optimizerswitches) or
  8305. (po_noreturn in current_procinfo.procdef.procoptions)) and
  8306. GetNextInstruction(p, hp1) and
  8307. (MatchInstruction(hp1,A_RET,[S_NO]) or
  8308. (MatchInstruction(hp1,A_VZEROUPPER,[S_NO]) and
  8309. SetAndTest(hp1,hp3) and
  8310. GetNextInstruction(hp1,hp1) and
  8311. MatchInstruction(hp1,A_RET,[S_NO])
  8312. )
  8313. ) and
  8314. (taicpu(hp1).ops=0) then
  8315. begin
  8316. if (cs_opt_level4 in current_settings.optimizerswitches) and
  8317. { we might destroy stack alignment here if we do not do a call }
  8318. (target_info.stackalign<=sizeof(SizeUInt)) then
  8319. begin
  8320. taicpu(p).opcode := A_JMP;
  8321. taicpu(p).is_jmp := true;
  8322. DebugMsg(SPeepholeOptimization + 'CallRet2Jmp done',p);
  8323. end
  8324. else
  8325. DebugMsg(SPeepholeOptimization + 'CallRet2Call done',p);
  8326. RemoveInstruction(hp1);
  8327. if Assigned(hp3) then
  8328. begin
  8329. AsmL.Remove(hp3);
  8330. AsmL.InsertBefore(hp3,p)
  8331. end;
  8332. Result:=true;
  8333. end;
  8334. end;
  8335. function TX86AsmOptimizer.PostPeepholeOptMovzx(var p : tai) : Boolean;
  8336. function ConstInRange(const Val: TCGInt; const OpSize: TOpSize): Boolean;
  8337. begin
  8338. case OpSize of
  8339. S_B, S_BW, S_BL{$ifdef x86_64}, S_BQ{$endif x86_64}:
  8340. Result := (Val <= $FF) and (Val >= -128);
  8341. S_W, S_WL{$ifdef x86_64}, S_WQ{$endif x86_64}:
  8342. Result := (Val <= $FFFF) and (Val >= -32768);
  8343. S_L{$ifdef x86_64}, S_LQ{$endif x86_64}:
  8344. Result := (Val <= $FFFFFFFF) and (Val >= -2147483648);
  8345. else
  8346. Result := True;
  8347. end;
  8348. end;
  8349. var
  8350. hp1, hp2 : tai;
  8351. SizeChange: Boolean;
  8352. PreMessage: string;
  8353. begin
  8354. Result := False;
  8355. if (taicpu(p).oper[0]^.typ = top_reg) and
  8356. SuperRegistersEqual(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^.reg) and
  8357. GetNextInstruction(p, hp1) and (hp1.typ = ait_instruction) then
  8358. begin
  8359. { Change (using movzbl %al,%eax as an example):
  8360. movzbl %al, %eax movzbl %al, %eax
  8361. cmpl x, %eax testl %eax,%eax
  8362. To:
  8363. cmpb x, %al testb %al, %al (Move one back to avoid a false dependency)
  8364. movzbl %al, %eax movzbl %al, %eax
  8365. Smaller instruction and minimises pipeline stall as the CPU
  8366. doesn't have to wait for the register to get zero-extended. [Kit]
  8367. Also allow if the smaller of the two registers is being checked,
  8368. as this still removes the false dependency.
  8369. }
  8370. if
  8371. (
  8372. (
  8373. (taicpu(hp1).opcode = A_CMP) and MatchOpType(taicpu(hp1), top_const, top_reg) and
  8374. ConstInRange(taicpu(hp1).oper[0]^.val, taicpu(p).opsize)
  8375. ) or (
  8376. { If MatchOperand returns True, they must both be registers }
  8377. (taicpu(hp1).opcode = A_TEST) and MatchOperand(taicpu(hp1).oper[0]^, taicpu(hp1).oper[1]^)
  8378. )
  8379. ) and
  8380. (reg2opsize(taicpu(hp1).oper[1]^.reg) <= reg2opsize(taicpu(p).oper[1]^.reg)) and
  8381. SuperRegistersEqual(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[1]^.reg) then
  8382. begin
  8383. PreMessage := debug_op2str(taicpu(hp1).opcode) + debug_opsize2str(taicpu(hp1).opsize) + ' ' + debug_operstr(taicpu(hp1).oper[0]^) + ',' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' -> ' + debug_op2str(taicpu(hp1).opcode);
  8384. asml.Remove(hp1);
  8385. asml.InsertBefore(hp1, p);
  8386. { Swap instructions in the case of cmp 0,%reg or test %reg,%reg }
  8387. if (taicpu(hp1).opcode = A_TEST) or (taicpu(hp1).oper[0]^.val = 0) then
  8388. begin
  8389. taicpu(hp1).opcode := A_TEST;
  8390. taicpu(hp1).loadreg(0, taicpu(p).oper[0]^.reg);
  8391. end;
  8392. taicpu(hp1).oper[1]^.reg := taicpu(p).oper[0]^.reg;
  8393. case taicpu(p).opsize of
  8394. S_BW, S_BL:
  8395. begin
  8396. SizeChange := taicpu(hp1).opsize <> S_B;
  8397. taicpu(hp1).changeopsize(S_B);
  8398. end;
  8399. S_WL:
  8400. begin
  8401. SizeChange := taicpu(hp1).opsize <> S_W;
  8402. taicpu(hp1).changeopsize(S_W);
  8403. end
  8404. else
  8405. InternalError(2020112701);
  8406. end;
  8407. UpdateUsedRegs(tai(p.Next));
  8408. { Check if the register is used aferwards - if not, we can
  8409. remove the movzx instruction completely }
  8410. if not RegUsedAfterInstruction(taicpu(hp1).oper[1]^.reg, p, UsedRegs) then
  8411. begin
  8412. { Hp1 is a better position than p for debugging purposes }
  8413. DebugMsg(SPeepholeOptimization + 'Movzx2Nop 4a', hp1);
  8414. RemoveCurrentp(p, hp1);
  8415. Result := True;
  8416. end;
  8417. if SizeChange then
  8418. DebugMsg(SPeepholeOptimization + PreMessage +
  8419. debug_opsize2str(taicpu(hp1).opsize) + ' ' + debug_operstr(taicpu(hp1).oper[0]^) + ',' + debug_regname(taicpu(hp1).oper[1]^.reg) + ' (smaller and minimises pipeline stall - MovzxCmp2CmpMovzx)', hp1)
  8420. else
  8421. DebugMsg(SPeepholeOptimization + 'MovzxCmp2CmpMovzx', hp1);
  8422. Exit;
  8423. end;
  8424. { Change (using movzwl %ax,%eax as an example):
  8425. movzwl %ax, %eax
  8426. movb %al, (dest) (Register is smaller than read register in movz)
  8427. To:
  8428. movb %al, (dest) (Move one back to avoid a false dependency)
  8429. movzwl %ax, %eax
  8430. }
  8431. if (taicpu(hp1).opcode = A_MOV) and
  8432. (taicpu(hp1).oper[0]^.typ = top_reg) and
  8433. not RegInOp(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^) and
  8434. SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(p).oper[0]^.reg) and
  8435. (reg2opsize(taicpu(hp1).oper[0]^.reg) <= reg2opsize(taicpu(p).oper[0]^.reg)) then
  8436. begin
  8437. DebugMsg(SPeepholeOptimization + 'MovzxMov2MovMovzx', hp1);
  8438. hp2 := tai(hp1.Previous); { Effectively the old position of hp1 }
  8439. asml.Remove(hp1);
  8440. asml.InsertBefore(hp1, p);
  8441. if taicpu(hp1).oper[1]^.typ = top_reg then
  8442. AllocRegBetween(taicpu(hp1).oper[1]^.reg, hp1, hp2, UsedRegs);
  8443. { Check if the register is used aferwards - if not, we can
  8444. remove the movzx instruction completely }
  8445. if not RegUsedAfterInstruction(taicpu(hp1).oper[0]^.reg, p, UsedRegs) then
  8446. begin
  8447. { Hp1 is a better position than p for debugging purposes }
  8448. DebugMsg(SPeepholeOptimization + 'Movzx2Nop 4b', hp1);
  8449. RemoveCurrentp(p, hp1);
  8450. Result := True;
  8451. end;
  8452. Exit;
  8453. end;
  8454. end;
  8455. {$ifdef x86_64}
  8456. { Code size reduction by J. Gareth "Kit" Moreton }
  8457. { Convert MOVZBQ and MOVZWQ to MOVZBL and MOVZWL respectively if it removes the REX prefix }
  8458. if (taicpu(p).opsize in [S_BQ, S_WQ]) and
  8459. (getsupreg(taicpu(p).oper[1]^.reg) in [RS_RAX, RS_RCX, RS_RDX, RS_RBX, RS_RSI, RS_RDI, RS_RBP, RS_RSP])
  8460. then
  8461. begin
  8462. { Has 64-bit register name and opcode suffix }
  8463. PreMessage := 'movz' + debug_opsize2str(taicpu(p).opsize) + ' ' + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' -> movz';
  8464. { The actual optimization }
  8465. setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
  8466. if taicpu(p).opsize = S_BQ then
  8467. taicpu(p).changeopsize(S_BL)
  8468. else
  8469. taicpu(p).changeopsize(S_WL);
  8470. DebugMsg(SPeepholeOptimization + PreMessage +
  8471. debug_opsize2str(taicpu(p).opsize) + ' ' + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' (removes REX prefix)', p);
  8472. end;
  8473. {$endif}
  8474. end;
  8475. {$ifdef x86_64}
  8476. function TX86AsmOptimizer.PostPeepholeOptXor(var p : tai) : Boolean;
  8477. var
  8478. PreMessage, RegName: string;
  8479. begin
  8480. { Code size reduction by J. Gareth "Kit" Moreton }
  8481. { change "xorq %reg,%reg" to "xorl %reg,%reg" for %rax, %rcx, %rdx, %rbx, %rsi, %rdi, %rbp and %rsp,
  8482. as this removes the REX prefix }
  8483. Result := False;
  8484. if not OpsEqual(taicpu(p).oper[0]^,taicpu(p).oper[1]^) then
  8485. Exit;
  8486. if taicpu(p).oper[0]^.typ <> top_reg then
  8487. { Should be impossible if both operands were equal, since one of XOR's operands must be a register }
  8488. InternalError(2018011500);
  8489. case taicpu(p).opsize of
  8490. S_Q:
  8491. begin
  8492. if (getsupreg(taicpu(p).oper[0]^.reg) in [RS_RAX, RS_RCX, RS_RDX, RS_RBX, RS_RSI, RS_RDI, RS_RBP, RS_RSP]) then
  8493. begin
  8494. RegName := debug_regname(taicpu(p).oper[0]^.reg); { 64-bit register name }
  8495. PreMessage := 'xorq ' + RegName + ',' + RegName + ' -> xorl ';
  8496. { The actual optimization }
  8497. setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
  8498. setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
  8499. taicpu(p).changeopsize(S_L);
  8500. RegName := debug_regname(taicpu(p).oper[0]^.reg); { 32-bit register name }
  8501. DebugMsg(SPeepholeOptimization + PreMessage + RegName + ',' + RegName + ' (removes REX prefix)', p);
  8502. end;
  8503. end;
  8504. else
  8505. ;
  8506. end;
  8507. end;
  8508. {$endif}
  8509. class procedure TX86AsmOptimizer.OptimizeRefs(var p: taicpu);
  8510. var
  8511. OperIdx: Integer;
  8512. begin
  8513. for OperIdx := 0 to p.ops - 1 do
  8514. if p.oper[OperIdx]^.typ = top_ref then
  8515. optimize_ref(p.oper[OperIdx]^.ref^, False);
  8516. end;
  8517. end.