aasmcpu.pas 199 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Peter Vreman
  3. Contains the abstract assembler implementation for the i386
  4. * Portions of this code was inspired by the NASM sources
  5. The Netwide Assembler is Copyright (c) 1996 Simon Tatham and
  6. Julian Hall. All rights reserved.
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. ****************************************************************************
  19. }
  20. unit aasmcpu;
  21. {$i fpcdefs.inc}
  22. interface
  23. uses
  24. globtype,verbose,
  25. cpubase,
  26. cgbase,cgutils,
  27. aasmbase,aasmtai,aasmsym,
  28. ogbase;
  29. const
  30. { "mov reg,reg" source operand number }
  31. O_MOV_SOURCE = 0;
  32. { "mov reg,reg" destination operand number }
  33. O_MOV_DEST = 1;
  34. { Operand types }
  35. OT_NONE = $00000000;
  36. { Bits 0..7: sizes }
  37. OT_BITS8 = $00000001;
  38. OT_BITS16 = $00000002;
  39. OT_BITS32 = $00000004;
  40. OT_BITS64 = $00000008; { x86_64 and FPU }
  41. //OT_BITS128 = $10000000; { 16 byte SSE }
  42. //OT_BITS256 = $20000000; { 32 byte AVX }
  43. //OT_BITS512 = $40000000; { 64 byte AVX512 }
  44. OT_BITS128 = $20000000; { 16 byte SSE }
  45. OT_BITS256 = $40000000; { 32 byte AVX }
  46. OT_BITS512 = $80000000; { 64 byte AVX512 }
  47. OT_VECTORMASK = $1000000000; { OPTIONAL VECTORMASK AVX512}
  48. OT_VECTORZERO = $2000000000; { OPTIONAL ZERO-FLAG AVX512}
  49. OT_VECTORBCST = $4000000000; { BROADCAST-MEM-FLAG AVX512}
  50. OT_VECTORSAE = $8000000000; { OPTIONAL SAE-FLAG AVX512}
  51. OT_VECTORER = $10000000000; { OPTIONAL ER-FLAG-FLAG AVX512}
  52. OT_VECTOR_EXT = OT_VECTORMASK or OT_VECTORZERO or OT_VECTORBCST or OT_VECTORSAE or OT_VECTORER;
  53. OT_BITSB32 = OT_BITS32 or OT_VECTORBCST;
  54. OT_BITSB64 = OT_BITS64 or OT_VECTORBCST;
  55. OT_BITS80 = $00000010; { FPU only }
  56. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  57. OT_NEAR = $00000040;
  58. OT_SHORT = $00000080;
  59. { TODO: FAR/NEAR/SHORT are sizes too, they should be included into size mask,
  60. but this requires adjusting the opcode table }
  61. //OT_SIZE_MASK = $3000001F; { all the size attributes }
  62. OT_SIZE_MASK = $E000001F; { all the size attributes }
  63. OT_NON_SIZE = longint(not(longint(OT_SIZE_MASK)));
  64. { Bits 8..11: modifiers }
  65. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  66. OT_TO = $00000200; { reverse effect in FADD, FSUB &c }
  67. OT_COLON = $00000400; { operand is followed by a colon }
  68. OT_MODIFIER_MASK = $00000F00;
  69. { Bits 12..15: type of operand }
  70. OT_REGISTER = $00001000;
  71. OT_IMMEDIATE = $00002000;
  72. OT_MEMORY = $0000C000; { always includes 'OT_REGMEM' bit as well }
  73. OT_REGMEM = $00008000; { for r/m, ie EA, operands }
  74. OT_TYPE_MASK = OT_REGISTER or OT_IMMEDIATE or OT_MEMORY or OT_REGMEM;
  75. OT_REGNORM = OT_REGISTER or OT_REGMEM; { 'normal' reg, qualifies as EA }
  76. { Bits 20..22, 24..26: register classes
  77. otf_* consts are not used alone, only to build other constants. }
  78. otf_reg_cdt = $00100000;
  79. otf_reg_gpr = $00200000;
  80. otf_reg_sreg = $00400000;
  81. otf_reg_k = $00800000;
  82. otf_reg_fpu = $01000000;
  83. otf_reg_mmx = $02000000;
  84. otf_reg_xmm = $04000000;
  85. otf_reg_ymm = $08000000;
  86. otf_reg_zmm = $10000000;
  87. otf_reg_extra_mask = $0F000000;
  88. { Bits 16..19: subclasses, meaning depends on classes field }
  89. otf_sub0 = $00010000;
  90. otf_sub1 = $00020000;
  91. otf_sub2 = $00040000;
  92. otf_sub3 = $00080000;
  93. OT_REG_SMASK = otf_sub0 or otf_sub1 or otf_sub2 or otf_sub3;
  94. //OT_REG_EXTRA_MASK = $0F000000;
  95. OT_REG_EXTRA_MASK = $1F000000;
  96. OT_REG_TYPMASK = otf_reg_cdt or otf_reg_gpr or otf_reg_sreg or otf_reg_k or otf_reg_extra_mask;
  97. { register class 0: CRx, DRx and TRx }
  98. {$ifdef x86_64}
  99. OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS64;
  100. {$else x86_64}
  101. OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS32;
  102. {$endif x86_64}
  103. OT_REG_CREG = OT_REG_CDT or otf_sub0; { CRn }
  104. OT_REG_DREG = OT_REG_CDT or otf_sub1; { DRn }
  105. OT_REG_TREG = OT_REG_CDT or otf_sub2; { TRn }
  106. OT_REG_CR4 = OT_REG_CDT or otf_sub3; { CR4 (Pentium only) }
  107. { register class 1: general-purpose registers }
  108. OT_REG_GPR = OT_REGNORM or otf_reg_gpr;
  109. OT_RM_GPR = OT_REGMEM or otf_reg_gpr;
  110. OT_REG8 = OT_REG_GPR or OT_BITS8; { 8-bit GPR }
  111. OT_REG16 = OT_REG_GPR or OT_BITS16;
  112. OT_REG32 = OT_REG_GPR or OT_BITS32;
  113. OT_REG64 = OT_REG_GPR or OT_BITS64;
  114. { GPR subclass 0: accumulator: AL, AX, EAX or RAX }
  115. OT_REG_ACCUM = OT_REG_GPR or otf_sub0;
  116. OT_REG_AL = OT_REG_ACCUM or OT_BITS8;
  117. OT_REG_AX = OT_REG_ACCUM or OT_BITS16;
  118. OT_REG_EAX = OT_REG_ACCUM or OT_BITS32;
  119. {$ifdef x86_64}
  120. OT_REG_RAX = OT_REG_ACCUM or OT_BITS64;
  121. {$endif x86_64}
  122. { GPR subclass 1: counter: CL, CX, ECX or RCX }
  123. OT_REG_COUNT = OT_REG_GPR or otf_sub1;
  124. OT_REG_CL = OT_REG_COUNT or OT_BITS8;
  125. OT_REG_CX = OT_REG_COUNT or OT_BITS16;
  126. OT_REG_ECX = OT_REG_COUNT or OT_BITS32;
  127. {$ifdef x86_64}
  128. OT_REG_RCX = OT_REG_COUNT or OT_BITS64;
  129. {$endif x86_64}
  130. { GPR subclass 2: data register: DL, DX, EDX or RDX }
  131. OT_REG_DX = OT_REG_GPR or otf_sub2 or OT_BITS16;
  132. OT_REG_EDX = OT_REG_GPR or otf_sub2 or OT_BITS32;
  133. { register class 2: Segment registers }
  134. OT_REG_SREG = OT_REGISTER or otf_reg_sreg or OT_BITS16;
  135. OT_REG_CS = OT_REG_SREG or otf_sub0; { CS }
  136. OT_REG_DESS = OT_REG_SREG or otf_sub1; { DS, ES, SS (non-CS 86 registers) }
  137. OT_REG_FSGS = OT_REG_SREG or otf_sub2; { FS, GS (386 extended registers) }
  138. { register class 3: FPU registers }
  139. OT_FPUREG = OT_REGISTER or otf_reg_fpu;
  140. OT_FPU0 = OT_FPUREG or otf_sub0; { FPU stack register zero }
  141. { register class 4: MMX (both reg and r/m) }
  142. OT_MMXREG = OT_REGNORM or otf_reg_mmx;
  143. OT_MMXRM = OT_REGMEM or otf_reg_mmx;
  144. { register class 5: XMM (both reg and r/m) }
  145. OT_XMMREG = OT_REGNORM or otf_reg_xmm;
  146. OT_XMMRM = OT_REGMEM or otf_reg_xmm;
  147. OT_XMEM32 = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS32;
  148. OT_XMEM32_M = OT_XMEM32 or OT_VECTORMASK;
  149. OT_XMEM64 = OT_REGNORM or otf_reg_xmm or otf_reg_gpr or OT_BITS64;
  150. OT_XMEM64_M = OT_XMEM64 or OT_VECTORMASK;
  151. OT_XMMREG_M = OT_XMMREG or OT_VECTORMASK;
  152. OT_XMMREG_MZ = OT_XMMREG or OT_VECTORMASK or OT_VECTORZERO;
  153. OT_XMMRM_MZ = OT_XMMRM or OT_VECTORMASK or OT_VECTORZERO;
  154. OT_XMMREG_SAE = OT_XMMREG or OT_VECTORSAE;
  155. OT_XMMRM_SAE = OT_XMMRM or OT_VECTORSAE;
  156. OT_XMMREG_ER = OT_XMMREG or OT_VECTORER;
  157. OT_XMMRM_ER = OT_XMMRM or OT_VECTORER;
  158. { register class 5: YMM (both reg and r/m) }
  159. OT_YMMREG = OT_REGNORM or otf_reg_ymm;
  160. OT_YMMRM = OT_REGMEM or otf_reg_ymm;
  161. OT_YMEM32 = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS32;
  162. OT_YMEM32_M = OT_YMEM32 or OT_VECTORMASK;
  163. OT_YMEM64 = OT_REGNORM or otf_reg_ymm or otf_reg_gpr or OT_BITS64;
  164. OT_YMEM64_M = OT_YMEM64 or OT_VECTORMASK;
  165. OT_YMMREG_M = OT_YMMREG or OT_VECTORMASK;
  166. OT_YMMREG_MZ = OT_YMMREG or OT_VECTORMASK or OT_VECTORZERO;
  167. OT_YMMRM_MZ = OT_YMMRM or OT_VECTORMASK or OT_VECTORZERO;
  168. OT_YMMREG_SAE = OT_YMMREG or OT_VECTORSAE;
  169. OT_YMMRM_SAE = OT_YMMRM or OT_VECTORSAE;
  170. OT_YMMREG_ER = OT_YMMREG or OT_VECTORER;
  171. OT_YMMRM_ER = OT_YMMRM or OT_VECTORER;
  172. { register class 5: ZMM (both reg and r/m) }
  173. OT_ZMMREG = OT_REGNORM or otf_reg_zmm;
  174. OT_ZMMRM = OT_REGMEM or otf_reg_zmm;
  175. OT_ZMEM32 = OT_REGNORM or otf_reg_zmm or otf_reg_gpr or OT_BITS32;
  176. OT_ZMEM32_M = OT_ZMEM32 or OT_VECTORMASK;
  177. OT_ZMEM64 = OT_REGNORM or otf_reg_zmm or otf_reg_gpr or OT_BITS64;
  178. OT_ZMEM64_M = OT_ZMEM64 or OT_VECTORMASK;
  179. OT_ZMMREG_M = OT_ZMMREG or OT_VECTORMASK;
  180. OT_ZMMREG_MZ = OT_ZMMREG or OT_VECTORMASK or OT_VECTORZERO;
  181. OT_ZMMRM_MZ = OT_ZMMRM or OT_VECTORMASK or OT_VECTORZERO;
  182. OT_ZMMREG_SAE = OT_ZMMREG or OT_VECTORSAE;
  183. OT_ZMMRM_SAE = OT_ZMMRM or OT_VECTORSAE;
  184. OT_ZMMREG_ER = OT_ZMMREG or OT_VECTORER;
  185. OT_ZMMRM_ER = OT_ZMMRM or OT_VECTORER;
  186. OT_KREG = OT_REGNORM or otf_reg_k;
  187. OT_KREG_M = OT_KREG or OT_VECTORMASK;
  188. { Vector-Memory operands }
  189. OT_VMEM_ANY = OT_XMEM32 or OT_XMEM64 or OT_YMEM32 or OT_YMEM64 or OT_ZMEM32 or OT_ZMEM64;
  190. { Memory operands }
  191. OT_MEM8 = OT_MEMORY or OT_BITS8;
  192. OT_MEM16 = OT_MEMORY or OT_BITS16;
  193. OT_MEM16_M = OT_MEM16 or OT_VECTORMASK;
  194. OT_MEM32 = OT_MEMORY or OT_BITS32;
  195. OT_MEM32_M = OT_MEMORY or OT_BITS32 or OT_VECTORMASK;
  196. OT_BMEM32 = OT_MEMORY or OT_BITS32 or OT_VECTORBCST;
  197. OT_BMEM32_SAE= OT_MEMORY or OT_BITS32 or OT_VECTORBCST or OT_VECTORSAE;
  198. OT_MEM64 = OT_MEMORY or OT_BITS64;
  199. OT_MEM64_M = OT_MEMORY or OT_BITS64 or OT_VECTORMASK;
  200. OT_BMEM64 = OT_MEMORY or OT_BITS64 or OT_VECTORBCST;
  201. OT_BMEM64_SAE= OT_MEMORY or OT_BITS64 or OT_VECTORBCST or OT_VECTORSAE;
  202. OT_MEM128 = OT_MEMORY or OT_BITS128;
  203. OT_MEM128_M = OT_MEMORY or OT_BITS128 or OT_VECTORMASK;
  204. OT_MEM256 = OT_MEMORY or OT_BITS256;
  205. OT_MEM256_M = OT_MEMORY or OT_BITS256 or OT_VECTORMASK;
  206. OT_MEM512 = OT_MEMORY or OT_BITS512;
  207. OT_MEM512_M = OT_MEMORY or OT_BITS512 or OT_VECTORMASK;
  208. OT_MEM80 = OT_MEMORY or OT_BITS80;
  209. OT_MEM_OFFS = OT_MEMORY or otf_sub0; { special type of EA }
  210. { simple [address] offset }
  211. { Matches any type of r/m operand }
  212. OT_MEMORY_ANY = OT_MEMORY or OT_RM_GPR or OT_XMMRM or OT_MMXRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK;
  213. { Immediate operands }
  214. OT_IMM8 = OT_IMMEDIATE or OT_BITS8;
  215. OT_IMM16 = OT_IMMEDIATE or OT_BITS16;
  216. OT_IMM32 = OT_IMMEDIATE or OT_BITS32;
  217. OT_IMM64 = OT_IMMEDIATE or OT_BITS64;
  218. OT_ONENESS = otf_sub0; { special type of immediate operand }
  219. OT_UNITY = OT_IMMEDIATE or OT_ONENESS; { for shift/rotate instructions }
  220. OTVE_VECTOR_SAE = 1 shl 8;
  221. OTVE_VECTOR_ER = 1 shl 9;
  222. OTVE_VECTOR_ZERO = 1 shl 10;
  223. OTVE_VECTOR_WRITEMASK = 1 shl 11;
  224. OTVE_VECTOR_BCST = 1 shl 12;
  225. OTVE_VECTOR_BCST2 = 0;
  226. OTVE_VECTOR_BCST4 = 1 shl 4;
  227. OTVE_VECTOR_BCST8 = 1 shl 5;
  228. OTVE_VECTOR_BCST16 = 3 shl 4;
  229. OTVE_VECTOR_RNSAE = OTVE_VECTOR_ER or 0;
  230. OTVE_VECTOR_RDSAE = OTVE_VECTOR_ER or 1 shl 6;
  231. OTVE_VECTOR_RUSAE = OTVE_VECTOR_ER or 1 shl 7;
  232. OTVE_VECTOR_RZSAE = OTVE_VECTOR_ER or 3 shl 6;
  233. OTVE_VECTOR_BCST_MASK = OTVE_VECTOR_BCST2 or OTVE_VECTOR_BCST4 or OTVE_VECTOR_BCST8 or OTVE_VECTOR_BCST16;
  234. OTVE_VECTOR_ER_MASK = OTVE_VECTOR_RNSAE or OTVE_VECTOR_RDSAE or OTVE_VECTOR_RUSAE or OTVE_VECTOR_RZSAE;
  235. OTVE_VECTOR_MASK = OTVE_VECTOR_SAE or OTVE_VECTOR_ER or OTVE_VECTOR_ZERO or OTVE_VECTOR_WRITEMASK or OTVE_VECTOR_BCST;
  236. { Size of the instruction table converted by nasmconv.pas }
  237. {$if defined(x86_64)}
  238. instabentries = {$i x8664nop.inc}
  239. {$elseif defined(i386)}
  240. instabentries = {$i i386nop.inc}
  241. {$elseif defined(i8086)}
  242. instabentries = {$i i8086nop.inc}
  243. {$endif}
  244. maxinfolen = 10;
  245. type
  246. { What an instruction can change. Needed for optimizer and spilling code.
  247. Note: The order of this enumeration is should not be changed! }
  248. TInsChange = (Ch_None,
  249. {Read from a register}
  250. Ch_REAX, Ch_RECX, Ch_REDX, Ch_REBX, Ch_RESP, Ch_REBP, Ch_RESI, Ch_REDI,
  251. {write from a register}
  252. Ch_WEAX, Ch_WECX, Ch_WEDX, Ch_WEBX, Ch_WESP, Ch_WEBP, Ch_WESI, Ch_WEDI,
  253. {read and write from/to a register}
  254. Ch_RWEAX, Ch_RWECX, Ch_RWEDX, Ch_RWEBX, Ch_RWESP, Ch_RWEBP, Ch_RWESI, Ch_RWEDI,
  255. {modify the contents of a register with the purpose of using
  256. this changed content afterwards (add/sub/..., but e.g. not rep
  257. or movsd)}
  258. Ch_MEAX, Ch_MECX, Ch_MEDX, Ch_MEBX, Ch_MESP, Ch_MEBP, Ch_MESI, Ch_MEDI,
  259. {read individual flag bits from the flags register}
  260. Ch_RCarryFlag,Ch_RParityFlag,Ch_RAuxiliaryFlag,Ch_RZeroFlag,Ch_RSignFlag,Ch_ROverflowFlag,
  261. {write individual flag bits to the flags register}
  262. Ch_WCarryFlag,Ch_WParityFlag,Ch_WAuxiliaryFlag,Ch_WZeroFlag,Ch_WSignFlag,Ch_WOverflowFlag,
  263. {set individual flag bits to 0 in the flags register}
  264. Ch_W0CarryFlag,Ch_W0ParityFlag,Ch_W0AuxiliaryFlag,Ch_W0ZeroFlag,Ch_W0SignFlag,Ch_W0OverflowFlag,
  265. {set individual flag bits to 1 in the flags register}
  266. Ch_W1CarryFlag,Ch_W1ParityFlag,Ch_W1AuxiliaryFlag,Ch_W1ZeroFlag,Ch_W1SignFlag,Ch_W1OverflowFlag,
  267. {write an undefined value to individual flag bits in the flags register}
  268. Ch_WUCarryFlag,Ch_WUParityFlag,Ch_WUAuxiliaryFlag,Ch_WUZeroFlag,Ch_WUSignFlag,Ch_WUOverflowFlag,
  269. {read and write flag bits}
  270. Ch_RWCarryFlag,Ch_RWParityFlag,Ch_RWAuxiliaryFlag,Ch_RWZeroFlag,Ch_RWSignFlag,Ch_RWOverflowFlag,
  271. {more specialized flag bits (not considered part of NR_DEFAULTFLAGS by the compiler)}
  272. Ch_RDirFlag,Ch_W0DirFlag,Ch_W1DirFlag,Ch_W0IntFlag,Ch_W1IntFlag,
  273. {instruction reads flag bits, according to its condition (used by Jcc/SETcc/CMOVcc)}
  274. Ch_RFLAGScc,
  275. {read/write/read+write the entire flags/eflags/rflags register}
  276. Ch_RFlags, Ch_WFlags, Ch_RWFlags,
  277. Ch_FPU,
  278. Ch_Rop1, Ch_Wop1, Ch_RWop1, Ch_Mop1,
  279. Ch_Rop2, Ch_Wop2, Ch_RWop2, Ch_Mop2,
  280. Ch_Rop3, Ch_WOp3, Ch_RWOp3, Ch_Mop3,
  281. Ch_Rop4, Ch_WOp4, Ch_RWOp4, Ch_Mop4,
  282. { instruction doesn't read it's input register, in case both parameters
  283. are the same register (e.g. xor eax,eax; sub eax,eax; sbb eax,eax (reads flags only), etc.) }
  284. Ch_NoReadIfEqualRegs,
  285. Ch_RMemEDI,Ch_WMemEDI,
  286. Ch_All,
  287. { x86_64 registers }
  288. Ch_RRAX, Ch_RRCX, Ch_RRDX, Ch_RRBX, Ch_RRSP, Ch_RRBP, Ch_RRSI, Ch_RRDI,
  289. Ch_WRAX, Ch_WRCX, Ch_WRDX, Ch_WRBX, Ch_WRSP, Ch_WRBP, Ch_WRSI, Ch_WRDI,
  290. Ch_RWRAX, Ch_RWRCX, Ch_RWRDX, Ch_RWRBX, Ch_RWRSP, Ch_RWRBP, Ch_RWRSI, Ch_RWRDI,
  291. Ch_MRAX, Ch_MRCX, Ch_MRDX, Ch_MRBX, Ch_MRSP, Ch_MRBP, Ch_MRSI, Ch_MRDI
  292. );
  293. TInsProp = packed record
  294. Ch : set of TInsChange;
  295. end;
  296. TMemRefSizeInfo = (msiUnknown, msiUnsupported, msiNoSize, msiNoMemRef,
  297. msiMultiple, msiMultipleMinSize8, msiMultipleMinSize16, msiMultipleMinSize32,
  298. msiMultipleMinSize64, msiMultipleMinSize128, msiMultipleminSize256, msiMultipleMinSize512,
  299. msiMemRegSize, msiMemRegx16y32, msiMemRegx16y32z64, msiMemRegx32y64, msiMemRegx32y64z128, msiMemRegx64y128, msiMemRegx64y128z256,
  300. msiMemRegx64y256, msiMemRegx64y256z512,
  301. msiMem8, msiMem16, msiMem32, msiBMem32, msiMem64, msiBMem64, msiMem128, msiMem256, msiMem512,
  302. msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64,
  303. msiVMemMultiple, msiVMemRegSize,
  304. msiMemRegConst128,msiMemRegConst256,msiMemRegConst512);
  305. TMemRefSizeInfoBCST = (msbUnknown, msbBCST32, msbBCST64, msbMultiple);
  306. TMemRefSizeInfoBCSTType = (btUnknown, bt1to2, bt1to4, bt1to8, bt1to16);
  307. TEVEXTupleState = (etsUnknown, etsIsTuple, etsNotTuple);
  308. TConstSizeInfo = (csiUnknown, csiMultiple, csiNoSize, csiMem8, csiMem16, csiMem32, csiMem64);
  309. TInsTabMemRefSizeInfoRec = record
  310. MemRefSize : TMemRefSizeInfo;
  311. MemRefSizeBCST : TMemRefSizeInfoBCST;
  312. BCSTXMMMultiplicator : byte;
  313. ExistsSSEAVX : boolean;
  314. ConstSize : TConstSizeInfo;
  315. BCSTTypes : Set of TMemRefSizeInfoBCSTType;
  316. RegXMMSizeMask : int64;
  317. RegYMMSizeMask : int64;
  318. RegZMMSizeMask : int64;
  319. end;
  320. const
  321. MemRefMultiples: set of TMemRefSizeInfo = [msiMultiple, msiMultipleMinSize8,
  322. msiMultipleMinSize16, msiMultipleMinSize32,
  323. msiMultipleMinSize64, msiMultipleMinSize128,
  324. msiMultipleMinSize256, msiMultipleMinSize512,
  325. msiVMemMultiple];
  326. MemRefSizeInfoVMems: Set of TMemRefSizeInfo = [msiXMem32, msiXMem64, msiYMem32, msiYMem64,
  327. msiZMem32, msiZMem64,
  328. msiVMemMultiple, msiVMemRegSize];
  329. InsProp : array[tasmop] of TInsProp =
  330. {$if defined(x86_64)}
  331. {$i x8664pro.inc}
  332. {$elseif defined(i386)}
  333. {$i i386prop.inc}
  334. {$elseif defined(i8086)}
  335. {$i i8086prop.inc}
  336. {$endif}
  337. type
  338. TOperandOrder = (op_intel,op_att);
  339. {Instruction flags }
  340. tinsflag = (
  341. { please keep these in order and in sync with IF_SMASK }
  342. IF_SM, { size match first two operands }
  343. IF_SM2,
  344. IF_SB, { unsized operands can't be non-byte }
  345. IF_SW, { unsized operands can't be non-word }
  346. IF_SD, { unsized operands can't be nondword }
  347. { unsized argument spec }
  348. { please keep these in order and in sync with IF_ARMASK }
  349. IF_AR0, { SB, SW, SD applies to argument 0 }
  350. IF_AR1, { SB, SW, SD applies to argument 1 }
  351. IF_AR2, { SB, SW, SD applies to argument 2 }
  352. IF_PRIV, { it's a privileged instruction }
  353. IF_SMM, { it's only valid in SMM }
  354. IF_PROT, { it's protected mode only }
  355. IF_NOX86_64, { removed instruction in x86_64 }
  356. IF_UNDOC, { it's an undocumented instruction }
  357. IF_FPU, { it's an FPU instruction }
  358. IF_MMX, { it's an MMX instruction }
  359. { it's a 3DNow! instruction }
  360. IF_3DNOW,
  361. { it's a SSE (KNI, MMX2) instruction }
  362. IF_SSE,
  363. { SSE2 instructions }
  364. IF_SSE2,
  365. { SSE3 instructions }
  366. IF_SSE3,
  367. { SSE64 instructions }
  368. IF_SSE64,
  369. { SVM instructions }
  370. IF_SVM,
  371. { SSE4 instructions }
  372. IF_SSE4,
  373. IF_SSSE3,
  374. IF_SSE41,
  375. IF_SSE42,
  376. IF_MOVBE,
  377. IF_CLMUL,
  378. IF_AVX,
  379. IF_AVX2,
  380. IF_AVX512,
  381. IF_BMI1,
  382. IF_BMI2,
  383. { Intel ADX (Multi-Precision Add-Carry Instruction Extensions) }
  384. IF_ADX,
  385. IF_16BITONLY,
  386. IF_FMA,
  387. IF_FMA4,
  388. IF_TSX,
  389. IF_RAND,
  390. IF_XSAVE,
  391. IF_PREFETCHWT1,
  392. IF_SHA,
  393. { mask for processor level }
  394. { please keep these in order and in sync with IF_PLEVEL }
  395. IF_8086, { 8086 instruction }
  396. IF_186, { 186+ instruction }
  397. IF_286, { 286+ instruction }
  398. IF_386, { 386+ instruction }
  399. IF_486, { 486+ instruction }
  400. IF_PENT, { Pentium instruction }
  401. IF_P6, { P6 instruction }
  402. IF_KATMAI, { Katmai instructions }
  403. IF_WILLAMETTE, { Willamette instructions }
  404. IF_PRESCOTT, { Prescott instructions }
  405. IF_X86_64,
  406. IF_SANDYBRIDGE, { Sandybridge-specific instruction }
  407. IF_NEC, { NEC V20/V30 instruction }
  408. { the following are not strictly part of the processor level, because
  409. they are never used standalone, but always in combination with a
  410. separate processor level flag. Therefore, they use bits outside of
  411. IF_PLEVEL, otherwise they would mess up the processor level they're
  412. used in combination with.
  413. The following combinations are currently used:
  414. [IF_AMD, IF_P6],
  415. [IF_CYRIX, IF_486],
  416. [IF_CYRIX, IF_PENT],
  417. [IF_CYRIX, IF_P6] }
  418. IF_CYRIX, { Cyrix, Centaur or VIA-specific instruction }
  419. IF_AMD, { AMD-specific instruction }
  420. { added flags }
  421. IF_PRE, { it's a prefix instruction }
  422. IF_PASS2, { if the instruction can change in a second pass }
  423. IF_IMM4, { immediate operand is a nibble (must be in range [0..15]) }
  424. IF_IMM3, { immediate operand is a triad (must be in range [0..7]) }
  425. { avx512 flags }
  426. IF_BCST2,
  427. IF_BCST4,
  428. IF_BCST8,
  429. IF_BCST16,
  430. IF_T2, { disp8 - tuple - 2 }
  431. IF_T4, { disp8 - tuple - 4 }
  432. IF_T8, { disp8 - tuple - 8 }
  433. IF_T1S, { disp8 - tuple - 1 scalar }
  434. IF_T1S8, { disp8 - tuple - 1 scalar byte }
  435. IF_T1S16, { disp8 - tuple - 1 scalar word }
  436. IF_T1F32,
  437. IF_T1F64,
  438. IF_TMDDUP,
  439. IF_TFV, { disp8 - tuple - full vector }
  440. IF_TFVM, { disp8 - tuple - full vector memory }
  441. IF_TQVM,
  442. IF_TMEM128,
  443. IF_THV,
  444. IF_THVM,
  445. IF_TOVM
  446. );
  447. tinsflags=set of tinsflag;
  448. const
  449. IF_SMASK=[IF_SM,IF_SM2,IF_SB,IF_SW,IF_SD];
  450. IF_ARMASK=[IF_AR0,IF_AR1,IF_AR2]; { mask for unsized argument spec }
  451. IF_PLEVEL=[IF_8086..IF_NEC]; { mask for processor level }
  452. IF_TUPLEMASK=[IF_T2..IF_TOVM]; { mask for AVX512 disp8-tuples }
  453. type
  454. tinsentry=packed record
  455. opcode : tasmop;
  456. ops : byte;
  457. optypes : array[0..max_operands-1] of int64;
  458. code : array[0..maxinfolen] of char;
  459. flags : tinsflags;
  460. end;
  461. pinsentry=^tinsentry;
  462. { alignment for operator }
  463. tai_align = class(tai_align_abstract)
  464. function calculatefillbuf(var buf : tfillbuffer;executable : boolean):pchar;override;
  465. end;
  466. { taicpu }
  467. taicpu = class(tai_cpu_abstract_sym)
  468. opsize : topsize;
  469. constructor op_none(op : tasmop);
  470. constructor op_none(op : tasmop;_size : topsize);
  471. constructor op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  472. constructor op_const(op : tasmop;_size : topsize;_op1 : aint);
  473. constructor op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  474. constructor op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  475. constructor op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  476. constructor op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aint);
  477. constructor op_const_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister);
  478. constructor op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aint);
  479. constructor op_const_ref(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference);
  480. constructor op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  481. constructor op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  482. constructor op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;_op3 : tregister);
  483. constructor op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference;_op3 : tregister);
  484. constructor op_ref_reg_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2,_op3 : tregister);
  485. constructor op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;const _op3 : treference);
  486. constructor op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister;const _op3 : treference);
  487. constructor op_const_reg_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2, _op3, _op4 : tregister);
  488. { this is for Jmp instructions }
  489. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  490. constructor op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  491. constructor op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  492. constructor op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  493. constructor op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  494. procedure changeopsize(siz:topsize);
  495. function GetString:string;
  496. { This is a workaround for the GAS non commutative fpu instruction braindamage.
  497. Early versions of the UnixWare assembler had a bug where some fpu instructions
  498. were reversed and GAS still keeps this "feature" for compatibility.
  499. for details: http://sourceware.org/binutils/docs/as/i386_002dBugs.html#i386_002dBugs
  500. http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=372528
  501. http://en.wikibooks.org/wiki/X86_Assembly/GAS_Syntax#Caveats
  502. Since FPC is "GAS centric" due to its history it generates instructions with the same operand order so
  503. when generating output for other assemblers, the opcodes must be fixed before writing them.
  504. This function returns the fixed opcodes. Changing the opcodes permanently is no good idea
  505. because in case of smartlinking assembler is generated twice so at the second run wrong
  506. assembler is generated.
  507. }
  508. function FixNonCommutativeOpcodes: tasmop;
  509. private
  510. FOperandOrder : TOperandOrder;
  511. procedure init(_size : topsize); { this need to be called by all constructor }
  512. public
  513. { the next will reset all instructions that can change in pass 2 }
  514. procedure ResetPass1;override;
  515. procedure ResetPass2;override;
  516. function CheckIfValid:boolean;
  517. function Pass1(objdata:TObjData):longint;override;
  518. procedure Pass2(objdata:TObjData);override;
  519. procedure SetOperandOrder(order:TOperandOrder);
  520. function is_same_reg_move(regtype: Tregistertype):boolean;override;
  521. { register spilling code }
  522. function spilling_get_operation_type(opnr: longint): topertype;override;
  523. {$ifdef i8086}
  524. procedure loadsegsymbol(opidx:longint;s:tasmsymbol);
  525. {$endif i8086}
  526. property OperandOrder : TOperandOrder read FOperandOrder;
  527. private
  528. { next fields are filled in pass1, so pass2 is faster }
  529. insentry : PInsEntry;
  530. insoffset : longint;
  531. LastInsOffset : longint; { need to be public to be reset }
  532. inssize : shortint;
  533. EVEXTupleState: TEVEXTupleState; { AVX512 disp8*N }
  534. {$ifdef x86_64}
  535. rex : byte;
  536. {$endif x86_64}
  537. function InsEnd:longint;
  538. procedure create_ot(objdata:TObjData);
  539. function Matches(p:PInsEntry):boolean;
  540. function calcsize(p:PInsEntry):shortint;
  541. procedure gencode(objdata:TObjData);
  542. function NeedAddrPrefix(opidx:byte):boolean;
  543. function NeedAddrPrefix:boolean;
  544. procedure write0x66prefix(objdata:TObjData);
  545. procedure write0x67prefix(objdata:TObjData);
  546. procedure Swapoperands;
  547. function FindInsentry(objdata:TObjData):boolean;
  548. function CheckUseEVEX: boolean;
  549. procedure CheckEVEXTuple(const aInput:toper; aInsEntry: pInsentry; aIsVector128, aIsVector256, aIsVector512, aIsEVEXW1: boolean);
  550. end;
  551. function is_64_bit_ref(const ref:treference):boolean;
  552. function is_32_bit_ref(const ref:treference):boolean;
  553. function is_16_bit_ref(const ref:treference):boolean;
  554. function get_ref_address_size(const ref:treference):byte;
  555. function get_default_segment_of_ref(const ref:treference):tregister;
  556. procedure optimize_ref(var ref:treference; inlineasm: boolean);
  557. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  558. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  559. function MemRefInfo(aAsmop: TAsmOp): TInsTabMemRefSizeInfoRec;
  560. function MightHaveExtension(AsmOp : TAsmOp) : Boolean;
  561. procedure InitAsm;
  562. procedure DoneAsm;
  563. {*****************************************************************************
  564. External Symbol Chain
  565. used for agx86nsm and agx86int
  566. *****************************************************************************}
  567. type
  568. PExternChain = ^TExternChain;
  569. TExternChain = Record
  570. psym : pshortstring;
  571. is_defined : boolean;
  572. next : PExternChain;
  573. end;
  574. const
  575. FEC : PExternChain = nil;
  576. procedure AddSymbol(symname : string; defined : boolean);
  577. procedure FreeExternChainList;
  578. implementation
  579. uses
  580. cutils,
  581. globals,
  582. systems,
  583. itcpugas,
  584. cpuinfo;
  585. procedure AddSymbol(symname : string; defined : boolean);
  586. var
  587. EC : PExternChain;
  588. begin
  589. EC:=FEC;
  590. while assigned(EC) do
  591. begin
  592. if EC^.psym^=symname then
  593. begin
  594. if defined then
  595. EC^.is_defined:=true;
  596. exit;
  597. end;
  598. EC:=EC^.next;
  599. end;
  600. New(EC);
  601. EC^.next:=FEC;
  602. FEC:=EC;
  603. FEC^.psym:=stringdup(symname);
  604. FEC^.is_defined := defined;
  605. end;
  606. procedure FreeExternChainList;
  607. var
  608. EC : PExternChain;
  609. begin
  610. EC:=FEC;
  611. while assigned(EC) do
  612. begin
  613. FEC:=EC^.next;
  614. stringdispose(EC^.psym);
  615. Dispose(EC);
  616. EC:=FEC;
  617. end;
  618. end;
  619. {*****************************************************************************
  620. Instruction table
  621. *****************************************************************************}
  622. type
  623. TInsTabCache=array[TasmOp] of longint;
  624. PInsTabCache=^TInsTabCache;
  625. TInsTabMemRefSizeInfoCache=array[TasmOp] of TInsTabMemRefSizeInfoRec;
  626. PInsTabMemRefSizeInfoCache=^TInsTabMemRefSizeInfoCache;
  627. const
  628. {$if defined(x86_64)}
  629. InsTab:array[0..instabentries-1] of TInsEntry={$i x8664tab.inc}
  630. {$elseif defined(i386)}
  631. InsTab:array[0..instabentries-1] of TInsEntry={$i i386tab.inc}
  632. {$elseif defined(i8086)}
  633. InsTab:array[0..instabentries-1] of TInsEntry={$i i8086tab.inc}
  634. {$endif}
  635. var
  636. InsTabCache : PInsTabCache;
  637. InsTabMemRefSizeInfoCache: PInsTabMemRefSizeInfoCache;
  638. const
  639. {$if defined(x86_64)}
  640. { Intel style operands ! }
  641. opsize_2_type:array[0..2,topsize] of int64=(
  642. (OT_NONE,
  643. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,OT_BITS64,OT_BITS64,OT_BITS64,
  644. OT_BITS16,OT_BITS32,OT_BITS64,
  645. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  646. OT_BITS64,
  647. OT_NEAR,OT_FAR,OT_SHORT,
  648. OT_NONE,
  649. OT_BITS128,
  650. OT_BITS256,
  651. OT_BITS512
  652. ),
  653. (OT_NONE,
  654. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,OT_BITS8,OT_BITS16,OT_BITS32,
  655. OT_BITS16,OT_BITS32,OT_BITS64,
  656. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  657. OT_BITS64,
  658. OT_NEAR,OT_FAR,OT_SHORT,
  659. OT_NONE,
  660. OT_BITS128,
  661. OT_BITS256,
  662. OT_BITS512
  663. ),
  664. (OT_NONE,
  665. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,
  666. OT_BITS16,OT_BITS32,OT_BITS64,
  667. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  668. OT_BITS64,
  669. OT_NEAR,OT_FAR,OT_SHORT,
  670. OT_NONE,
  671. OT_BITS128,
  672. OT_BITS256,
  673. OT_BITS512
  674. )
  675. );
  676. reg_ot_table : array[tregisterindex] of longint = (
  677. {$i r8664ot.inc}
  678. );
  679. {$elseif defined(i386)}
  680. { Intel style operands ! }
  681. opsize_2_type:array[0..2,topsize] of int64=(
  682. (OT_NONE,
  683. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,
  684. OT_BITS16,OT_BITS32,OT_BITS64,
  685. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  686. OT_BITS64,
  687. OT_NEAR,OT_FAR,OT_SHORT,
  688. OT_NONE,
  689. OT_BITS128,
  690. OT_BITS256,
  691. OT_BITS512
  692. ),
  693. (OT_NONE,
  694. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,
  695. OT_BITS16,OT_BITS32,OT_BITS64,
  696. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  697. OT_BITS64,
  698. OT_NEAR,OT_FAR,OT_SHORT,
  699. OT_NONE,
  700. OT_BITS128,
  701. OT_BITS256,
  702. OT_BITS512
  703. ),
  704. (OT_NONE,
  705. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,
  706. OT_BITS16,OT_BITS32,OT_BITS64,
  707. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  708. OT_BITS64,
  709. OT_NEAR,OT_FAR,OT_SHORT,
  710. OT_NONE,
  711. OT_BITS128,
  712. OT_BITS256,
  713. OT_BITS512
  714. )
  715. );
  716. reg_ot_table : array[tregisterindex] of longint = (
  717. {$i r386ot.inc}
  718. );
  719. {$elseif defined(i8086)}
  720. { Intel style operands ! }
  721. opsize_2_type:array[0..2,topsize] of int64=(
  722. (OT_NONE,
  723. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,
  724. OT_BITS16,OT_BITS32,OT_BITS64,
  725. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  726. OT_BITS64,
  727. OT_NEAR,OT_FAR,OT_SHORT,
  728. OT_NONE,
  729. OT_BITS128,
  730. OT_BITS256,
  731. OT_BITS512
  732. ),
  733. (OT_NONE,
  734. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,
  735. OT_BITS16,OT_BITS32,OT_BITS64,
  736. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  737. OT_BITS64,
  738. OT_NEAR,OT_FAR,OT_SHORT,
  739. OT_NONE,
  740. OT_BITS128,
  741. OT_BITS256,
  742. OT_BITS512
  743. ),
  744. (OT_NONE,
  745. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,
  746. OT_BITS16,OT_BITS32,OT_BITS64,
  747. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  748. OT_BITS64,
  749. OT_NEAR,OT_FAR,OT_SHORT,
  750. OT_NONE,
  751. OT_BITS128,
  752. OT_BITS256,
  753. OT_BITS512
  754. )
  755. );
  756. reg_ot_table : array[tregisterindex] of longint = (
  757. {$i r8086ot.inc}
  758. );
  759. {$endif}
  760. function MemRefInfo(aAsmop: TAsmOp): TInsTabMemRefSizeInfoRec;
  761. begin
  762. result := InsTabMemRefSizeInfoCache^[aAsmop];
  763. end;
  764. function MightHaveExtension(AsmOp : TAsmOp): Boolean;
  765. var
  766. i,j: LongInt;
  767. insentry: pinsentry;
  768. begin
  769. Result:=true;
  770. i:=InsTabCache^[AsmOp];
  771. if i>=0 then
  772. begin
  773. insentry:=@instab[i];
  774. while insentry^.opcode=AsmOp do
  775. begin
  776. for j:=0 to insentry^.ops-1 do
  777. begin
  778. if (insentry^.optypes[j] and OT_VECTOR_EXT)<>0 then
  779. exit;
  780. end;
  781. inc(i);
  782. insentry:=@instab[i];
  783. end;
  784. end;
  785. Result:=false;
  786. end;
  787. { Operation type for spilling code }
  788. type
  789. toperation_type_table=array[tasmop,0..Max_Operands] of topertype;
  790. var
  791. operation_type_table : ^toperation_type_table;
  792. {****************************************************************************
  793. TAI_ALIGN
  794. ****************************************************************************}
  795. function tai_align.calculatefillbuf(var buf : tfillbuffer;executable : boolean):pchar;
  796. const
  797. { Updated according to
  798. Software Optimization Guide for AMD Family 15h Processors, Verison 3.08, January 2014
  799. and
  800. Intel 64 and IA-32 Architectures Software Developer’s Manual
  801. Volume 2B: Instruction Set Reference, N-Z, January 2015
  802. }
  803. {$ifndef i8086}
  804. alignarray_cmovcpus:array[0..10] of string[11]=(
  805. #$66#$66#$66#$0F#$1F#$84#$00#$00#$00#$00#$00,
  806. #$66#$66#$0F#$1F#$84#$00#$00#$00#$00#$00,
  807. #$66#$0F#$1F#$84#$00#$00#$00#$00#$00,
  808. #$0F#$1F#$84#$00#$00#$00#$00#$00,
  809. #$0F#$1F#$80#$00#$00#$00#$00,
  810. #$66#$0F#$1F#$44#$00#$00,
  811. #$0F#$1F#$44#$00#$00,
  812. #$0F#$1F#$40#$00,
  813. #$0F#$1F#$00,
  814. #$66#$90,
  815. #$90);
  816. {$endif i8086}
  817. {$ifdef i8086}
  818. alignarray:array[0..5] of string[8]=(
  819. #$90#$90#$90#$90#$90#$90#$90,
  820. #$90#$90#$90#$90#$90#$90,
  821. #$90#$90#$90#$90,
  822. #$90#$90#$90,
  823. #$90#$90,
  824. #$90);
  825. {$else i8086}
  826. alignarray:array[0..5] of string[8]=(
  827. #$8D#$B4#$26#$00#$00#$00#$00,
  828. #$8D#$B6#$00#$00#$00#$00,
  829. #$8D#$74#$26#$00,
  830. #$8D#$76#$00,
  831. #$89#$F6,
  832. #$90);
  833. {$endif i8086}
  834. var
  835. bufptr : pchar;
  836. j : longint;
  837. localsize: byte;
  838. begin
  839. inherited calculatefillbuf(buf,executable);
  840. if not(use_op) and executable then
  841. begin
  842. bufptr:=pchar(@buf);
  843. { fillsize may still be used afterwards, so don't modify }
  844. { e.g. writebytes(hp.calculatefillbuf(buf)^,hp.fillsize) }
  845. localsize:=fillsize;
  846. while (localsize>0) do
  847. begin
  848. {$ifndef i8086}
  849. if (CPUX86_HAS_CMOV in cpu_capabilities[current_settings.cputype]) then
  850. begin
  851. for j:=low(alignarray_cmovcpus) to high(alignarray_cmovcpus) do
  852. if (localsize>=length(alignarray_cmovcpus[j])) then
  853. break;
  854. move(alignarray_cmovcpus[j][1],bufptr^,length(alignarray_cmovcpus[j]));
  855. inc(bufptr,length(alignarray_cmovcpus[j]));
  856. dec(localsize,length(alignarray_cmovcpus[j]));
  857. end
  858. else
  859. {$endif not i8086}
  860. begin
  861. for j:=low(alignarray) to high(alignarray) do
  862. if (localsize>=length(alignarray[j])) then
  863. break;
  864. move(alignarray[j][1],bufptr^,length(alignarray[j]));
  865. inc(bufptr,length(alignarray[j]));
  866. dec(localsize,length(alignarray[j]));
  867. end
  868. end;
  869. end;
  870. calculatefillbuf:=pchar(@buf);
  871. end;
  872. {*****************************************************************************
  873. Taicpu Constructors
  874. *****************************************************************************}
  875. procedure taicpu.changeopsize(siz:topsize);
  876. begin
  877. opsize:=siz;
  878. end;
  879. procedure taicpu.init(_size : topsize);
  880. begin
  881. { default order is att }
  882. FOperandOrder:=op_att;
  883. segprefix:=NR_NO;
  884. opsize:=_size;
  885. insentry:=nil;
  886. LastInsOffset:=-1;
  887. InsOffset:=0;
  888. InsSize:=0;
  889. EVEXTupleState := etsUnknown;
  890. end;
  891. constructor taicpu.op_none(op : tasmop);
  892. begin
  893. inherited create(op);
  894. init(S_NO);
  895. end;
  896. constructor taicpu.op_none(op : tasmop;_size : topsize);
  897. begin
  898. inherited create(op);
  899. init(_size);
  900. end;
  901. constructor taicpu.op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  902. begin
  903. inherited create(op);
  904. init(_size);
  905. ops:=1;
  906. loadreg(0,_op1);
  907. end;
  908. constructor taicpu.op_const(op : tasmop;_size : topsize;_op1 : aint);
  909. begin
  910. inherited create(op);
  911. init(_size);
  912. ops:=1;
  913. loadconst(0,_op1);
  914. end;
  915. constructor taicpu.op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  916. begin
  917. inherited create(op);
  918. init(_size);
  919. ops:=1;
  920. loadref(0,_op1);
  921. end;
  922. constructor taicpu.op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  923. begin
  924. inherited create(op);
  925. init(_size);
  926. ops:=2;
  927. loadreg(0,_op1);
  928. loadreg(1,_op2);
  929. end;
  930. constructor taicpu.op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aint);
  931. begin
  932. inherited create(op);
  933. init(_size);
  934. ops:=2;
  935. loadreg(0,_op1);
  936. loadconst(1,_op2);
  937. end;
  938. constructor taicpu.op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  939. begin
  940. inherited create(op);
  941. init(_size);
  942. ops:=2;
  943. loadreg(0,_op1);
  944. loadref(1,_op2);
  945. end;
  946. constructor taicpu.op_const_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister);
  947. begin
  948. inherited create(op);
  949. init(_size);
  950. ops:=2;
  951. loadconst(0,_op1);
  952. loadreg(1,_op2);
  953. end;
  954. constructor taicpu.op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aint);
  955. begin
  956. inherited create(op);
  957. init(_size);
  958. ops:=2;
  959. loadconst(0,_op1);
  960. loadconst(1,_op2);
  961. end;
  962. constructor taicpu.op_const_ref(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference);
  963. begin
  964. inherited create(op);
  965. init(_size);
  966. ops:=2;
  967. loadconst(0,_op1);
  968. loadref(1,_op2);
  969. end;
  970. constructor taicpu.op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  971. begin
  972. inherited create(op);
  973. init(_size);
  974. ops:=2;
  975. loadref(0,_op1);
  976. loadreg(1,_op2);
  977. end;
  978. constructor taicpu.op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  979. begin
  980. inherited create(op);
  981. init(_size);
  982. ops:=3;
  983. loadreg(0,_op1);
  984. loadreg(1,_op2);
  985. loadreg(2,_op3);
  986. end;
  987. constructor taicpu.op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;_op3 : tregister);
  988. begin
  989. inherited create(op);
  990. init(_size);
  991. ops:=3;
  992. loadconst(0,_op1);
  993. loadreg(1,_op2);
  994. loadreg(2,_op3);
  995. end;
  996. constructor taicpu.op_ref_reg_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2,_op3 : tregister);
  997. begin
  998. inherited create(op);
  999. init(_size);
  1000. ops:=3;
  1001. loadref(0,_op1);
  1002. loadreg(1,_op2);
  1003. loadreg(2,_op3);
  1004. end;
  1005. constructor taicpu.op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference;_op3 : tregister);
  1006. begin
  1007. inherited create(op);
  1008. init(_size);
  1009. ops:=3;
  1010. loadconst(0,_op1);
  1011. loadref(1,_op2);
  1012. loadreg(2,_op3);
  1013. end;
  1014. constructor taicpu.op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;const _op3 : treference);
  1015. begin
  1016. inherited create(op);
  1017. init(_size);
  1018. ops:=3;
  1019. loadconst(0,_op1);
  1020. loadreg(1,_op2);
  1021. loadref(2,_op3);
  1022. end;
  1023. constructor taicpu.op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister;const _op3 : treference);
  1024. begin
  1025. inherited create(op);
  1026. init(_size);
  1027. ops:=3;
  1028. loadreg(0,_op1);
  1029. loadreg(1,_op2);
  1030. loadref(2,_op3);
  1031. end;
  1032. constructor taicpu.op_const_reg_reg_reg(op : tasmop; _size : topsize; _op1 : aint; _op2, _op3, _op4 : tregister);
  1033. begin
  1034. inherited create(op);
  1035. init(_size);
  1036. ops:=4;
  1037. loadconst(0,_op1);
  1038. loadreg(1,_op2);
  1039. loadreg(2,_op3);
  1040. loadreg(3,_op4);
  1041. end;
  1042. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  1043. begin
  1044. inherited create(op);
  1045. init(_size);
  1046. condition:=cond;
  1047. ops:=1;
  1048. loadsymbol(0,_op1,0);
  1049. end;
  1050. constructor taicpu.op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  1051. begin
  1052. inherited create(op);
  1053. init(_size);
  1054. ops:=1;
  1055. loadsymbol(0,_op1,0);
  1056. end;
  1057. constructor taicpu.op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  1058. begin
  1059. inherited create(op);
  1060. init(_size);
  1061. ops:=1;
  1062. loadsymbol(0,_op1,_op1ofs);
  1063. end;
  1064. constructor taicpu.op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  1065. begin
  1066. inherited create(op);
  1067. init(_size);
  1068. ops:=2;
  1069. loadsymbol(0,_op1,_op1ofs);
  1070. loadreg(1,_op2);
  1071. end;
  1072. constructor taicpu.op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  1073. begin
  1074. inherited create(op);
  1075. init(_size);
  1076. ops:=2;
  1077. loadsymbol(0,_op1,_op1ofs);
  1078. loadref(1,_op2);
  1079. end;
  1080. function taicpu.GetString:string;
  1081. var
  1082. i : longint;
  1083. s : string;
  1084. regnr: string;
  1085. addsize : boolean;
  1086. begin
  1087. s:='['+std_op2str[opcode];
  1088. for i:=0 to ops-1 do
  1089. begin
  1090. with oper[i]^ do
  1091. begin
  1092. if i=0 then
  1093. s:=s+' '
  1094. else
  1095. s:=s+',';
  1096. { type }
  1097. addsize:=false;
  1098. regnr := '';
  1099. if getregtype(reg) = R_MMREGISTER then
  1100. str(getsupreg(reg),regnr);
  1101. if (ot and OT_XMMREG)=OT_XMMREG then
  1102. s:=s+'xmmreg' + regnr
  1103. else
  1104. if (ot and OT_YMMREG)=OT_YMMREG then
  1105. s:=s+'ymmreg' + regnr
  1106. else
  1107. if (ot and OT_ZMMREG)=OT_ZMMREG then
  1108. s:=s+'zmmreg' + regnr
  1109. else
  1110. if (ot and OT_REG_EXTRA_MASK)=OT_MMXREG then
  1111. s:=s+'mmxreg'
  1112. else
  1113. if (ot and OT_REG_EXTRA_MASK)=OT_FPUREG then
  1114. s:=s+'fpureg'
  1115. else
  1116. if (ot and OT_REGISTER)=OT_REGISTER then
  1117. begin
  1118. s:=s+'reg';
  1119. addsize:=true;
  1120. end
  1121. else
  1122. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  1123. begin
  1124. s:=s+'imm';
  1125. addsize:=true;
  1126. end
  1127. else
  1128. if (ot and OT_MEMORY)=OT_MEMORY then
  1129. begin
  1130. s:=s+'mem';
  1131. addsize:=true;
  1132. end
  1133. else
  1134. s:=s+'???';
  1135. { size }
  1136. if addsize then
  1137. begin
  1138. if (ot and OT_BITS8)<>0 then
  1139. s:=s+'8'
  1140. else
  1141. if (ot and OT_BITS16)<>0 then
  1142. s:=s+'16'
  1143. else
  1144. if (ot and OT_BITS32)<>0 then
  1145. s:=s+'32'
  1146. else
  1147. if (ot and OT_BITS64)<>0 then
  1148. s:=s+'64'
  1149. else
  1150. if (ot and OT_BITS128)<>0 then
  1151. s:=s+'128'
  1152. else
  1153. if (ot and OT_BITS256)<>0 then
  1154. s:=s+'256'
  1155. else
  1156. if (ot and OT_BITS512)<>0 then
  1157. s:=s+'512'
  1158. else
  1159. s:=s+'??';
  1160. { signed }
  1161. if (ot and OT_SIGNED)<>0 then
  1162. s:=s+'s';
  1163. end;
  1164. if vopext <> 0 then
  1165. begin
  1166. str(vopext and $07, regnr);
  1167. if vopext and OTVE_VECTOR_WRITEMASK = OTVE_VECTOR_WRITEMASK then
  1168. s := s + ' {k' + regnr + '}';
  1169. if vopext and OTVE_VECTOR_ZERO = OTVE_VECTOR_ZERO then
  1170. s := s + ' {z}';
  1171. if vopext and OTVE_VECTOR_SAE = OTVE_VECTOR_SAE then
  1172. s := s + ' {sae}';
  1173. if vopext and OTVE_VECTOR_BCST = OTVE_VECTOR_BCST then
  1174. case vopext and OTVE_VECTOR_BCST_MASK of
  1175. OTVE_VECTOR_BCST2: s := s + ' {1to2}';
  1176. OTVE_VECTOR_BCST4: s := s + ' {1to4}';
  1177. OTVE_VECTOR_BCST8: s := s + ' {1to8}';
  1178. OTVE_VECTOR_BCST16: s := s + ' {1to16}';
  1179. end;
  1180. if vopext and OTVE_VECTOR_ER = OTVE_VECTOR_ER then
  1181. case vopext and OTVE_VECTOR_ER_MASK of
  1182. OTVE_VECTOR_RNSAE: s := s + ' {rn-sae}';
  1183. OTVE_VECTOR_RDSAE: s := s + ' {rd-sae}';
  1184. OTVE_VECTOR_RUSAE: s := s + ' {ru-sae}';
  1185. OTVE_VECTOR_RZSAE: s := s + ' {rz-sae}';
  1186. end;
  1187. end;
  1188. end;
  1189. end;
  1190. GetString:=s+']';
  1191. end;
  1192. procedure taicpu.Swapoperands;
  1193. var
  1194. p : POper;
  1195. begin
  1196. { Fix the operands which are in AT&T style and we need them in Intel style }
  1197. case ops of
  1198. 0,1:
  1199. ;
  1200. 2 : begin
  1201. { 0,1 -> 1,0 }
  1202. p:=oper[0];
  1203. oper[0]:=oper[1];
  1204. oper[1]:=p;
  1205. end;
  1206. 3 : begin
  1207. { 0,1,2 -> 2,1,0 }
  1208. p:=oper[0];
  1209. oper[0]:=oper[2];
  1210. oper[2]:=p;
  1211. end;
  1212. 4 : begin
  1213. { 0,1,2,3 -> 3,2,1,0 }
  1214. p:=oper[0];
  1215. oper[0]:=oper[3];
  1216. oper[3]:=p;
  1217. p:=oper[1];
  1218. oper[1]:=oper[2];
  1219. oper[2]:=p;
  1220. end;
  1221. else
  1222. internalerror(201108141);
  1223. end;
  1224. end;
  1225. procedure taicpu.SetOperandOrder(order:TOperandOrder);
  1226. begin
  1227. if FOperandOrder<>order then
  1228. begin
  1229. Swapoperands;
  1230. FOperandOrder:=order;
  1231. end;
  1232. end;
  1233. function taicpu.FixNonCommutativeOpcodes: tasmop;
  1234. begin
  1235. result:=opcode;
  1236. { we need ATT order }
  1237. SetOperandOrder(op_att);
  1238. if (
  1239. (ops=2) and
  1240. (oper[0]^.typ=top_reg) and
  1241. (oper[1]^.typ=top_reg) and
  1242. { if the first is ST and the second is also a register
  1243. it is necessarily ST1 .. ST7 }
  1244. ((oper[0]^.reg=NR_ST) or
  1245. (oper[0]^.reg=NR_ST0))
  1246. ) or
  1247. { ((ops=1) and
  1248. (oper[0]^.typ=top_reg) and
  1249. (oper[0]^.reg in [R_ST1..R_ST7])) or}
  1250. (ops=0) then
  1251. begin
  1252. if opcode=A_FSUBR then
  1253. result:=A_FSUB
  1254. else if opcode=A_FSUB then
  1255. result:=A_FSUBR
  1256. else if opcode=A_FDIVR then
  1257. result:=A_FDIV
  1258. else if opcode=A_FDIV then
  1259. result:=A_FDIVR
  1260. else if opcode=A_FSUBRP then
  1261. result:=A_FSUBP
  1262. else if opcode=A_FSUBP then
  1263. result:=A_FSUBRP
  1264. else if opcode=A_FDIVRP then
  1265. result:=A_FDIVP
  1266. else if opcode=A_FDIVP then
  1267. result:=A_FDIVRP;
  1268. end;
  1269. if (
  1270. (ops=1) and
  1271. (oper[0]^.typ=top_reg) and
  1272. (getregtype(oper[0]^.reg)=R_FPUREGISTER) and
  1273. (oper[0]^.reg<>NR_ST)
  1274. ) then
  1275. begin
  1276. if opcode=A_FSUBRP then
  1277. result:=A_FSUBP
  1278. else if opcode=A_FSUBP then
  1279. result:=A_FSUBRP
  1280. else if opcode=A_FDIVRP then
  1281. result:=A_FDIVP
  1282. else if opcode=A_FDIVP then
  1283. result:=A_FDIVRP;
  1284. end;
  1285. end;
  1286. {*****************************************************************************
  1287. Assembler
  1288. *****************************************************************************}
  1289. type
  1290. ea = packed record
  1291. sib_present : boolean;
  1292. bytes : byte;
  1293. size : byte;
  1294. modrm : byte;
  1295. sib : byte;
  1296. {$ifdef x86_64}
  1297. rex : byte;
  1298. {$endif x86_64}
  1299. end;
  1300. procedure taicpu.create_ot(objdata:TObjData);
  1301. {
  1302. this function will also fix some other fields which only needs to be once
  1303. }
  1304. var
  1305. i,l,relsize : longint;
  1306. currsym : TObjSymbol;
  1307. begin
  1308. if ops=0 then
  1309. exit;
  1310. { update oper[].ot field }
  1311. for i:=0 to ops-1 do
  1312. with oper[i]^ do
  1313. begin
  1314. case typ of
  1315. top_reg :
  1316. begin
  1317. ot:=reg_ot_table[findreg_by_number(reg)];
  1318. end;
  1319. top_ref :
  1320. begin
  1321. if (ref^.refaddr in [addr_no{$ifdef x86_64},addr_tpoff{$endif x86_64}{$ifdef i386},addr_ntpoff{$endif i386}])
  1322. {$ifdef i386}
  1323. or (
  1324. (ref^.refaddr in [addr_pic,addr_tlsgd]) and
  1325. ((ref^.base<>NR_NO) or (ref^.index<>NR_NO))
  1326. )
  1327. {$endif i386}
  1328. {$ifdef x86_64}
  1329. or (
  1330. (ref^.refaddr in [addr_pic,addr_pic_no_got,addr_tlsgd]) and
  1331. (ref^.base<>NR_NO)
  1332. )
  1333. {$endif x86_64}
  1334. then
  1335. begin
  1336. { create ot field }
  1337. if (reg_ot_table[findreg_by_number(ref^.base)] and OT_REG_GPR = OT_REG_GPR) and
  1338. ((reg_ot_table[findreg_by_number(ref^.index)] = OT_XMMREG) or
  1339. (reg_ot_table[findreg_by_number(ref^.index)] = OT_YMMREG) or
  1340. (reg_ot_table[findreg_by_number(ref^.index)] = OT_ZMMREG)
  1341. ) then
  1342. // AVX2 - vector-memory-referenz (e.g. vgatherdpd xmm0, [rax xmm1], xmm2)
  1343. ot := (reg_ot_table[findreg_by_number(ref^.base)] and OT_REG_GPR) or
  1344. (reg_ot_table[findreg_by_number(ref^.index)])
  1345. else if (ref^.base = NR_NO) and
  1346. ((reg_ot_table[findreg_by_number(ref^.index)] = OT_XMMREG) or
  1347. (reg_ot_table[findreg_by_number(ref^.index)] = OT_YMMREG) or
  1348. (reg_ot_table[findreg_by_number(ref^.index)] = OT_ZMMREG)
  1349. ) then
  1350. // AVX2 - vector-memory-referenz without base-register (e.g. vgatherdpd xmm0, [xmm1], xmm2)
  1351. ot := (OT_REG_GPR) or
  1352. (reg_ot_table[findreg_by_number(ref^.index)])
  1353. else if (ot and OT_SIZE_MASK)=0 then
  1354. ot:=OT_MEMORY_ANY or opsize_2_type[i,opsize]
  1355. else
  1356. ot:=OT_MEMORY_ANY or (ot and OT_SIZE_MASK);
  1357. if (ref^.base=NR_NO) and (ref^.index=NR_NO) then
  1358. ot:=ot or OT_MEM_OFFS;
  1359. { fix scalefactor }
  1360. if (ref^.index=NR_NO) then
  1361. ref^.scalefactor:=0
  1362. else
  1363. if (ref^.scalefactor=0) then
  1364. ref^.scalefactor:=1;
  1365. end
  1366. else
  1367. begin
  1368. { Jumps use a relative offset which can be 8bit,
  1369. for other opcodes we always need to generate the full
  1370. 32bit address }
  1371. if assigned(objdata) and
  1372. is_jmp then
  1373. begin
  1374. currsym:=objdata.symbolref(ref^.symbol);
  1375. l:=ref^.offset;
  1376. {$push}
  1377. {$r-,q-} { disable also overflow as address returns a qword for x86_64 }
  1378. if assigned(currsym) then
  1379. inc(l,currsym.address);
  1380. {$pop}
  1381. { when it is a forward jump we need to compensate the
  1382. offset of the instruction since the previous time,
  1383. because the symbol address is then still using the
  1384. 'old-style' addressing.
  1385. For backwards jumps this is not required because the
  1386. address of the symbol is already adjusted to the
  1387. new offset }
  1388. if (l>InsOffset) and (LastInsOffset<>-1) then
  1389. inc(l,InsOffset-LastInsOffset);
  1390. { instruction size will then always become 2 (PFV) }
  1391. relsize:=(InsOffset+2)-l;
  1392. if (relsize>=-128) and (relsize<=127) and
  1393. (
  1394. not assigned(currsym) or
  1395. (currsym.objsection=objdata.currobjsec)
  1396. ) then
  1397. ot:=OT_IMM8 or OT_SHORT
  1398. else
  1399. {$ifdef i8086}
  1400. ot:=OT_IMM16 or OT_NEAR;
  1401. {$else i8086}
  1402. ot:=OT_IMM32 or OT_NEAR;
  1403. {$endif i8086}
  1404. end
  1405. else
  1406. {$ifdef i8086}
  1407. if opsize=S_FAR then
  1408. ot:=OT_IMM16 or OT_FAR
  1409. else
  1410. ot:=OT_IMM16 or OT_NEAR;
  1411. {$else i8086}
  1412. ot:=OT_IMM32 or OT_NEAR;
  1413. {$endif i8086}
  1414. end;
  1415. end;
  1416. top_local :
  1417. begin
  1418. if (ot and OT_SIZE_MASK)=0 then
  1419. ot:=OT_MEMORY or opsize_2_type[i,opsize]
  1420. else
  1421. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  1422. end;
  1423. top_const :
  1424. begin
  1425. // if opcode is a SSE or AVX-instruction then we need a
  1426. // special handling (opsize can different from const-size)
  1427. // (e.g. "pextrw reg/m16, xmmreg, imm8" =>> opsize (16 bit), const-size (8 bit)
  1428. if (InsTabMemRefSizeInfoCache^[opcode].ExistsSSEAVX) and
  1429. (not(InsTabMemRefSizeInfoCache^[opcode].ConstSize in [csiMultiple, csiUnknown])) then
  1430. begin
  1431. case InsTabMemRefSizeInfoCache^[opcode].ConstSize of
  1432. csiNoSize: ot := ot and OT_NON_SIZE or OT_IMMEDIATE;
  1433. csiMem8: ot := ot and OT_NON_SIZE or OT_IMMEDIATE or OT_BITS8;
  1434. csiMem16: ot := ot and OT_NON_SIZE or OT_IMMEDIATE or OT_BITS16;
  1435. csiMem32: ot := ot and OT_NON_SIZE or OT_IMMEDIATE or OT_BITS32;
  1436. csiMem64: ot := ot and OT_NON_SIZE or OT_IMMEDIATE or OT_BITS64;
  1437. else
  1438. ;
  1439. end;
  1440. end
  1441. else
  1442. begin
  1443. { allow 2nd, 3rd or 4th operand being a constant and expect no size for shuf* etc. }
  1444. { further, allow AAD and AAM with imm. operand }
  1445. if (opsize=S_NO) and not((i in [1,2,3])
  1446. {$ifndef x86_64}
  1447. or ((i=0) and (opcode in [A_AAD,A_AAM]))
  1448. {$endif x86_64}
  1449. ) then
  1450. message(asmr_e_invalid_opcode_and_operand);
  1451. if
  1452. {$ifdef i8086}
  1453. (longint(val)>=-128) and (val<=127) then
  1454. {$else i8086}
  1455. (opsize<>S_W) and
  1456. (aint(val)>=-128) and (val<=127) then
  1457. {$endif not i8086}
  1458. ot:=OT_IMM8 or OT_SIGNED
  1459. else
  1460. ot:=OT_IMMEDIATE or opsize_2_type[i,opsize];
  1461. if (val=1) and (i=1) then
  1462. ot := ot or OT_ONENESS;
  1463. end;
  1464. end;
  1465. top_none :
  1466. begin
  1467. { generated when there was an error in the
  1468. assembler reader. It never happends when generating
  1469. assembler }
  1470. end;
  1471. else
  1472. internalerror(200402266);
  1473. end;
  1474. end;
  1475. end;
  1476. function taicpu.InsEnd:longint;
  1477. begin
  1478. InsEnd:=InsOffset+InsSize;
  1479. end;
  1480. function taicpu.Matches(p:PInsEntry):boolean;
  1481. { * IF_SM stands for Size Match: any operand whose size is not
  1482. * explicitly specified by the template is `really' intended to be
  1483. * the same size as the first size-specified operand.
  1484. * Non-specification is tolerated in the input instruction, but
  1485. * _wrong_ specification is not.
  1486. *
  1487. * IF_SM2 invokes Size Match on only the first _two_ operands, for
  1488. * three-operand instructions such as SHLD: it implies that the
  1489. * first two operands must match in size, but that the third is
  1490. * required to be _unspecified_.
  1491. *
  1492. * IF_SB invokes Size Byte: operands with unspecified size in the
  1493. * template are really bytes, and so no non-byte specification in
  1494. * the input instruction will be tolerated. IF_SW similarly invokes
  1495. * Size Word, and IF_SD invokes Size Doubleword.
  1496. *
  1497. * (The default state if neither IF_SM nor IF_SM2 is specified is
  1498. * that any operand with unspecified size in the template is
  1499. * required to have unspecified size in the instruction too...)
  1500. }
  1501. var
  1502. insot,
  1503. currot: int64;
  1504. i,j,asize,oprs : longint;
  1505. insflags:tinsflags;
  1506. vopext: int64;
  1507. siz : array[0..max_operands-1] of longint;
  1508. begin
  1509. result:=false;
  1510. { Check the opcode and operands }
  1511. if (p^.opcode<>opcode) or (p^.ops<>ops) then
  1512. exit;
  1513. {$ifdef i8086}
  1514. { On i8086, we need to skip the i386+ version of Jcc near, if the target
  1515. cpu is earlier than 386. There's another entry, later in the table for
  1516. i8086, which simulates it with i8086 instructions:
  1517. JNcc short +3
  1518. JMP near target }
  1519. if (p^.opcode=A_Jcc) and (current_settings.cputype<cpu_386) and
  1520. (IF_386 in p^.flags) then
  1521. exit;
  1522. {$endif i8086}
  1523. for i:=0 to p^.ops-1 do
  1524. begin
  1525. insot:=p^.optypes[i];
  1526. currot:=oper[i]^.ot;
  1527. { Check the operand flags }
  1528. if (insot and (not currot) and OT_NON_SIZE)<>0 then
  1529. exit;
  1530. // IGNORE VECTOR-MEMORY-SIZE
  1531. if insot and OT_TYPE_MASK = OT_MEMORY then
  1532. insot := insot and not(int64(OT_BITS128 or OT_BITS256 or OT_BITS512));
  1533. { Check if the passed operand size matches with one of
  1534. the supported operand sizes }
  1535. if ((insot and OT_SIZE_MASK)<>0) and
  1536. ((insot and currot and OT_SIZE_MASK)<>(currot and OT_SIZE_MASK)) then
  1537. exit;
  1538. { "far" matches only with "far" }
  1539. if (insot and OT_FAR)<>(currot and OT_FAR) then
  1540. exit;
  1541. end;
  1542. { Check operand sizes }
  1543. insflags:=p^.flags;
  1544. if (insflags*IF_SMASK)<>[] then
  1545. begin
  1546. { as default an untyped size can get all the sizes, this is different
  1547. from nasm, but else we need to do a lot checking which opcodes want
  1548. size or not with the automatic size generation }
  1549. asize:=-1;
  1550. if IF_SB in insflags then
  1551. asize:=OT_BITS8
  1552. else if IF_SW in insflags then
  1553. asize:=OT_BITS16
  1554. else if IF_SD in insflags then
  1555. asize:=OT_BITS32;
  1556. if insflags*IF_ARMASK<>[] then
  1557. begin
  1558. siz[0]:=-1;
  1559. siz[1]:=-1;
  1560. siz[2]:=-1;
  1561. if IF_AR0 in insflags then
  1562. siz[0]:=asize
  1563. else if IF_AR1 in insflags then
  1564. siz[1]:=asize
  1565. else if IF_AR2 in insflags then
  1566. siz[2]:=asize
  1567. else
  1568. internalerror(2017092101);
  1569. end
  1570. else
  1571. begin
  1572. siz[0]:=asize;
  1573. siz[1]:=asize;
  1574. siz[2]:=asize;
  1575. end;
  1576. if insflags*[IF_SM,IF_SM2]<>[] then
  1577. begin
  1578. if IF_SM2 in insflags then
  1579. oprs:=2
  1580. else
  1581. oprs:=p^.ops;
  1582. for i:=0 to oprs-1 do
  1583. if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
  1584. begin
  1585. for j:=0 to oprs-1 do
  1586. siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
  1587. break;
  1588. end;
  1589. end
  1590. else
  1591. oprs:=2;
  1592. { Check operand sizes }
  1593. for i:=0 to p^.ops-1 do
  1594. begin
  1595. insot:=p^.optypes[i];
  1596. currot:=oper[i]^.ot;
  1597. if ((insot and OT_SIZE_MASK)=0) and
  1598. ((currot and OT_SIZE_MASK and (not siz[i]))<>0) and
  1599. { Immediates can always include smaller size }
  1600. ((currot and OT_IMMEDIATE)=0) and
  1601. (((insot and OT_SIZE_MASK) or siz[i])<(currot and OT_SIZE_MASK)) then
  1602. exit;
  1603. if (insot and OT_FAR)<>(currot and OT_FAR) then
  1604. exit;
  1605. end;
  1606. end;
  1607. if (InsTabMemRefSizeInfoCache^[opcode].MemRefSize in MemRefMultiples) and
  1608. (InsTabMemRefSizeInfoCache^[opcode].ExistsSSEAVX) then
  1609. begin
  1610. for i:=0 to p^.ops-1 do
  1611. begin
  1612. insot:=p^.optypes[i];
  1613. currot:=oper[i]^.ot;
  1614. { Check the operand flags }
  1615. if (insot and (not currot) and OT_NON_SIZE)<>0 then
  1616. exit;
  1617. { Check if the passed operand size matches with one of
  1618. the supported operand sizes }
  1619. if ((insot and OT_SIZE_MASK)<>0) and
  1620. ((insot and currot and OT_SIZE_MASK)<>(currot and OT_SIZE_MASK)) then
  1621. exit;
  1622. end;
  1623. end;
  1624. if (InsTabMemRefSizeInfoCache^[opcode].ExistsSSEAVX) then
  1625. begin
  1626. for i:=0 to p^.ops-1 do
  1627. begin
  1628. // check vectoroperand-extention e.g. {k1} {z}
  1629. vopext := 0;
  1630. if (oper[i]^.vopext and OTVE_VECTOR_WRITEMASK) = OTVE_VECTOR_WRITEMASK then
  1631. begin
  1632. vopext := vopext or OT_VECTORMASK;
  1633. if (oper[i]^.vopext and OTVE_VECTOR_ZERO) = OTVE_VECTOR_ZERO then
  1634. vopext := vopext or OT_VECTORZERO;
  1635. end;
  1636. if (oper[i]^.vopext and OTVE_VECTOR_BCST) = OTVE_VECTOR_BCST then
  1637. begin
  1638. vopext := vopext or OT_VECTORBCST;
  1639. if (InsTabMemRefSizeInfoCache^[opcode].BCSTTypes <> []) then
  1640. begin
  1641. // any opcodes needs a special handling
  1642. // default broadcast calculation is
  1643. // bmem32
  1644. // xmmreg: {1to4}
  1645. // ymmreg: {1to8}
  1646. // zmmreg: {1to16}
  1647. // bmem64
  1648. // xmmreg: {1to2}
  1649. // ymmreg: {1to4}
  1650. // zmmreg: {1to8}
  1651. // in any opcodes not exists a mmregister
  1652. // e.g. vfpclasspd k1, [RAX] {1to8}, 0
  1653. // =>> check flags
  1654. case oper[i]^.vopext and (OTVE_VECTOR_BCST2 or OTVE_VECTOR_BCST4 or OTVE_VECTOR_BCST8 or OTVE_VECTOR_BCST16) of
  1655. OTVE_VECTOR_BCST2: if not(IF_BCST2 in p^.flags) then exit;
  1656. OTVE_VECTOR_BCST4: if not(IF_BCST4 in p^.flags) then exit;
  1657. OTVE_VECTOR_BCST8: if not(IF_BCST8 in p^.flags) then exit;
  1658. OTVE_VECTOR_BCST16: if not(IF_BCST16 in p^.flags) then exit;
  1659. else exit;
  1660. end;
  1661. end;
  1662. end;
  1663. if (oper[i]^.vopext and OTVE_VECTOR_ER) = OTVE_VECTOR_ER then
  1664. vopext := vopext or OT_VECTORER;
  1665. if (oper[i]^.vopext and OTVE_VECTOR_SAE) = OTVE_VECTOR_SAE then
  1666. vopext := vopext or OT_VECTORSAE;
  1667. if p^.optypes[i] and vopext <> vopext then
  1668. exit;
  1669. end;
  1670. end;
  1671. result:=true;
  1672. end;
  1673. procedure taicpu.ResetPass1;
  1674. begin
  1675. { we need to reset everything here, because the choosen insentry
  1676. can be invalid for a new situation where the previously optimized
  1677. insentry is not correct }
  1678. InsEntry:=nil;
  1679. InsSize:=0;
  1680. LastInsOffset:=-1;
  1681. end;
  1682. procedure taicpu.ResetPass2;
  1683. begin
  1684. { we are here in a second pass, check if the instruction can be optimized }
  1685. if assigned(InsEntry) and
  1686. (IF_PASS2 in InsEntry^.flags) then
  1687. begin
  1688. InsEntry:=nil;
  1689. InsSize:=0;
  1690. end;
  1691. LastInsOffset:=-1;
  1692. end;
  1693. function taicpu.CheckIfValid:boolean;
  1694. begin
  1695. result:=FindInsEntry(nil);
  1696. end;
  1697. function taicpu.FindInsentry(objdata:TObjData):boolean;
  1698. var
  1699. i : longint;
  1700. begin
  1701. result:=false;
  1702. { Things which may only be done once, not when a second pass is done to
  1703. optimize }
  1704. if (Insentry=nil) or (IF_PASS2 in InsEntry^.flags) then
  1705. begin
  1706. current_filepos:=fileinfo;
  1707. { We need intel style operands }
  1708. SetOperandOrder(op_intel);
  1709. { create the .ot fields }
  1710. create_ot(objdata);
  1711. { set the file postion }
  1712. end
  1713. else
  1714. begin
  1715. { we've already an insentry so it's valid }
  1716. result:=true;
  1717. exit;
  1718. end;
  1719. { Lookup opcode in the table }
  1720. InsSize:=-1;
  1721. i:=instabcache^[opcode];
  1722. if i=-1 then
  1723. begin
  1724. Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
  1725. exit;
  1726. end;
  1727. insentry:=@instab[i];
  1728. while (insentry^.opcode=opcode) do
  1729. begin
  1730. if matches(insentry) then
  1731. begin
  1732. result:=true;
  1733. exit;
  1734. end;
  1735. inc(insentry);
  1736. end;
  1737. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1738. { No instruction found, set insentry to nil and inssize to -1 }
  1739. insentry:=nil;
  1740. inssize:=-1;
  1741. end;
  1742. function taicpu.CheckUseEVEX: boolean;
  1743. var
  1744. i: integer;
  1745. begin
  1746. result := false;
  1747. for i := 0 to ops - 1 do
  1748. begin
  1749. if (oper[i]^.typ=top_reg) and
  1750. (getregtype(oper[i]^.reg) = R_MMREGISTER) then
  1751. if getsupreg(oper[i]^.reg)>=16 then
  1752. result := true;
  1753. if (oper[i]^.vopext and OTVE_VECTOR_MASK) <> 0 then
  1754. result := true;
  1755. end;
  1756. end;
  1757. procedure taicpu.CheckEVEXTuple(const aInput:toper; aInsEntry: pInsentry; aIsVector128, aIsVector256, aIsVector512, aIsEVEXW1: boolean);
  1758. var
  1759. i: integer;
  1760. tuplesize: integer;
  1761. memsize: integer;
  1762. begin
  1763. if EVEXTupleState = etsUnknown then
  1764. begin
  1765. EVEXTupleState := etsNotTuple;
  1766. if aInsEntry^.Flags * IF_TUPLEMASK <> [] then
  1767. begin
  1768. tuplesize := 0;
  1769. if IF_TFV in aInsEntry^.Flags then
  1770. begin
  1771. for i := 0 to aInsEntry^.ops - 1 do
  1772. if (aInsEntry^.optypes[i] and OT_BMEM32 = OT_BMEM32) then
  1773. begin
  1774. tuplesize := 4;
  1775. break;
  1776. end
  1777. else if (aInsEntry^.optypes[i] and OT_BMEM64 = OT_BMEM64) then
  1778. begin
  1779. tuplesize := 8;
  1780. break;
  1781. end
  1782. else if (aInsEntry^.optypes[i] and OT_MEMORY = OT_MEMORY) then
  1783. begin
  1784. if aIsVector512 then tuplesize := 64
  1785. else if aIsVector256 then tuplesize := 32
  1786. else tuplesize := 16;
  1787. break;
  1788. end
  1789. else if (aInsEntry^.optypes[i] and OT_REGNORM = OT_REGMEM) then
  1790. begin
  1791. if aIsVector512 then tuplesize := 64
  1792. else if aIsVector256 then tuplesize := 32
  1793. else tuplesize := 16;
  1794. break;
  1795. end;
  1796. end
  1797. else if IF_THV in aInsEntry^.Flags then
  1798. begin
  1799. for i := 0 to aInsEntry^.ops - 1 do
  1800. if (aInsEntry^.optypes[i] and OT_BMEM32 = OT_BMEM32) then
  1801. begin
  1802. tuplesize := 4;
  1803. break;
  1804. end
  1805. else if (aInsEntry^.optypes[i] and OT_REGNORM = OT_REGMEM) then
  1806. begin
  1807. if aIsVector512 then tuplesize := 32
  1808. else if aIsVector256 then tuplesize := 16
  1809. else tuplesize := 8;
  1810. break;
  1811. end
  1812. end
  1813. else if IF_TFVM in aInsEntry^.Flags then
  1814. begin
  1815. if aIsVector512 then tuplesize := 64
  1816. else if aIsVector256 then tuplesize := 32
  1817. else tuplesize := 16;
  1818. end
  1819. else
  1820. begin
  1821. memsize := 0;
  1822. for i := 0 to aInsEntry^.ops - 1 do
  1823. begin
  1824. if aInsEntry^.optypes[i] and (OT_REGNORM or OT_MEMORY) = OT_REGMEM then
  1825. begin
  1826. case aInsEntry^.optypes[i] and (OT_BITS32 or OT_BITS64) of
  1827. OT_BITS32: begin
  1828. memsize := 32;
  1829. break;
  1830. end;
  1831. OT_BITS64: begin
  1832. memsize := 64;
  1833. break;
  1834. end;
  1835. end;
  1836. end
  1837. else
  1838. case aInsEntry^.optypes[i] and (OT_MEM8 or OT_MEM16 or OT_MEM32 or OT_MEM64) of
  1839. OT_MEM8: begin
  1840. memsize := 8;
  1841. break;
  1842. end;
  1843. OT_MEM16: begin
  1844. memsize := 16;
  1845. break;
  1846. end;
  1847. OT_MEM32: begin
  1848. memsize := 32;
  1849. break;
  1850. end;
  1851. OT_MEM64: //if aIsEVEXW1 then
  1852. begin
  1853. memsize := 64;
  1854. break;
  1855. end;
  1856. end;
  1857. end;
  1858. if IF_T1S in aInsEntry^.Flags then
  1859. begin
  1860. case memsize of
  1861. 8: tuplesize := 1;
  1862. 16: tuplesize := 2;
  1863. else if aIsEVEXW1 then tuplesize := 8
  1864. else tuplesize := 4;
  1865. end;
  1866. end
  1867. else if IF_T1S8 in aInsEntry^.Flags then tuplesize := 1
  1868. else if IF_T1S16 in aInsEntry^.Flags then tuplesize := 2
  1869. else if IF_T1F32 in aInsEntry^.Flags then tuplesize := 4
  1870. else if IF_T1F64 in aInsEntry^.Flags then tuplesize := 8
  1871. else if IF_T2 in aInsEntry^.Flags then
  1872. begin
  1873. case aIsEVEXW1 of
  1874. false: tuplesize := 8;
  1875. else if aIsVector256 or aIsVector512 then tuplesize := 16;
  1876. end;
  1877. end
  1878. else if IF_T4 in aInsEntry^.Flags then
  1879. begin
  1880. case aIsEVEXW1 of
  1881. false: if aIsVector256 or aIsVector512 then tuplesize := 16;
  1882. else if aIsVector512 then tuplesize := 32;
  1883. end;
  1884. end
  1885. else if IF_T8 in aInsEntry^.Flags then
  1886. begin
  1887. case aIsEVEXW1 of
  1888. false: if aIsVector512 then tuplesize := 32;
  1889. else
  1890. Internalerror(2019081013);
  1891. end;
  1892. end
  1893. else if IF_THVM in aInsEntry^.Flags then
  1894. begin
  1895. tuplesize := 8; // default 128bit-vectorlength
  1896. if aIsVector256 then tuplesize := 16
  1897. else if aIsVector512 then tuplesize := 32;
  1898. end
  1899. else if IF_TQVM in aInsEntry^.Flags then
  1900. begin
  1901. tuplesize := 4; // default 128bit-vectorlength
  1902. if aIsVector256 then tuplesize := 8
  1903. else if aIsVector512 then tuplesize := 16;
  1904. end
  1905. else if IF_TOVM in aInsEntry^.Flags then
  1906. begin
  1907. tuplesize := 2; // default 128bit-vectorlength
  1908. if aIsVector256 then tuplesize := 4
  1909. else if aIsVector512 then tuplesize := 8;
  1910. end
  1911. else if IF_TMEM128 in aInsEntry^.Flags then tuplesize := 16
  1912. else if IF_TMDDUP in aInsEntry^.Flags then
  1913. begin
  1914. tuplesize := 8; // default 128bit-vectorlength
  1915. if aIsVector256 then tuplesize := 32
  1916. else if aIsVector512 then tuplesize := 64;
  1917. end;
  1918. end;
  1919. if tuplesize > 0 then
  1920. begin
  1921. if aInput.typ = top_ref then
  1922. begin
  1923. if aInput.ref^.base <> NR_NO then
  1924. begin
  1925. if (aInput.ref^.offset <> 0) and
  1926. ((aInput.ref^.offset mod tuplesize) = 0) and
  1927. (abs(aInput.ref^.offset) div tuplesize <= 127) then
  1928. begin
  1929. aInput.ref^.offset := aInput.ref^.offset div tuplesize;
  1930. EVEXTupleState := etsIsTuple;
  1931. end;
  1932. end;
  1933. end;
  1934. end;
  1935. end;
  1936. end;
  1937. end;
  1938. function taicpu.Pass1(objdata:TObjData):longint;
  1939. begin
  1940. Pass1:=0;
  1941. { Save the old offset and set the new offset }
  1942. InsOffset:=ObjData.CurrObjSec.Size;
  1943. { Error? }
  1944. if (Insentry=nil) and (InsSize=-1) then
  1945. exit;
  1946. { set the file postion }
  1947. current_filepos:=fileinfo;
  1948. { Get InsEntry }
  1949. if FindInsEntry(ObjData) then
  1950. begin
  1951. { Calculate instruction size }
  1952. InsSize:=calcsize(insentry);
  1953. if segprefix<>NR_NO then
  1954. inc(InsSize);
  1955. if NeedAddrPrefix then
  1956. inc(InsSize);
  1957. { Fix opsize if size if forced }
  1958. if insentry^.flags*[IF_SB,IF_SW,IF_SD]<>[] then
  1959. begin
  1960. if insentry^.flags*IF_ARMASK=[] then
  1961. begin
  1962. if IF_SB in insentry^.flags then
  1963. begin
  1964. if opsize=S_NO then
  1965. opsize:=S_B;
  1966. end
  1967. else if IF_SW in insentry^.flags then
  1968. begin
  1969. if opsize=S_NO then
  1970. opsize:=S_W;
  1971. end
  1972. else if IF_SD in insentry^.flags then
  1973. begin
  1974. if opsize=S_NO then
  1975. opsize:=S_L;
  1976. end;
  1977. end;
  1978. end;
  1979. LastInsOffset:=InsOffset;
  1980. Pass1:=InsSize;
  1981. exit;
  1982. end;
  1983. LastInsOffset:=-1;
  1984. end;
  1985. const
  1986. segprefixes: array[NR_ES..NR_GS] of Byte=(
  1987. // es cs ss ds fs gs
  1988. $26, $2E, $36, $3E, $64, $65
  1989. );
  1990. procedure taicpu.Pass2(objdata:TObjData);
  1991. begin
  1992. { error in pass1 ? }
  1993. if insentry=nil then
  1994. exit;
  1995. current_filepos:=fileinfo;
  1996. { Segment override }
  1997. if (segprefix>=NR_ES) and (segprefix<=NR_GS) then
  1998. begin
  1999. {$ifdef i8086}
  2000. if (objdata.CPUType<>cpu_none) and (objdata.CPUType<cpu_386) and
  2001. ((segprefix=NR_FS) or (segprefix=NR_GS)) then
  2002. Message(asmw_e_instruction_not_supported_by_cpu);
  2003. {$endif i8086}
  2004. objdata.writebytes(segprefixes[segprefix],1);
  2005. { fix the offset for GenNode }
  2006. inc(InsOffset);
  2007. end
  2008. else if segprefix<>NR_NO then
  2009. InternalError(201001071);
  2010. { Address size prefix? }
  2011. if NeedAddrPrefix then
  2012. begin
  2013. write0x67prefix(objdata);
  2014. { fix the offset for GenNode }
  2015. inc(InsOffset);
  2016. end;
  2017. { Generate the instruction }
  2018. GenCode(objdata);
  2019. end;
  2020. function is_64_bit_ref(const ref:treference):boolean;
  2021. begin
  2022. {$if defined(x86_64)}
  2023. result:=not is_32_bit_ref(ref);
  2024. {$elseif defined(i386) or defined(i8086)}
  2025. result:=false;
  2026. {$endif}
  2027. end;
  2028. function is_32_bit_ref(const ref:treference):boolean;
  2029. begin
  2030. {$if defined(x86_64)}
  2031. result:=(ref.refaddr=addr_no) and
  2032. (ref.base<>NR_RIP) and
  2033. (
  2034. ((ref.index<>NR_NO) and (getsubreg(ref.index)=R_SUBD)) or
  2035. ((ref.base<>NR_NO) and (getsubreg(ref.base)=R_SUBD))
  2036. );
  2037. {$elseif defined(i386) or defined(i8086)}
  2038. result:=not is_16_bit_ref(ref);
  2039. {$endif}
  2040. end;
  2041. function is_16_bit_ref(const ref:treference):boolean;
  2042. var
  2043. ir,br : Tregister;
  2044. isub,bsub : tsubregister;
  2045. begin
  2046. if (ref.index<>NR_NO) and (getregtype(ref.index)=R_MMREGISTER) then
  2047. exit(false);
  2048. ir:=ref.index;
  2049. br:=ref.base;
  2050. isub:=getsubreg(ir);
  2051. bsub:=getsubreg(br);
  2052. { it's a direct address }
  2053. if (br=NR_NO) and (ir=NR_NO) then
  2054. begin
  2055. {$ifdef i8086}
  2056. result:=true;
  2057. {$else i8086}
  2058. result:=false;
  2059. {$endif}
  2060. end
  2061. else
  2062. { it's an indirection }
  2063. begin
  2064. result := ((ir<>NR_NO) and (isub=R_SUBW)) or
  2065. ((br<>NR_NO) and (bsub=R_SUBW));
  2066. end;
  2067. end;
  2068. function get_ref_address_size(const ref:treference):byte;
  2069. begin
  2070. if is_64_bit_ref(ref) then
  2071. result:=64
  2072. else if is_32_bit_ref(ref) then
  2073. result:=32
  2074. else if is_16_bit_ref(ref) then
  2075. result:=16
  2076. else
  2077. internalerror(2017101601);
  2078. end;
  2079. function get_default_segment_of_ref(const ref:treference):tregister;
  2080. begin
  2081. { for 16-bit registers, we allow base and index to be swapped, that's
  2082. why we also we check whether ref.index=NR_BP. For 32-bit registers,
  2083. however, index=NR_EBP is encoded differently than base=NR_EBP and has
  2084. a different default segment. }
  2085. if (ref.base=NR_BP) or (ref.index=NR_BP) or
  2086. (ref.base=NR_EBP) or (ref.base=NR_ESP)
  2087. {$ifdef x86_64}
  2088. or (ref.base=NR_RBP) or (ref.base=NR_RSP)
  2089. {$endif x86_64}
  2090. then
  2091. result:=NR_SS
  2092. else
  2093. result:=NR_DS;
  2094. end;
  2095. procedure optimize_ref(var ref:treference; inlineasm: boolean);
  2096. var
  2097. ss_equals_ds: boolean;
  2098. tmpreg: TRegister;
  2099. begin
  2100. {$ifdef x86_64}
  2101. { x86_64 in long mode ignores all segment base, limit and access rights
  2102. checks for the DS, ES and SS registers, so we can set ss_equals_ds to
  2103. true (and thus, perform stronger optimizations on the reference),
  2104. regardless of whether this is inline asm or not (so, even if the user
  2105. is doing tricks by loading different values into DS and SS, it still
  2106. doesn't matter while the processor is in long mode) }
  2107. ss_equals_ds:=True;
  2108. {$else x86_64}
  2109. { for i8086 and i386 inline asm, we assume SS<>DS, even if we're
  2110. compiling for a memory model, where SS=DS, because the user might be
  2111. doing something tricky with the segment registers (and may have
  2112. temporarily set them differently) }
  2113. if inlineasm then
  2114. ss_equals_ds:=False
  2115. else
  2116. ss_equals_ds:=segment_regs_equal(NR_DS,NR_SS);
  2117. {$endif x86_64}
  2118. { remove redundant segment overrides }
  2119. if (ref.segment<>NR_NO) and
  2120. ((inlineasm and (ref.segment=get_default_segment_of_ref(ref))) or
  2121. ((not inlineasm) and (segment_regs_equal(ref.segment,get_default_segment_of_ref(ref))))) then
  2122. ref.segment:=NR_NO;
  2123. if not is_16_bit_ref(ref) then
  2124. begin
  2125. { Switching index to base position gives shorter assembler instructions.
  2126. Converting index*2 to base+index also gives shorter instructions. }
  2127. if (ref.base=NR_NO) and (ref.index<>NR_NO) and (ref.scalefactor<=2) and
  2128. (ss_equals_ds or (ref.segment<>NR_NO) or (ref.index<>NR_EBP))
  2129. { do not mess with tls references, they have the (,reg,1) format on purpose
  2130. else the linker cannot resolve/replace them }
  2131. {$ifdef i386} and (ref.refaddr<>addr_tlsgd) {$endif i386} then
  2132. begin
  2133. ref.base:=ref.index;
  2134. if ref.scalefactor=2 then
  2135. ref.scalefactor:=1
  2136. else
  2137. begin
  2138. ref.index:=NR_NO;
  2139. ref.scalefactor:=0;
  2140. end;
  2141. end;
  2142. { Switching rBP+reg to reg+rBP sometimes gives shorter instructions (if there's no offset)
  2143. On x86_64 this also works for switching r13+reg to reg+r13. }
  2144. if ((ref.base=NR_EBP) {$ifdef x86_64}or (ref.base=NR_RBP) or (ref.base=NR_R13) or (ref.base=NR_R13D){$endif}) and
  2145. (ref.index<>NR_NO) and
  2146. (ref.index<>NR_EBP) and {$ifdef x86_64}(ref.index<>NR_RBP) and (ref.index<>NR_R13) and (ref.index<>NR_R13D) and{$endif}
  2147. (ref.scalefactor<=1) and (ref.offset=0) and (ref.refaddr=addr_no) and
  2148. (ss_equals_ds or (ref.segment<>NR_NO)) then
  2149. begin
  2150. tmpreg:=ref.base;
  2151. ref.base:=ref.index;
  2152. ref.index:=tmpreg;
  2153. end;
  2154. end;
  2155. { remove redundant segment overrides again }
  2156. if (ref.segment<>NR_NO) and
  2157. ((inlineasm and (ref.segment=get_default_segment_of_ref(ref))) or
  2158. ((not inlineasm) and (segment_regs_equal(ref.segment,get_default_segment_of_ref(ref))))) then
  2159. ref.segment:=NR_NO;
  2160. end;
  2161. function taicpu.NeedAddrPrefix(opidx: byte): boolean;
  2162. begin
  2163. {$if defined(x86_64)}
  2164. result:=(oper[opidx]^.typ=top_ref) and is_32_bit_ref(oper[opidx]^.ref^);
  2165. {$elseif defined(i386)}
  2166. result:=(oper[opidx]^.typ=top_ref) and is_16_bit_ref(oper[opidx]^.ref^);
  2167. {$elseif defined(i8086)}
  2168. result:=(oper[opidx]^.typ=top_ref) and is_32_bit_ref(oper[opidx]^.ref^);
  2169. {$endif}
  2170. end;
  2171. function taicpu.NeedAddrPrefix:boolean;
  2172. var
  2173. i: Integer;
  2174. begin
  2175. for i:=0 to ops-1 do
  2176. if needaddrprefix(i) then
  2177. exit(true);
  2178. result:=false;
  2179. end;
  2180. procedure badreg(r:Tregister);
  2181. begin
  2182. Message1(asmw_e_invalid_register,generic_regname(r));
  2183. end;
  2184. function regval(r:Tregister):byte;
  2185. const
  2186. intsupreg2opcode: array[0..7] of byte=
  2187. // ax cx dx bx si di bp sp -- in x86reg.dat
  2188. // ax cx dx bx sp bp si di -- needed order
  2189. (0, 1, 2, 3, 6, 7, 5, 4);
  2190. maxsupreg: array[tregistertype] of tsuperregister=
  2191. {$ifdef x86_64}
  2192. (0, 16, 9, 8, 32, 32, 8, 0, 0, 0);
  2193. {$else x86_64}
  2194. (0, 8, 9, 8, 8, 32, 8, 0, 0, 0);
  2195. {$endif x86_64}
  2196. var
  2197. rs: tsuperregister;
  2198. rt: tregistertype;
  2199. begin
  2200. rs:=getsupreg(r);
  2201. rt:=getregtype(r);
  2202. if (rs>=maxsupreg[rt]) then
  2203. badreg(r);
  2204. result:=rs and 7;
  2205. if (rt=R_INTREGISTER) then
  2206. begin
  2207. if (rs<8) then
  2208. result:=intsupreg2opcode[rs];
  2209. if getsubreg(r)=R_SUBH then
  2210. inc(result,4);
  2211. end;
  2212. end;
  2213. {$if defined(x86_64)}
  2214. function rexbits(r: tregister): byte;
  2215. begin
  2216. result:=0;
  2217. case getregtype(r) of
  2218. R_INTREGISTER:
  2219. if (getsupreg(r)>=RS_R8) then
  2220. { Either B,X or R bits can be set, depending on register role in instruction.
  2221. Set all three bits here, caller will discard unnecessary ones. }
  2222. result:=result or $47
  2223. else if (getsubreg(r)=R_SUBL) and
  2224. (getsupreg(r) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
  2225. result:=result or $40
  2226. else if (getsubreg(r)=R_SUBH) then
  2227. { Not an actual REX bit, used to detect incompatible usage of
  2228. AH/BH/CH/DH }
  2229. result:=result or $80;
  2230. R_MMREGISTER:
  2231. //if getsupreg(r)>=RS_XMM8 then
  2232. // AVX512 = 32 register
  2233. // rexbit = 0 => MMRegister 0..7 or 16..23
  2234. // rexbit = 1 => MMRegister 8..15 or 24..31
  2235. if (getsupreg(r) and $08) = $08 then
  2236. result:=result or $47;
  2237. else
  2238. ;
  2239. end;
  2240. end;
  2241. function process_ea_ref_64_32(const input:toper;var output:ea;rfield:longint; uselargeoffset: boolean):boolean;
  2242. var
  2243. sym : tasmsymbol;
  2244. md,s : byte;
  2245. base,index,scalefactor,
  2246. o : longint;
  2247. ir,br : Tregister;
  2248. isub,bsub : tsubregister;
  2249. begin
  2250. result:=false;
  2251. ir:=input.ref^.index;
  2252. br:=input.ref^.base;
  2253. isub:=getsubreg(ir);
  2254. bsub:=getsubreg(br);
  2255. s:=input.ref^.scalefactor;
  2256. o:=input.ref^.offset;
  2257. sym:=input.ref^.symbol;
  2258. //if ((ir<>NR_NO) and (getregtype(ir)<>R_INTREGISTER)) or
  2259. // ((br<>NR_NO) and (br<>NR_RIP) and (getregtype(br)<>R_INTREGISTER)) then
  2260. if ((ir<>NR_NO) and (getregtype(ir)=R_MMREGISTER) and (br<>NR_NO) and (getregtype(br)<>R_INTREGISTER)) or // vector memory (AVX2)
  2261. ((ir<>NR_NO) and (getregtype(ir)<>R_INTREGISTER) and (getregtype(ir)<>R_MMREGISTER)) or
  2262. ((br<>NR_NO) and (br<>NR_RIP) and (getregtype(br)<>R_INTREGISTER)) then
  2263. internalerror(200301081);
  2264. { it's direct address }
  2265. if (br=NR_NO) and (ir=NR_NO) then
  2266. begin
  2267. output.sib_present:=true;
  2268. output.bytes:=4;
  2269. output.modrm:=4 or (rfield shl 3);
  2270. output.sib:=$25;
  2271. end
  2272. else if (br=NR_RIP) and (ir=NR_NO) then
  2273. begin
  2274. { rip based }
  2275. output.sib_present:=false;
  2276. output.bytes:=4;
  2277. output.modrm:=5 or (rfield shl 3);
  2278. end
  2279. else
  2280. { it's an indirection }
  2281. begin
  2282. if ((br=NR_RIP) and (ir<>NR_NO)) or
  2283. (ir=NR_RIP) then
  2284. message(asmw_e_illegal_use_of_rip);
  2285. if ir=NR_STACK_POINTER_REG then
  2286. Message(asmw_e_illegal_use_of_sp);
  2287. { 16 bit? }
  2288. if ((ir<>NR_NO) and (isub in [R_SUBMMX,R_SUBMMY,R_SUBMMZ]) and
  2289. (br<>NR_NO) and (bsub=R_SUBQ)
  2290. ) then
  2291. begin
  2292. // vector memory (AVX2) =>> ignore
  2293. end
  2294. else if ((ir<>NR_NO) and (isub<>R_SUBQ) and (isub<>R_SUBD)) or
  2295. ((br<>NR_NO) and (bsub<>R_SUBQ) and (bsub<>R_SUBD)) then
  2296. begin
  2297. message(asmw_e_16bit_32bit_not_supported);
  2298. end;
  2299. { wrong, for various reasons }
  2300. if (ir=NR_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (ir<>NR_NO)) then
  2301. exit;
  2302. output.rex:=output.rex or (rexbits(br) and $F1) or (rexbits(ir) and $F2);
  2303. result:=true;
  2304. { base }
  2305. case br of
  2306. NR_R8D,
  2307. NR_EAX,
  2308. NR_R8,
  2309. NR_RAX : base:=0;
  2310. NR_R9D,
  2311. NR_ECX,
  2312. NR_R9,
  2313. NR_RCX : base:=1;
  2314. NR_R10D,
  2315. NR_EDX,
  2316. NR_R10,
  2317. NR_RDX : base:=2;
  2318. NR_R11D,
  2319. NR_EBX,
  2320. NR_R11,
  2321. NR_RBX : base:=3;
  2322. NR_R12D,
  2323. NR_ESP,
  2324. NR_R12,
  2325. NR_RSP : base:=4;
  2326. NR_R13D,
  2327. NR_EBP,
  2328. NR_R13,
  2329. NR_NO,
  2330. NR_RBP : base:=5;
  2331. NR_R14D,
  2332. NR_ESI,
  2333. NR_R14,
  2334. NR_RSI : base:=6;
  2335. NR_R15D,
  2336. NR_EDI,
  2337. NR_R15,
  2338. NR_RDI : base:=7;
  2339. else
  2340. exit;
  2341. end;
  2342. { index }
  2343. case ir of
  2344. NR_R8D,
  2345. NR_EAX,
  2346. NR_R8,
  2347. NR_RAX,
  2348. NR_XMM0,
  2349. NR_XMM8,
  2350. NR_XMM16,
  2351. NR_XMM24,
  2352. NR_YMM0,
  2353. NR_YMM8,
  2354. NR_YMM16,
  2355. NR_YMM24,
  2356. NR_ZMM0,
  2357. NR_ZMM8,
  2358. NR_ZMM16,
  2359. NR_ZMM24: index:=0;
  2360. NR_R9D,
  2361. NR_ECX,
  2362. NR_R9,
  2363. NR_RCX,
  2364. NR_XMM1,
  2365. NR_XMM9,
  2366. NR_XMM17,
  2367. NR_XMM25,
  2368. NR_YMM1,
  2369. NR_YMM9,
  2370. NR_YMM17,
  2371. NR_YMM25,
  2372. NR_ZMM1,
  2373. NR_ZMM9,
  2374. NR_ZMM17,
  2375. NR_ZMM25: index:=1;
  2376. NR_R10D,
  2377. NR_EDX,
  2378. NR_R10,
  2379. NR_RDX,
  2380. NR_XMM2,
  2381. NR_XMM10,
  2382. NR_XMM18,
  2383. NR_XMM26,
  2384. NR_YMM2,
  2385. NR_YMM10,
  2386. NR_YMM18,
  2387. NR_YMM26,
  2388. NR_ZMM2,
  2389. NR_ZMM10,
  2390. NR_ZMM18,
  2391. NR_ZMM26: index:=2;
  2392. NR_R11D,
  2393. NR_EBX,
  2394. NR_R11,
  2395. NR_RBX,
  2396. NR_XMM3,
  2397. NR_XMM11,
  2398. NR_XMM19,
  2399. NR_XMM27,
  2400. NR_YMM3,
  2401. NR_YMM11,
  2402. NR_YMM19,
  2403. NR_YMM27,
  2404. NR_ZMM3,
  2405. NR_ZMM11,
  2406. NR_ZMM19,
  2407. NR_ZMM27: index:=3;
  2408. NR_R12D,
  2409. NR_ESP,
  2410. NR_R12,
  2411. NR_NO,
  2412. NR_XMM4,
  2413. NR_XMM12,
  2414. NR_XMM20,
  2415. NR_XMM28,
  2416. NR_YMM4,
  2417. NR_YMM12,
  2418. NR_YMM20,
  2419. NR_YMM28,
  2420. NR_ZMM4,
  2421. NR_ZMM12,
  2422. NR_ZMM20,
  2423. NR_ZMM28: index:=4;
  2424. NR_R13D,
  2425. NR_EBP,
  2426. NR_R13,
  2427. NR_RBP,
  2428. NR_XMM5,
  2429. NR_XMM13,
  2430. NR_XMM21,
  2431. NR_XMM29,
  2432. NR_YMM5,
  2433. NR_YMM13,
  2434. NR_YMM21,
  2435. NR_YMM29,
  2436. NR_ZMM5,
  2437. NR_ZMM13,
  2438. NR_ZMM21,
  2439. NR_ZMM29: index:=5;
  2440. NR_R14D,
  2441. NR_ESI,
  2442. NR_R14,
  2443. NR_RSI,
  2444. NR_XMM6,
  2445. NR_XMM14,
  2446. NR_XMM22,
  2447. NR_XMM30,
  2448. NR_YMM6,
  2449. NR_YMM14,
  2450. NR_YMM22,
  2451. NR_YMM30,
  2452. NR_ZMM6,
  2453. NR_ZMM14,
  2454. NR_ZMM22,
  2455. NR_ZMM30: index:=6;
  2456. NR_R15D,
  2457. NR_EDI,
  2458. NR_R15,
  2459. NR_RDI,
  2460. NR_XMM7,
  2461. NR_XMM15,
  2462. NR_XMM23,
  2463. NR_XMM31,
  2464. NR_YMM7,
  2465. NR_YMM15,
  2466. NR_YMM23,
  2467. NR_YMM31,
  2468. NR_ZMM7,
  2469. NR_ZMM15,
  2470. NR_ZMM23,
  2471. NR_ZMM31: index:=7;
  2472. else
  2473. exit;
  2474. end;
  2475. case s of
  2476. 0,
  2477. 1 : scalefactor:=0;
  2478. 2 : scalefactor:=1;
  2479. 4 : scalefactor:=2;
  2480. 8 : scalefactor:=3;
  2481. else
  2482. exit;
  2483. end;
  2484. { If rbp or r13 is used we must always include an offset }
  2485. if (br=NR_NO) or
  2486. ((br<>NR_RBP) and (br<>NR_R13) and (br<>NR_EBP) and (br<>NR_R13D) and (o=0) and (sym=nil)) then
  2487. md:=0
  2488. else
  2489. if ((o>=-128) and (o<=127) and (sym=nil) and (not(uselargeoffset) or (o = 0))) then
  2490. md:=1
  2491. else
  2492. md:=2;
  2493. if (br=NR_NO) or (md=2) then
  2494. output.bytes:=4
  2495. else
  2496. output.bytes:=md;
  2497. { SIB needed ? }
  2498. if (ir=NR_NO) and (br<>NR_RSP) and (br<>NR_R12) and (br<>NR_ESP) and (br<>NR_R12D) then
  2499. begin
  2500. output.sib_present:=false;
  2501. output.modrm:=(md shl 6) or (rfield shl 3) or base;
  2502. end
  2503. else
  2504. begin
  2505. output.sib_present:=true;
  2506. output.modrm:=(md shl 6) or (rfield shl 3) or 4;
  2507. output.sib:=(scalefactor shl 6) or (index shl 3) or base;
  2508. end;
  2509. end;
  2510. output.size:=1+ord(output.sib_present)+output.bytes;
  2511. result:=true;
  2512. end;
  2513. {$elseif defined(i386) or defined(i8086)}
  2514. function process_ea_ref_32(const input:toper;out output:ea;rfield:longint; uselargeoffset: boolean):boolean;
  2515. var
  2516. sym : tasmsymbol;
  2517. md,s : byte;
  2518. base,index,scalefactor,
  2519. o : longint;
  2520. ir,br : Tregister;
  2521. isub,bsub : tsubregister;
  2522. begin
  2523. result:=false;
  2524. if ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)=R_MMREGISTER) and (input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) or // vector memory (AVX2)
  2525. ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)<>R_INTREGISTER) and (getregtype(input.ref^.index)<>R_MMREGISTER)) or
  2526. ((input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) then
  2527. internalerror(2003010802);
  2528. ir:=input.ref^.index;
  2529. br:=input.ref^.base;
  2530. isub:=getsubreg(ir);
  2531. bsub:=getsubreg(br);
  2532. s:=input.ref^.scalefactor;
  2533. o:=input.ref^.offset;
  2534. sym:=input.ref^.symbol;
  2535. { it's direct address }
  2536. if (br=NR_NO) and (ir=NR_NO) then
  2537. begin
  2538. { it's a pure offset }
  2539. output.sib_present:=false;
  2540. output.bytes:=4;
  2541. output.modrm:=5 or (rfield shl 3);
  2542. end
  2543. else
  2544. { it's an indirection }
  2545. begin
  2546. { 16 bit address? }
  2547. if ((ir<>NR_NO) and (isub in [R_SUBMMX,R_SUBMMY,R_SUBMMZ]) and
  2548. (br<>NR_NO) and (bsub=R_SUBD)
  2549. ) then
  2550. begin
  2551. // vector memory (AVX2) =>> ignore
  2552. end
  2553. else if ((ir<>NR_NO) and (isub<>R_SUBD)) or
  2554. ((br<>NR_NO) and (bsub<>R_SUBD)) then
  2555. message(asmw_e_16bit_not_supported);
  2556. {$ifdef OPTEA}
  2557. { make single reg base }
  2558. if (br=NR_NO) and (s=1) then
  2559. begin
  2560. br:=ir;
  2561. ir:=NR_NO;
  2562. end;
  2563. { convert [3,5,9]*EAX to EAX+[2,4,8]*EAX }
  2564. if (br=NR_NO) and
  2565. (((s=2) and (ir<>NR_ESP)) or
  2566. (s=3) or (s=5) or (s=9)) then
  2567. begin
  2568. br:=ir;
  2569. dec(s);
  2570. end;
  2571. { swap ESP into base if scalefactor is 1 }
  2572. if (s=1) and (ir=NR_ESP) then
  2573. begin
  2574. ir:=br;
  2575. br:=NR_ESP;
  2576. end;
  2577. {$endif OPTEA}
  2578. { wrong, for various reasons }
  2579. if (ir=NR_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (ir<>NR_NO)) then
  2580. exit;
  2581. { base }
  2582. case br of
  2583. NR_EAX : base:=0;
  2584. NR_ECX : base:=1;
  2585. NR_EDX : base:=2;
  2586. NR_EBX : base:=3;
  2587. NR_ESP : base:=4;
  2588. NR_NO,
  2589. NR_EBP : base:=5;
  2590. NR_ESI : base:=6;
  2591. NR_EDI : base:=7;
  2592. else
  2593. exit;
  2594. end;
  2595. { index }
  2596. case ir of
  2597. NR_EAX,
  2598. NR_XMM0,
  2599. NR_YMM0,
  2600. NR_ZMM0: index:=0;
  2601. NR_ECX,
  2602. NR_XMM1,
  2603. NR_YMM1,
  2604. NR_ZMM1: index:=1;
  2605. NR_EDX,
  2606. NR_XMM2,
  2607. NR_YMM2,
  2608. NR_ZMM2: index:=2;
  2609. NR_EBX,
  2610. NR_XMM3,
  2611. NR_YMM3,
  2612. NR_ZMM3: index:=3;
  2613. NR_NO,
  2614. NR_XMM4,
  2615. NR_YMM4,
  2616. NR_ZMM4: index:=4;
  2617. NR_EBP,
  2618. NR_XMM5,
  2619. NR_YMM5,
  2620. NR_ZMM5: index:=5;
  2621. NR_ESI,
  2622. NR_XMM6,
  2623. NR_YMM6,
  2624. NR_ZMM6: index:=6;
  2625. NR_EDI,
  2626. NR_XMM7,
  2627. NR_YMM7,
  2628. NR_ZMM7: index:=7;
  2629. else
  2630. exit;
  2631. end;
  2632. case s of
  2633. 0,
  2634. 1 : scalefactor:=0;
  2635. 2 : scalefactor:=1;
  2636. 4 : scalefactor:=2;
  2637. 8 : scalefactor:=3;
  2638. else
  2639. exit;
  2640. end;
  2641. if (br=NR_NO) or
  2642. ((br<>NR_EBP) and (o=0) and (sym=nil)) then
  2643. md:=0
  2644. else
  2645. if ((o>=-128) and (o<=127) and (sym=nil) and (not(uselargeoffset) or (o = 0))) then
  2646. md:=1
  2647. else
  2648. md:=2;
  2649. if (br=NR_NO) or (md=2) then
  2650. output.bytes:=4
  2651. else
  2652. output.bytes:=md;
  2653. { SIB needed ? }
  2654. if (ir=NR_NO) and (br<>NR_ESP) then
  2655. begin
  2656. output.sib_present:=false;
  2657. output.modrm:=(longint(md) shl 6) or (rfield shl 3) or base;
  2658. end
  2659. else
  2660. begin
  2661. output.sib_present:=true;
  2662. output.modrm:=(longint(md) shl 6) or (rfield shl 3) or 4;
  2663. output.sib:=(scalefactor shl 6) or (index shl 3) or base;
  2664. end;
  2665. end;
  2666. if output.sib_present then
  2667. output.size:=2+output.bytes
  2668. else
  2669. output.size:=1+output.bytes;
  2670. result:=true;
  2671. end;
  2672. procedure maybe_swap_index_base(var br,ir:Tregister);
  2673. var
  2674. tmpreg: Tregister;
  2675. begin
  2676. if ((br=NR_NO) or (br=NR_SI) or (br=NR_DI)) and
  2677. ((ir=NR_NO) or (ir=NR_BP) or (ir=NR_BX)) then
  2678. begin
  2679. tmpreg:=br;
  2680. br:=ir;
  2681. ir:=tmpreg;
  2682. end;
  2683. end;
  2684. function process_ea_ref_16(const input:toper;out output:ea;rfield:longint; uselargeoffset: boolean):boolean;
  2685. var
  2686. sym : tasmsymbol;
  2687. md,s : byte;
  2688. base,
  2689. o : longint;
  2690. ir,br : Tregister;
  2691. isub,bsub : tsubregister;
  2692. begin
  2693. result:=false;
  2694. if ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)<>R_INTREGISTER)) or
  2695. ((input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) then
  2696. internalerror(2003010803);
  2697. ir:=input.ref^.index;
  2698. br:=input.ref^.base;
  2699. isub:=getsubreg(ir);
  2700. bsub:=getsubreg(br);
  2701. s:=input.ref^.scalefactor;
  2702. o:=input.ref^.offset;
  2703. sym:=input.ref^.symbol;
  2704. { it's a direct address }
  2705. if (br=NR_NO) and (ir=NR_NO) then
  2706. begin
  2707. { it's a pure offset }
  2708. output.bytes:=2;
  2709. output.modrm:=6 or (rfield shl 3);
  2710. end
  2711. else
  2712. { it's an indirection }
  2713. begin
  2714. { 32 bit address? }
  2715. if ((ir<>NR_NO) and (isub<>R_SUBW)) or
  2716. ((br<>NR_NO) and (bsub<>R_SUBW)) then
  2717. message(asmw_e_32bit_not_supported);
  2718. { scalefactor can only be 1 in 16-bit addresses }
  2719. if (s<>1) and (ir<>NR_NO) then
  2720. exit;
  2721. maybe_swap_index_base(br,ir);
  2722. if (br=NR_BX) and (ir=NR_SI) then
  2723. base:=0
  2724. else if (br=NR_BX) and (ir=NR_DI) then
  2725. base:=1
  2726. else if (br=NR_BP) and (ir=NR_SI) then
  2727. base:=2
  2728. else if (br=NR_BP) and (ir=NR_DI) then
  2729. base:=3
  2730. else if (br=NR_NO) and (ir=NR_SI) then
  2731. base:=4
  2732. else if (br=NR_NO) and (ir=NR_DI) then
  2733. base:=5
  2734. else if (br=NR_BP) and (ir=NR_NO) then
  2735. base:=6
  2736. else if (br=NR_BX) and (ir=NR_NO) then
  2737. base:=7
  2738. else
  2739. exit;
  2740. if (base<>6) and (o=0) and (sym=nil) then
  2741. md:=0
  2742. else if ((o>=-128) and (o<=127) and (sym=nil) and (not(uselargeoffset) or (o = 0))) then
  2743. md:=1
  2744. else
  2745. md:=2;
  2746. output.bytes:=md;
  2747. output.modrm:=(longint(md) shl 6) or (rfield shl 3) or base;
  2748. end;
  2749. output.size:=1+output.bytes;
  2750. output.sib_present:=false;
  2751. result:=true;
  2752. end;
  2753. {$endif}
  2754. function process_ea(const input:toper;out output:ea;rfield:longint; uselargeoffset: boolean):boolean;
  2755. var
  2756. rv : byte;
  2757. begin
  2758. result:=false;
  2759. fillchar(output,sizeof(output),0);
  2760. {Register ?}
  2761. if (input.typ=top_reg) then
  2762. begin
  2763. rv:=regval(input.reg);
  2764. output.modrm:=$c0 or (rfield shl 3) or rv;
  2765. output.size:=1;
  2766. {$ifdef x86_64}
  2767. output.rex:=output.rex or (rexbits(input.reg) and $F1);
  2768. {$endif x86_64}
  2769. result:=true;
  2770. exit;
  2771. end;
  2772. {No register, so memory reference.}
  2773. if input.typ<>top_ref then
  2774. internalerror(200409263);
  2775. {$if defined(x86_64)}
  2776. result:=process_ea_ref_64_32(input,output,rfield, uselargeoffset);
  2777. {$elseif defined(i386) or defined(i8086)}
  2778. if is_16_bit_ref(input.ref^) then
  2779. result:=process_ea_ref_16(input,output,rfield, uselargeoffset)
  2780. else
  2781. result:=process_ea_ref_32(input,output,rfield, uselargeoffset);
  2782. {$endif}
  2783. end;
  2784. function taicpu.calcsize(p:PInsEntry):shortint;
  2785. var
  2786. codes : pchar;
  2787. c : byte;
  2788. len : shortint;
  2789. ea_data : ea;
  2790. exists_evex: boolean;
  2791. exists_vex: boolean;
  2792. exists_vex_extension: boolean;
  2793. exists_prefix_66: boolean;
  2794. exists_prefix_F2: boolean;
  2795. exists_prefix_F3: boolean;
  2796. exists_l256: boolean;
  2797. exists_l512: boolean;
  2798. exists_EVEXW1: boolean;
  2799. {$ifdef x86_64}
  2800. omit_rexw : boolean;
  2801. {$endif x86_64}
  2802. begin
  2803. len:=0;
  2804. codes:=@p^.code[0];
  2805. exists_vex := false;
  2806. exists_vex_extension := false;
  2807. exists_prefix_66 := false;
  2808. exists_prefix_F2 := false;
  2809. exists_prefix_F3 := false;
  2810. exists_evex := false;
  2811. exists_l256 := false;
  2812. exists_l512 := false;
  2813. exists_EVEXW1 := false;
  2814. {$ifdef x86_64}
  2815. rex:=0;
  2816. omit_rexw:=false;
  2817. {$endif x86_64}
  2818. repeat
  2819. c:=ord(codes^);
  2820. inc(codes);
  2821. case c of
  2822. &0 :
  2823. break;
  2824. &1,&2,&3 :
  2825. begin
  2826. inc(codes,c);
  2827. inc(len,c);
  2828. end;
  2829. &10,&11,&12 :
  2830. begin
  2831. {$ifdef x86_64}
  2832. rex:=rex or (rexbits(oper[c-&10]^.reg) and $F1);
  2833. {$endif x86_64}
  2834. inc(codes);
  2835. inc(len);
  2836. end;
  2837. &13,&23 :
  2838. begin
  2839. inc(codes);
  2840. inc(len);
  2841. end;
  2842. &4,&5,&6,&7 :
  2843. begin
  2844. if opsize={$ifdef i8086}S_L{$else}S_W{$endif} then
  2845. inc(len,2)
  2846. else
  2847. inc(len);
  2848. end;
  2849. &14,&15,&16,
  2850. &20,&21,&22,
  2851. &24,&25,&26,&27,
  2852. &50,&51,&52 :
  2853. inc(len);
  2854. &30,&31,&32,
  2855. &37,
  2856. &60,&61,&62 :
  2857. inc(len,2);
  2858. &34,&35,&36:
  2859. begin
  2860. {$ifdef i8086}
  2861. inc(len,2);
  2862. {$else i8086}
  2863. if opsize=S_Q then
  2864. inc(len,8)
  2865. else
  2866. inc(len,4);
  2867. {$endif i8086}
  2868. end;
  2869. &44,&45,&46:
  2870. inc(len,sizeof(pint));
  2871. &54,&55,&56:
  2872. inc(len,8);
  2873. &40,&41,&42,
  2874. &70,&71,&72,
  2875. &254,&255,&256 :
  2876. inc(len,4);
  2877. &64,&65,&66:
  2878. {$ifdef i8086}
  2879. inc(len,2);
  2880. {$else i8086}
  2881. inc(len,4);
  2882. {$endif i8086}
  2883. &74,&75,&76,&77: ; // ignore vex-coded operand-idx
  2884. &320,&321,&322 :
  2885. begin
  2886. case (oper[c-&320]^.ot and OT_SIZE_MASK) of
  2887. {$if defined(i386) or defined(x86_64)}
  2888. OT_BITS16 :
  2889. {$elseif defined(i8086)}
  2890. OT_BITS32 :
  2891. {$endif}
  2892. inc(len);
  2893. {$ifdef x86_64}
  2894. OT_BITS64:
  2895. begin
  2896. rex:=rex or $48;
  2897. end;
  2898. {$endif x86_64}
  2899. end;
  2900. end;
  2901. &310 :
  2902. {$if defined(x86_64)}
  2903. { every insentry with code 0310 must be marked with NOX86_64 }
  2904. InternalError(2011051301);
  2905. {$elseif defined(i386)}
  2906. inc(len);
  2907. {$elseif defined(i8086)}
  2908. {nothing};
  2909. {$endif}
  2910. &311 :
  2911. {$if defined(x86_64) or defined(i8086)}
  2912. inc(len)
  2913. {$endif x86_64 or i8086}
  2914. ;
  2915. &324 :
  2916. {$ifndef i8086}
  2917. inc(len)
  2918. {$endif not i8086}
  2919. ;
  2920. &326 :
  2921. begin
  2922. {$ifdef x86_64}
  2923. rex:=rex or $48;
  2924. {$endif x86_64}
  2925. end;
  2926. &312,
  2927. &323,
  2928. &327,
  2929. &331,&332: ;
  2930. &325:
  2931. {$ifdef i8086}
  2932. inc(len)
  2933. {$endif i8086}
  2934. ;
  2935. &333:
  2936. begin
  2937. inc(len);
  2938. exists_prefix_F2 := true;
  2939. end;
  2940. &334:
  2941. begin
  2942. inc(len);
  2943. exists_prefix_F3 := true;
  2944. end;
  2945. &361:
  2946. begin
  2947. {$ifndef i8086}
  2948. inc(len);
  2949. exists_prefix_66 := true;
  2950. {$endif not i8086}
  2951. end;
  2952. &335:
  2953. {$ifdef x86_64}
  2954. omit_rexw:=true
  2955. {$endif x86_64}
  2956. ;
  2957. &336,
  2958. &337: {nothing};
  2959. &100..&227 :
  2960. begin
  2961. {$ifdef x86_64}
  2962. if (c<&177) then
  2963. begin
  2964. if (oper[c and 7]^.typ=top_reg) then
  2965. begin
  2966. rex:=rex or (rexbits(oper[c and 7]^.reg) and $F4);
  2967. end;
  2968. end;
  2969. {$endif x86_64}
  2970. if (oper[(c shr 3) and 7]^.typ = top_ref) and
  2971. (oper[(c shr 3) and 7]^.ref^.offset <> 0) then
  2972. begin
  2973. if (exists_vex and exists_evex and CheckUseEVEX) or
  2974. (not(exists_vex) and exists_evex) then
  2975. begin
  2976. CheckEVEXTuple(oper[(c shr 3) and 7]^, p, not(exists_l256 or exists_l512), exists_l256, exists_l512, exists_EVEXW1);
  2977. //const aInput:toper; aInsEntry: pInsentry; aIsVector128, aIsVector256, aIsVector512, aIsEVEXW1: boolean);
  2978. end;
  2979. end;
  2980. if process_ea(oper[(c shr 3) and 7]^, ea_data, 0, EVEXTupleState = etsNotTuple) then
  2981. inc(len,ea_data.size)
  2982. else Message(asmw_e_invalid_effective_address);
  2983. {$ifdef x86_64}
  2984. rex:=rex or ea_data.rex;
  2985. {$endif x86_64}
  2986. end;
  2987. &350:
  2988. begin
  2989. exists_evex := true;
  2990. end;
  2991. &351: exists_l512 := true; // EVEX length bit 512
  2992. &352: exists_EVEXW1 := true; // EVEX W1
  2993. &362: // VEX prefix for AVX (length = 2 or 3 bytes, dependens on REX.XBW or opcode-prefix ($0F38 or $0F3A))
  2994. // =>> DEFAULT = 2 Bytes
  2995. begin
  2996. //if not(exists_vex) then
  2997. //begin
  2998. // inc(len, 2);
  2999. //end;
  3000. exists_vex := true;
  3001. end;
  3002. &363: // REX.W = 1
  3003. // =>> VEX prefix length = 3
  3004. begin
  3005. if not(exists_vex_extension) then
  3006. begin
  3007. //inc(len);
  3008. exists_vex_extension := true;
  3009. end;
  3010. end;
  3011. &364: exists_l256 := true; // VEX length bit 256
  3012. &366, // operand 2 (ymmreg) encoded immediate byte (bit 4-7)
  3013. &367: inc(len); // operand 3 (ymmreg) encoded immediate byte (bit 4-7)
  3014. &370: // VEX-Extension prefix $0F
  3015. // ignore for calculating length
  3016. ;
  3017. &371, // VEX-Extension prefix $0F38
  3018. &372: // VEX-Extension prefix $0F3A
  3019. begin
  3020. if not(exists_vex_extension) then
  3021. begin
  3022. //inc(len);
  3023. exists_vex_extension := true;
  3024. end;
  3025. end;
  3026. &300,&301,&302:
  3027. begin
  3028. {$if defined(x86_64) or defined(i8086)}
  3029. if (oper[c and 3]^.ot and OT_SIZE_MASK)=OT_BITS32 then
  3030. inc(len);
  3031. {$endif x86_64 or i8086}
  3032. end;
  3033. else
  3034. InternalError(200603141);
  3035. end;
  3036. until false;
  3037. {$ifdef x86_64}
  3038. if ((rex and $80)<>0) and ((rex and $4F)<>0) then
  3039. Message(asmw_e_bad_reg_with_rex);
  3040. rex:=rex and $4F; { reset extra bits in upper nibble }
  3041. if omit_rexw then
  3042. begin
  3043. if rex=$48 then { remove rex entirely? }
  3044. rex:=0
  3045. else
  3046. rex:=rex and $F7;
  3047. end;
  3048. if not(exists_vex or exists_evex) then
  3049. begin
  3050. if rex<>0 then
  3051. Inc(len);
  3052. end;
  3053. {$endif}
  3054. if exists_evex and
  3055. exists_vex then
  3056. begin
  3057. if CheckUseEVEX then
  3058. begin
  3059. inc(len, 4);
  3060. end
  3061. else
  3062. begin
  3063. inc(len, 2);
  3064. if exists_vex_extension then inc(len);
  3065. {$ifdef x86_64}
  3066. if not(exists_vex_extension) then
  3067. if rex and $0B <> 0 then inc(len); // REX.WXB <> 0 =>> needed VEX-Extension
  3068. {$endif x86_64}
  3069. end;
  3070. if exists_prefix_66 then dec(len);
  3071. if exists_prefix_F2 then dec(len);
  3072. if exists_prefix_F3 then dec(len);
  3073. end
  3074. else if exists_evex then
  3075. begin
  3076. inc(len, 4);
  3077. if exists_prefix_66 then dec(len);
  3078. if exists_prefix_F2 then dec(len);
  3079. if exists_prefix_F3 then dec(len);
  3080. end
  3081. else
  3082. begin
  3083. if exists_vex then
  3084. begin
  3085. inc(len,2);
  3086. if exists_prefix_66 then dec(len);
  3087. if exists_prefix_F2 then dec(len);
  3088. if exists_prefix_F3 then dec(len);
  3089. if exists_vex_extension then inc(len);
  3090. {$ifdef x86_64}
  3091. if not(exists_vex_extension) then
  3092. if rex and $0B <> 0 then inc(len); // REX.WXB <> 0 =>> needed VEX-Extension
  3093. {$endif x86_64}
  3094. end;
  3095. end;
  3096. calcsize:=len;
  3097. end;
  3098. procedure taicpu.write0x66prefix(objdata:TObjData);
  3099. const
  3100. b66: Byte=$66;
  3101. begin
  3102. {$ifdef i8086}
  3103. if (objdata.CPUType<>cpu_none) and (objdata.CPUType<cpu_386) then
  3104. Message(asmw_e_instruction_not_supported_by_cpu);
  3105. {$endif i8086}
  3106. objdata.writebytes(b66,1);
  3107. end;
  3108. procedure taicpu.write0x67prefix(objdata:TObjData);
  3109. const
  3110. b67: Byte=$67;
  3111. begin
  3112. {$ifdef i8086}
  3113. if (objdata.CPUType<>cpu_none) and (objdata.CPUType<cpu_386) then
  3114. Message(asmw_e_instruction_not_supported_by_cpu);
  3115. {$endif i8086}
  3116. objdata.writebytes(b67,1);
  3117. end;
  3118. procedure taicpu.gencode(objdata: TObjData);
  3119. {
  3120. * the actual codes (C syntax, i.e. octal):
  3121. * \0 - terminates the code. (Unless it's a literal of course.)
  3122. * \1, \2, \3 - that many literal bytes follow in the code stream
  3123. * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
  3124. * (POP is never used for CS) depending on operand 0
  3125. * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
  3126. * on operand 0
  3127. * \10, \11, \12 - a literal byte follows in the code stream, to be added
  3128. * to the register value of operand 0, 1 or 2
  3129. * \13 - a literal byte follows in the code stream, to be added
  3130. * to the condition code value of the instruction.
  3131. * \14, \15, \16 - a signed byte immediate operand, from operand 0, 1 or 2
  3132. * \20, \21, \22 - a byte immediate operand, from operand 0, 1 or 2
  3133. * \23 - a literal byte follows in the code stream, to be added
  3134. * to the inverted condition code value of the instruction
  3135. * (inverted version of \13).
  3136. * \24, \25, \26, \27 - an unsigned byte immediate operand, from operand 0, 1, 2 or 3
  3137. * \30, \31, \32 - a word immediate operand, from operand 0, 1 or 2
  3138. * \34, \35, \36 - select between \3[012] and \4[012] depending on 16/32 bit
  3139. * assembly mode or the address-size override on the operand
  3140. * \37 - a word constant, from the _segment_ part of operand 0
  3141. * \40, \41, \42 - a long immediate operand, from operand 0, 1 or 2
  3142. * \44, \45, \46 - select between \3[012], \4[012] or \5[456] depending
  3143. on the address size of instruction
  3144. * \50, \51, \52 - a byte relative operand, from operand 0, 1 or 2
  3145. * \54, \55, \56 - a qword immediate, from operand 0, 1 or 2
  3146. * \60, \61, \62 - a word relative operand, from operand 0, 1 or 2
  3147. * \64, \65, \66 - select between \6[012] and \7[012] depending on 16/32 bit
  3148. * assembly mode or the address-size override on the operand
  3149. * \70, \71, \72 - a long relative operand, from operand 0, 1 or 2
  3150. * \74, \75, \76 - a vex-coded vector operand, from operand 0, 1 or 2
  3151. * \1ab - a ModRM, calculated on EA in operand a, with the spare
  3152. * field the register value of operand b.
  3153. * \2ab - a ModRM, calculated on EA in operand a, with the spare
  3154. * field equal to digit b.
  3155. * \254,\255,\256 - a signed 32-bit immediate to be extended to 64 bits
  3156. * \300,\301,\302 - might be an 0x67, depending on the address size of
  3157. * the memory reference in operand x.
  3158. * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
  3159. * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
  3160. * \312 - (disassembler only) invalid with non-default address size.
  3161. * \320,\321,\322 - might be an 0x66 or 0x48 byte, depending on the operand
  3162. * size of operand x.
  3163. * \324 - indicates fixed 16-bit operand size, i.e. optional 0x66.
  3164. * \325 - indicates fixed 32-bit operand size, i.e. optional 0x66.
  3165. * \326 - indicates fixed 64-bit operand size, i.e. optional 0x48.
  3166. * \327 - indicates that this instruction is only valid when the
  3167. * operand size is the default (instruction to disassembler,
  3168. * generates no code in the assembler)
  3169. * \331 - instruction not valid with REP prefix. Hint for
  3170. * disassembler only; for SSE instructions.
  3171. * \332 - disassemble a rep (0xF3 byte) prefix as repe not rep.
  3172. * \333 - 0xF3 prefix for SSE instructions
  3173. * \334 - 0xF2 prefix for SSE instructions
  3174. * \335 - Indicates 64-bit operand size with REX.W not necessary / 64-bit scalar vector operand size
  3175. * \336 - Indicates 32-bit scalar vector operand size
  3176. * \337 - Indicates 64-bit scalar vector operand size
  3177. * \350 - EVEX prefix for AVX instructions
  3178. * \351 - EVEX Vector length 512
  3179. * \352 - EVEX W1
  3180. * \361 - 0x66 prefix for SSE instructions
  3181. * \362 - VEX prefix for AVX instructions
  3182. * \363 - VEX W1
  3183. * \364 - VEX Vector length 256
  3184. * \366 - operand 2 (ymmreg,zmmreg) encoded in bit 4-7 of the immediate byte
  3185. * \367 - operand 3 (ymmreg,zmmreg) encoded in bit 4-7 of the immediate byte
  3186. * \370 - VEX 0F-FLAG
  3187. * \371 - VEX 0F38-FLAG
  3188. * \372 - VEX 0F3A-FLAG
  3189. }
  3190. var
  3191. {$ifdef i8086}
  3192. currval : longint;
  3193. {$else i8086}
  3194. currval : aint;
  3195. {$endif i8086}
  3196. currsym : tobjsymbol;
  3197. currrelreloc,
  3198. currabsreloc,
  3199. currabsreloc32 : TObjRelocationType;
  3200. {$ifdef x86_64}
  3201. rexwritten : boolean;
  3202. {$endif x86_64}
  3203. procedure getvalsym(opidx:longint);
  3204. begin
  3205. case oper[opidx]^.typ of
  3206. top_ref :
  3207. begin
  3208. currval:=oper[opidx]^.ref^.offset;
  3209. currsym:=ObjData.symbolref(oper[opidx]^.ref^.symbol);
  3210. {$ifdef i8086}
  3211. if oper[opidx]^.ref^.refaddr=addr_seg then
  3212. begin
  3213. currrelreloc:=RELOC_SEGREL;
  3214. currabsreloc:=RELOC_SEG;
  3215. currabsreloc32:=RELOC_SEG;
  3216. end
  3217. else if oper[opidx]^.ref^.refaddr=addr_dgroup then
  3218. begin
  3219. currrelreloc:=RELOC_DGROUPREL;
  3220. currabsreloc:=RELOC_DGROUP;
  3221. currabsreloc32:=RELOC_DGROUP;
  3222. end
  3223. else if oper[opidx]^.ref^.refaddr=addr_fardataseg then
  3224. begin
  3225. currrelreloc:=RELOC_FARDATASEGREL;
  3226. currabsreloc:=RELOC_FARDATASEG;
  3227. currabsreloc32:=RELOC_FARDATASEG;
  3228. end
  3229. else
  3230. {$endif i8086}
  3231. {$ifdef i386}
  3232. if (oper[opidx]^.ref^.refaddr=addr_pic) and
  3233. (tf_pic_uses_got in target_info.flags) then
  3234. begin
  3235. currrelreloc:=RELOC_PLT32;
  3236. currabsreloc:=RELOC_GOT32;
  3237. currabsreloc32:=RELOC_GOT32;
  3238. end
  3239. else if oper[opidx]^.ref^.refaddr=addr_ntpoff then
  3240. begin
  3241. currrelreloc:=RELOC_NTPOFF;
  3242. currabsreloc:=RELOC_NTPOFF;
  3243. currabsreloc32:=RELOC_NTPOFF;
  3244. end
  3245. else if oper[opidx]^.ref^.refaddr=addr_tlsgd then
  3246. begin
  3247. currrelreloc:=RELOC_TLSGD;
  3248. currabsreloc:=RELOC_TLSGD;
  3249. currabsreloc32:=RELOC_TLSGD;
  3250. end
  3251. else
  3252. {$endif i386}
  3253. {$ifdef x86_64}
  3254. if oper[opidx]^.ref^.refaddr=addr_pic then
  3255. begin
  3256. currrelreloc:=RELOC_PLT32;
  3257. currabsreloc:=RELOC_GOTPCREL;
  3258. currabsreloc32:=RELOC_GOTPCREL;
  3259. end
  3260. else if oper[opidx]^.ref^.refaddr=addr_pic_no_got then
  3261. begin
  3262. currrelreloc:=RELOC_RELATIVE;
  3263. currabsreloc:=RELOC_RELATIVE;
  3264. currabsreloc32:=RELOC_RELATIVE;
  3265. end
  3266. else if oper[opidx]^.ref^.refaddr=addr_tpoff then
  3267. begin
  3268. currrelreloc:=RELOC_TPOFF;
  3269. currabsreloc:=RELOC_TPOFF;
  3270. currabsreloc32:=RELOC_TPOFF;
  3271. end
  3272. else if oper[opidx]^.ref^.refaddr=addr_tlsgd then
  3273. begin
  3274. currrelreloc:=RELOC_TLSGD;
  3275. currabsreloc:=RELOC_TLSGD;
  3276. currabsreloc32:=RELOC_TLSGD;
  3277. end
  3278. else
  3279. {$endif x86_64}
  3280. begin
  3281. currrelreloc:=RELOC_RELATIVE;
  3282. currabsreloc:=RELOC_ABSOLUTE;
  3283. currabsreloc32:=RELOC_ABSOLUTE32;
  3284. end;
  3285. end;
  3286. top_const :
  3287. begin
  3288. {$ifdef i8086}
  3289. currval:=longint(oper[opidx]^.val);
  3290. {$else i8086}
  3291. currval:=aint(oper[opidx]^.val);
  3292. {$endif i8086}
  3293. currsym:=nil;
  3294. currabsreloc:=RELOC_ABSOLUTE;
  3295. currabsreloc32:=RELOC_ABSOLUTE32;
  3296. end;
  3297. else
  3298. Message(asmw_e_immediate_or_reference_expected);
  3299. end;
  3300. end;
  3301. {$ifdef x86_64}
  3302. procedure maybewriterex;
  3303. begin
  3304. if (rex<>0) and not(rexwritten) then
  3305. begin
  3306. rexwritten:=true;
  3307. objdata.writebytes(rex,1);
  3308. end;
  3309. end;
  3310. {$endif x86_64}
  3311. procedure objdata_writereloc(Data:TRelocDataInt;len:aword;p:TObjSymbol;Reloctype:TObjRelocationType);
  3312. begin
  3313. {$ifdef i386}
  3314. { Special case of '_GLOBAL_OFFSET_TABLE_'
  3315. which needs a special relocation type R_386_GOTPC }
  3316. if assigned (p) and
  3317. (p.name='_GLOBAL_OFFSET_TABLE_') and
  3318. (tf_pic_uses_got in target_info.flags) then
  3319. begin
  3320. { nothing else than a 4 byte relocation should occur
  3321. for GOT }
  3322. if len<>4 then
  3323. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  3324. Reloctype:=RELOC_GOTPC;
  3325. { We need to add the offset of the relocation
  3326. of _GLOBAL_OFFSET_TABLE symbol within
  3327. the current instruction }
  3328. inc(data,objdata.currobjsec.size-insoffset);
  3329. end;
  3330. {$endif i386}
  3331. objdata.writereloc(data,len,p,Reloctype);
  3332. {$ifdef x86_64}
  3333. { Computed offset is not yet correct for GOTPC relocation }
  3334. { RELOC_GOTPCREL, RELOC_REX_GOTPCRELX, RELOC_GOTPCRELX need special handling }
  3335. if assigned(p) and (RelocType in [RELOC_GOTPCREL, RELOC_REX_GOTPCRELX, RELOC_GOTPCRELX]) and
  3336. { These relocations seem to be used only for ELF
  3337. which always has relocs_use_addend set to true
  3338. so that it is the orgsize of the last relocation which needs to be fixed PM }
  3339. (insend<>objdata.CurrObjSec.size) then
  3340. dec(TObjRelocation(objdata.CurrObjSec.ObjRelocations.Last).orgsize,insend-objdata.CurrObjSec.size);
  3341. {$endif}
  3342. end;
  3343. const
  3344. CondVal:array[TAsmCond] of byte=($0,
  3345. $7, $3, $2, $6, $2, $4, $F, $D, $C, $E, $6, $2,
  3346. $3, $7, $3, $5, $E, $C, $D, $F, $1, $B, $9, $5,
  3347. $0, $A, $A, $B, $8, $4);
  3348. var
  3349. i: integer;
  3350. c : byte;
  3351. pb : pbyte;
  3352. codes : pchar;
  3353. bytes : array[0..3] of byte;
  3354. rfield,
  3355. data,s,opidx : longint;
  3356. ea_data : ea;
  3357. relsym : TObjSymbol;
  3358. needed_VEX_Extension: boolean;
  3359. needed_VEX: boolean;
  3360. needed_EVEX: boolean;
  3361. {$ifdef x86_64}
  3362. needed_VSIB: boolean;
  3363. {$endif x86_64}
  3364. opmode: integer;
  3365. VEXvvvv: byte;
  3366. VEXmmmmm: byte;
  3367. {
  3368. VEXw : byte;
  3369. VEXpp : byte;
  3370. VEXll : byte;
  3371. }
  3372. EVEXvvvv: byte;
  3373. EVEXpp: byte;
  3374. EVEXr: byte;
  3375. EVEXx: byte;
  3376. EVEXv: byte;
  3377. EVEXll: byte;
  3378. EVEXw1: byte;
  3379. EVEXz : byte;
  3380. EVEXaaa : byte;
  3381. EVEXb : byte;
  3382. EVEXmm : byte;
  3383. begin
  3384. { safety check }
  3385. if objdata.currobjsec.size<>longword(insoffset) then
  3386. internalerror(200130121);
  3387. { those variables are initialized inside local procedures, the dfa cannot handle this yet }
  3388. currsym:=nil;
  3389. currabsreloc:=RELOC_NONE;
  3390. currabsreloc32:=RELOC_NONE;
  3391. currrelreloc:=RELOC_NONE;
  3392. currval:=0;
  3393. { check instruction's processor level }
  3394. { todo: maybe adapt and enable this code for i386 and x86_64 as well }
  3395. {$ifdef i8086}
  3396. if objdata.CPUType<>cpu_none then
  3397. begin
  3398. if IF_8086 in insentry^.flags then
  3399. else if IF_186 in insentry^.flags then
  3400. begin
  3401. if objdata.CPUType<cpu_186 then
  3402. Message(asmw_e_instruction_not_supported_by_cpu);
  3403. end
  3404. else if IF_286 in insentry^.flags then
  3405. begin
  3406. if objdata.CPUType<cpu_286 then
  3407. Message(asmw_e_instruction_not_supported_by_cpu);
  3408. end
  3409. else if IF_386 in insentry^.flags then
  3410. begin
  3411. if objdata.CPUType<cpu_386 then
  3412. Message(asmw_e_instruction_not_supported_by_cpu);
  3413. end
  3414. else if IF_486 in insentry^.flags then
  3415. begin
  3416. if objdata.CPUType<cpu_486 then
  3417. Message(asmw_e_instruction_not_supported_by_cpu);
  3418. end
  3419. else if IF_PENT in insentry^.flags then
  3420. begin
  3421. if objdata.CPUType<cpu_Pentium then
  3422. Message(asmw_e_instruction_not_supported_by_cpu);
  3423. end
  3424. else if IF_P6 in insentry^.flags then
  3425. begin
  3426. if objdata.CPUType<cpu_Pentium2 then
  3427. Message(asmw_e_instruction_not_supported_by_cpu);
  3428. end
  3429. else if IF_KATMAI in insentry^.flags then
  3430. begin
  3431. if objdata.CPUType<cpu_Pentium3 then
  3432. Message(asmw_e_instruction_not_supported_by_cpu);
  3433. end
  3434. else if insentry^.flags*[IF_WILLAMETTE,IF_PRESCOTT]<>[] then
  3435. begin
  3436. if objdata.CPUType<cpu_Pentium4 then
  3437. Message(asmw_e_instruction_not_supported_by_cpu);
  3438. end
  3439. else if IF_NEC in insentry^.flags then
  3440. begin
  3441. { the NEC V20/V30 extensions are incompatible with 386+, due to overlapping opcodes }
  3442. if objdata.CPUType>=cpu_386 then
  3443. Message(asmw_e_instruction_not_supported_by_cpu);
  3444. end
  3445. else if IF_SANDYBRIDGE in insentry^.flags then
  3446. begin
  3447. { todo: handle these properly }
  3448. end;
  3449. end;
  3450. {$endif i8086}
  3451. { load data to write }
  3452. codes:=insentry^.code;
  3453. {$ifdef x86_64}
  3454. rexwritten:=false;
  3455. {$endif x86_64}
  3456. { Force word push/pop for registers }
  3457. if (opsize={$ifdef i8086}S_L{$else}S_W{$endif}) and ((codes[0]=#4) or (codes[0]=#6) or
  3458. ((codes[0]=#1) and ((codes[2]=#5) or (codes[2]=#7)))) then
  3459. write0x66prefix(objdata);
  3460. // needed VEX Prefix (for AVX etc.)
  3461. needed_VEX := false;
  3462. needed_EVEX := false;
  3463. needed_VEX_Extension := false;
  3464. {$ifdef x86_64}
  3465. needed_VSIB := false;
  3466. {$endif x86_64}
  3467. opmode := -1;
  3468. VEXvvvv := 0;
  3469. VEXmmmmm := 0;
  3470. {
  3471. VEXll := 0;
  3472. VEXw := 0;
  3473. VEXpp := 0;
  3474. }
  3475. EVEXpp := 0;
  3476. EVEXvvvv := 0;
  3477. EVEXr := 0;
  3478. EVEXx := 0;
  3479. EVEXv := 0;
  3480. EVEXll := 0;
  3481. EVEXw1 := 0;
  3482. EVEXz := 0;
  3483. EVEXaaa := 0;
  3484. EVEXb := 0;
  3485. EVEXmm := 0;
  3486. repeat
  3487. c:=ord(codes^);
  3488. inc(codes);
  3489. case c of
  3490. &0: break;
  3491. &1,
  3492. &2,
  3493. &3: inc(codes,c);
  3494. &10,
  3495. &11,
  3496. &12: inc(codes, 1);
  3497. &74: opmode := 0;
  3498. &75: opmode := 1;
  3499. &76: opmode := 2;
  3500. &100..&227: begin
  3501. // AVX 512 - EVEX
  3502. // check operands
  3503. if (c shr 6) = 1 then
  3504. begin
  3505. opidx := c and 7;
  3506. if ops > opidx then
  3507. begin
  3508. if (oper[opidx]^.typ=top_reg) then
  3509. if getsupreg(oper[opidx]^.reg) and $10 = $0 then EVEXr := 1;
  3510. end
  3511. end
  3512. else EVEXr := 1; // modrm:reg not used =>> 1
  3513. opidx := (c shr 3) and 7;
  3514. if ops > opidx then
  3515. case oper[opidx]^.typ of
  3516. top_reg: if getsupreg(oper[opidx]^.reg) and $10 = $0 then EVEXx := 1;
  3517. top_ref: begin
  3518. if getsupreg(oper[opidx]^.ref^.index) and $08 = $0 then EVEXx := 1;
  3519. if getsubreg(oper[opidx]^.ref^.index) in [R_SUBMMX,R_SUBMMY,R_SUBMMZ] then
  3520. begin
  3521. // VSIB memory addresing
  3522. if getsupreg(oper[opidx]^.ref^.index) and $10 = $0 then EVEXv := 1; // VECTOR-Index
  3523. {$ifdef x86_64}
  3524. needed_VSIB := true;
  3525. {$endif x86_64}
  3526. end;
  3527. end;
  3528. else
  3529. Internalerror(2019081014);
  3530. end;
  3531. end;
  3532. &333: begin
  3533. VEXvvvv := VEXvvvv OR $02; // set SIMD-prefix $F3
  3534. //VEXpp := $02; // set SIMD-prefix $F3
  3535. EVEXpp := $02; // set SIMD-prefix $F3
  3536. end;
  3537. &334: begin
  3538. VEXvvvv := VEXvvvv OR $03; // set SIMD-prefix $F2
  3539. //VEXpp := $03; // set SIMD-prefix $F2
  3540. EVEXpp := $03; // set SIMD-prefix $F2
  3541. end;
  3542. &350: needed_EVEX := true; // AVX512 instruction or AVX128/256/512-instruction (depended on operands [x,y,z]mm16..)
  3543. &351: EVEXll := $02; // vectorlength = 512 bits AND no scalar
  3544. &352: EVEXw1 := $01;
  3545. &361: begin
  3546. VEXvvvv := VEXvvvv OR $01; // set SIMD-prefix $66
  3547. //VEXpp := $01; // set SIMD-prefix $66
  3548. EVEXpp := $01; // set SIMD-prefix $66
  3549. end;
  3550. &362: needed_VEX := true;
  3551. &363: begin
  3552. needed_VEX_Extension := true;
  3553. VEXvvvv := VEXvvvv OR (1 shl 7); // set REX.W
  3554. //VEXw := 1;
  3555. end;
  3556. &364: begin
  3557. VEXvvvv := VEXvvvv OR $04; // vectorlength = 256 bits AND no scalar
  3558. //VEXll := $01;
  3559. EVEXll := $01;
  3560. end;
  3561. &366,
  3562. &367: begin
  3563. opidx:=c-&364; { 0366->operand 2, 0367->operand 3 }
  3564. if (ops > opidx) and
  3565. (oper[opidx]^.typ=top_reg) and
  3566. ((oper[opidx]^.ot and OT_REG_EXTRA_MASK = otf_reg_xmm) or
  3567. (oper[opidx]^.ot and OT_REG_EXTRA_MASK = otf_reg_ymm) or
  3568. (oper[opidx]^.ot and OT_REG_EXTRA_MASK = otf_reg_zmm)) then
  3569. if (getsupreg(oper[opidx]^.reg) and $10 = $0) then EVEXx := 1;
  3570. end;
  3571. &370: begin
  3572. VEXmmmmm := VEXmmmmm OR $01; // set leading opcode byte $0F
  3573. EVEXmm := $01;
  3574. end;
  3575. &371: begin
  3576. needed_VEX_Extension := true;
  3577. VEXmmmmm := VEXmmmmm OR $02; // set leading opcode byte $0F38
  3578. EVEXmm := $02;
  3579. end;
  3580. &372: begin
  3581. needed_VEX_Extension := true;
  3582. VEXmmmmm := VEXmmmmm OR $03; // set leading opcode byte $0F3A
  3583. EVEXmm := $03;
  3584. end;
  3585. end;
  3586. until false;
  3587. {$ifndef x86_64}
  3588. EVEXv := 1;
  3589. EVEXx := 1;
  3590. EVEXr := 1;
  3591. {$endif}
  3592. if needed_VEX or needed_EVEX then
  3593. begin
  3594. if (opmode > ops) or
  3595. (opmode < -1) then
  3596. begin
  3597. Internalerror(777100);
  3598. end
  3599. else if opmode = -1 then
  3600. begin
  3601. VEXvvvv := VEXvvvv or ($0F shl 3); // set VEXvvvv bits (bits 6-3) to 1
  3602. EVEXvvvv := $0F;
  3603. {$ifdef x86_64}
  3604. if not(needed_vsib) then EVEXv := 1;
  3605. {$endif x86_64}
  3606. end
  3607. else if oper[opmode]^.typ = top_reg then
  3608. begin
  3609. VEXvvvv := VEXvvvv or ((not(regval(oper[opmode]^.reg)) and $07) shl 3);
  3610. EVEXvvvv := not(regval(oper[opmode]^.reg)) and $07;
  3611. {$ifdef x86_64}
  3612. if rexbits(oper[opmode]^.reg) = 0 then VEXvvvv := VEXvvvv or (1 shl 6);
  3613. if rexbits(oper[opmode]^.reg) = 0 then EVEXvvvv := EVEXvvvv or (1 shl 3);
  3614. if getsupreg(oper[opmode]^.reg) and $10 = 0 then EVEXv := 1;
  3615. {$else}
  3616. VEXvvvv := VEXvvvv or (1 shl 6);
  3617. EVEXvvvv := EVEXvvvv or (1 shl 3);
  3618. {$endif x86_64}
  3619. end
  3620. else Internalerror(777101);
  3621. if not(needed_VEX_Extension) then
  3622. begin
  3623. {$ifdef x86_64}
  3624. if rex and $0B <> 0 then needed_VEX_Extension := true;
  3625. {$endif x86_64}
  3626. end;
  3627. //TG
  3628. if needed_EVEX and needed_VEX then
  3629. begin
  3630. needed_EVEX := false;
  3631. if CheckUseEVEX then
  3632. begin
  3633. // EVEX-Flags r,v,x indicate extended-MMregister
  3634. // Flag = 0 =>> [x,y,z]mm16..[x,y,z]mm31
  3635. // Flag = 1 =>> [x,y,z]mm00..[x,y,z]mm15
  3636. needed_EVEX := true;
  3637. needed_VEX := false;
  3638. needed_VEX_Extension := false;
  3639. end;
  3640. end;
  3641. if needed_EVEX then
  3642. begin
  3643. EVEXaaa:= 0;
  3644. EVEXz := 0;
  3645. for i := 0 to ops - 1 do
  3646. if (oper[i]^.vopext and OTVE_VECTOR_MASK) <> 0 then
  3647. begin
  3648. if oper[i]^.vopext and OTVE_VECTOR_WRITEMASK = OTVE_VECTOR_WRITEMASK then
  3649. begin
  3650. EVEXaaa := oper[i]^.vopext and $07;
  3651. if oper[i]^.vopext and OTVE_VECTOR_ZERO = OTVE_VECTOR_ZERO then EVEXz := 1;
  3652. end;
  3653. if oper[i]^.vopext and OTVE_VECTOR_BCST = OTVE_VECTOR_BCST then
  3654. begin
  3655. EVEXb := 1;
  3656. end;
  3657. // flag EVEXb is multiple use (broadcast, sae and er)
  3658. if oper[i]^.vopext and OTVE_VECTOR_SAE = OTVE_VECTOR_SAE then
  3659. begin
  3660. EVEXb := 1;
  3661. end;
  3662. if oper[i]^.vopext and OTVE_VECTOR_ER = OTVE_VECTOR_ER then
  3663. begin
  3664. EVEXb := 1;
  3665. case oper[i]^.vopext and OTVE_VECTOR_ER_MASK of
  3666. OTVE_VECTOR_RNSAE: EVEXll := 0;
  3667. OTVE_VECTOR_RDSAE: EVEXll := 1;
  3668. OTVE_VECTOR_RUSAE: EVEXll := 2;
  3669. OTVE_VECTOR_RZSAE: EVEXll := 3;
  3670. else EVEXll := 0;
  3671. end;
  3672. end;
  3673. end;
  3674. bytes[0] := $62;
  3675. bytes[1] := ((EVEXmm and $03) shl 0) or
  3676. {$ifdef x86_64}
  3677. ((not(rex) and $05) shl 5) or
  3678. {$else}
  3679. (($05) shl 5) or
  3680. {$endif x86_64}
  3681. ((EVEXr and $01) shl 4) or
  3682. ((EVEXx and $01) shl 6);
  3683. bytes[2] := ((EVEXpp and $03) shl 0) or
  3684. ((1 and $01) shl 2) or // fixed in AVX512
  3685. ((EVEXvvvv and $0F) shl 3) or
  3686. ((EVEXw1 and $01) shl 7);
  3687. bytes[3] := ((EVEXaaa and $07) shl 0) or
  3688. ((EVEXv and $01) shl 3) or
  3689. ((EVEXb and $01) shl 4) or
  3690. ((EVEXll and $03) shl 5) or
  3691. ((EVEXz and $01) shl 7);
  3692. objdata.writebytes(bytes,4);
  3693. end
  3694. else if needed_VEX_Extension then
  3695. begin
  3696. // VEX-Prefix-Length = 3 Bytes
  3697. {$ifdef x86_64}
  3698. VEXmmmmm := VEXmmmmm or ((not(rex) and $07) shl 5); // set REX.rxb
  3699. VEXvvvv := VEXvvvv or ((rex and $08) shl 7); // set REX.w
  3700. {$else}
  3701. VEXmmmmm := VEXmmmmm or (7 shl 5); //
  3702. {$endif x86_64}
  3703. bytes[0]:=$C4;
  3704. bytes[1]:=VEXmmmmm;
  3705. bytes[2]:=VEXvvvv;
  3706. objdata.writebytes(bytes,3);
  3707. end
  3708. else
  3709. begin
  3710. // VEX-Prefix-Length = 2 Bytes
  3711. {$ifdef x86_64}
  3712. if rex and $04 = 0 then
  3713. {$endif x86_64}
  3714. begin
  3715. VEXvvvv := VEXvvvv or (1 shl 7);
  3716. end;
  3717. bytes[0]:=$C5;
  3718. bytes[1]:=VEXvvvv;
  3719. objdata.writebytes(bytes,2);
  3720. end;
  3721. end
  3722. else
  3723. begin
  3724. needed_VEX_Extension := false;
  3725. opmode := -1;
  3726. end;
  3727. if not(needed_EVEX) then
  3728. begin
  3729. for opidx := 0 to ops - 1 do
  3730. begin
  3731. if ops > opidx then
  3732. if (oper[opidx]^.typ=top_reg) and
  3733. (getregtype(oper[opidx]^.reg) = R_MMREGISTER) then
  3734. if getsupreg(oper[opidx]^.reg) and $10 = $10 then
  3735. begin
  3736. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  3737. break;
  3738. end;
  3739. //badreg(oper[opidx]^.reg);
  3740. end;
  3741. end;
  3742. { load data to write }
  3743. codes:=insentry^.code;
  3744. repeat
  3745. c:=ord(codes^);
  3746. inc(codes);
  3747. case c of
  3748. &0 :
  3749. break;
  3750. &1,&2,&3 :
  3751. begin
  3752. {$ifdef x86_64}
  3753. if not(needed_VEX or needed_EVEX) then // TG
  3754. maybewriterex;
  3755. {$endif x86_64}
  3756. objdata.writebytes(codes^,c);
  3757. inc(codes,c);
  3758. end;
  3759. &4,&6 :
  3760. begin
  3761. case oper[0]^.reg of
  3762. NR_CS:
  3763. bytes[0]:=$e;
  3764. NR_NO,
  3765. NR_DS:
  3766. bytes[0]:=$1e;
  3767. NR_ES:
  3768. bytes[0]:=$6;
  3769. NR_SS:
  3770. bytes[0]:=$16;
  3771. else
  3772. internalerror(777004);
  3773. end;
  3774. if c=&4 then
  3775. inc(bytes[0]);
  3776. objdata.writebytes(bytes,1);
  3777. end;
  3778. &5,&7 :
  3779. begin
  3780. case oper[0]^.reg of
  3781. NR_FS:
  3782. bytes[0]:=$a0;
  3783. NR_GS:
  3784. bytes[0]:=$a8;
  3785. else
  3786. internalerror(777005);
  3787. end;
  3788. if c=&5 then
  3789. inc(bytes[0]);
  3790. objdata.writebytes(bytes,1);
  3791. end;
  3792. &10,&11,&12 :
  3793. begin
  3794. {$ifdef x86_64}
  3795. if not(needed_VEX or needed_EVEX) then // TG
  3796. maybewriterex;
  3797. {$endif x86_64}
  3798. bytes[0]:=ord(codes^)+regval(oper[c-&10]^.reg);
  3799. inc(codes);
  3800. objdata.writebytes(bytes,1);
  3801. end;
  3802. &13 :
  3803. begin
  3804. bytes[0]:=ord(codes^)+condval[condition];
  3805. inc(codes);
  3806. objdata.writebytes(bytes,1);
  3807. end;
  3808. &14,&15,&16 :
  3809. begin
  3810. getvalsym(c-&14);
  3811. if (currval<-128) or (currval>127) then
  3812. Message2(asmw_e_value_exceeds_bounds,'signed byte',tostr(currval));
  3813. if assigned(currsym) then
  3814. objdata_writereloc(currval,1,currsym,currabsreloc)
  3815. else
  3816. objdata.writebytes(currval,1);
  3817. end;
  3818. &20,&21,&22 :
  3819. begin
  3820. getvalsym(c-&20);
  3821. if (currval<-256) or (currval>255) then
  3822. Message2(asmw_e_value_exceeds_bounds,'byte',tostr(currval));
  3823. if assigned(currsym) then
  3824. objdata_writereloc(currval,1,currsym,currabsreloc)
  3825. else
  3826. objdata.writebytes(currval,1);
  3827. end;
  3828. &23 :
  3829. begin
  3830. bytes[0]:=ord(codes^)+condval[inverse_cond(condition)];
  3831. inc(codes);
  3832. objdata.writebytes(bytes,1);
  3833. end;
  3834. &24,&25,&26,&27 :
  3835. begin
  3836. getvalsym(c-&24);
  3837. if IF_IMM3 in insentry^.flags then
  3838. begin
  3839. if (currval<0) or (currval>7) then
  3840. Message2(asmw_e_value_exceeds_bounds,'unsigned triad',tostr(currval));
  3841. end
  3842. else if IF_IMM4 in insentry^.flags then
  3843. begin
  3844. if (currval<0) or (currval>15) then
  3845. Message2(asmw_e_value_exceeds_bounds,'unsigned nibble',tostr(currval));
  3846. end
  3847. else
  3848. if (currval<0) or (currval>255) then
  3849. Message2(asmw_e_value_exceeds_bounds,'unsigned byte',tostr(currval));
  3850. if assigned(currsym) then
  3851. objdata_writereloc(currval,1,currsym,currabsreloc)
  3852. else
  3853. objdata.writebytes(currval,1);
  3854. end;
  3855. &30,&31,&32 : // 030..032
  3856. begin
  3857. getvalsym(c-&30);
  3858. {$ifndef i8086}
  3859. { currval is an aint so this cannot happen on i8086 and causes only a warning }
  3860. if (currval<-65536) or (currval>65535) then
  3861. Message2(asmw_e_value_exceeds_bounds,'word',tostr(currval));
  3862. {$endif i8086}
  3863. if assigned(currsym)
  3864. {$ifdef i8086}
  3865. or (currabsreloc in [RELOC_DGROUP,RELOC_FARDATASEG])
  3866. {$endif i8086}
  3867. then
  3868. objdata_writereloc(currval,2,currsym,currabsreloc)
  3869. else
  3870. objdata.writebytes(currval,2);
  3871. end;
  3872. &34,&35,&36 : // 034..036
  3873. { !!! These are intended (and used in opcode table) to select depending
  3874. on address size, *not* operand size. Works by coincidence only. }
  3875. begin
  3876. getvalsym(c-&34);
  3877. {$ifdef i8086}
  3878. if assigned(currsym) then
  3879. objdata_writereloc(currval,2,currsym,currabsreloc)
  3880. else
  3881. objdata.writebytes(currval,2);
  3882. {$else i8086}
  3883. if opsize=S_Q then
  3884. begin
  3885. if assigned(currsym) then
  3886. objdata_writereloc(currval,8,currsym,currabsreloc)
  3887. else
  3888. objdata.writebytes(currval,8);
  3889. end
  3890. else
  3891. begin
  3892. if assigned(currsym) then
  3893. objdata_writereloc(currval,4,currsym,currabsreloc32)
  3894. else
  3895. objdata.writebytes(currval,4);
  3896. end
  3897. {$endif i8086}
  3898. end;
  3899. &40,&41,&42 : // 040..042
  3900. begin
  3901. getvalsym(c-&40);
  3902. if assigned(currsym)
  3903. {$ifdef i8086}
  3904. or (currabsreloc in [RELOC_DGROUP,RELOC_FARDATASEG])
  3905. {$endif i8086}
  3906. then
  3907. objdata_writereloc(currval,4,currsym,currabsreloc32)
  3908. else
  3909. objdata.writebytes(currval,4);
  3910. end;
  3911. &44,&45,&46 :// 044..046 - select between word/dword/qword depending on
  3912. begin // address size (we support only default address sizes).
  3913. getvalsym(c-&44);
  3914. {$if defined(x86_64)}
  3915. if assigned(currsym) then
  3916. objdata_writereloc(currval,8,currsym,currabsreloc)
  3917. else
  3918. objdata.writebytes(currval,8);
  3919. {$elseif defined(i386)}
  3920. if assigned(currsym) then
  3921. objdata_writereloc(currval,4,currsym,currabsreloc32)
  3922. else
  3923. objdata.writebytes(currval,4);
  3924. {$elseif defined(i8086)}
  3925. if assigned(currsym) then
  3926. objdata_writereloc(currval,2,currsym,currabsreloc)
  3927. else
  3928. objdata.writebytes(currval,2);
  3929. {$endif}
  3930. end;
  3931. &50,&51,&52 : // 050..052 - byte relative operand
  3932. begin
  3933. getvalsym(c-&50);
  3934. data:=currval-insend;
  3935. {$push}
  3936. {$r-,q-} { disable also overflow as address returns a qword for x86_64 }
  3937. if assigned(currsym) then
  3938. inc(data,currsym.address);
  3939. {$pop}
  3940. if (data>127) or (data<-128) then
  3941. Message1(asmw_e_short_jmp_out_of_range,tostr(data));
  3942. objdata.writebytes(data,1);
  3943. end;
  3944. &54,&55,&56: // 054..056 - qword immediate operand
  3945. begin
  3946. getvalsym(c-&54);
  3947. if assigned(currsym) then
  3948. objdata_writereloc(currval,8,currsym,currabsreloc)
  3949. else
  3950. objdata.writebytes(currval,8);
  3951. end;
  3952. &60,&61,&62 :
  3953. begin
  3954. getvalsym(c-&60);
  3955. {$ifdef i8086}
  3956. if assigned(currsym) then
  3957. objdata_writereloc(currval,2,currsym,currrelreloc)
  3958. else
  3959. objdata_writereloc(currval-insend,2,nil,currabsreloc)
  3960. {$else i8086}
  3961. InternalError(2020100821);
  3962. {$endif i8086}
  3963. end;
  3964. &64,&65,&66 : // 064..066 - select between 16/32 address mode, but we support only 32 (only 16 on i8086)
  3965. begin
  3966. getvalsym(c-&64);
  3967. {$ifdef i8086}
  3968. if assigned(currsym) then
  3969. objdata_writereloc(currval,2,currsym,currrelreloc)
  3970. else
  3971. objdata_writereloc(currval-insend,2,nil,currabsreloc)
  3972. {$else i8086}
  3973. if assigned(currsym) then
  3974. objdata_writereloc(currval,4,currsym,currrelreloc)
  3975. else
  3976. objdata_writereloc(currval-insend,4,nil,currabsreloc32)
  3977. {$endif i8086}
  3978. end;
  3979. &70,&71,&72 : // 070..072 - long relative operand
  3980. begin
  3981. getvalsym(c-&70);
  3982. if assigned(currsym) then
  3983. objdata_writereloc(currval,4,currsym,currrelreloc)
  3984. else
  3985. objdata_writereloc(currval-insend,4,nil,currabsreloc32)
  3986. end;
  3987. &74,&75,&76 : ; // 074..076 - vex-coded vector operand
  3988. // ignore
  3989. &254,&255,&256 : // 0254..0256 - dword implicitly sign-extended to 64-bit (x86_64 only)
  3990. begin
  3991. getvalsym(c-&254);
  3992. {$ifdef x86_64}
  3993. { for i386 as aint type is longint the
  3994. following test is useless }
  3995. if (currval<low(longint)) or (currval>high(longint)) then
  3996. Message2(asmw_e_value_exceeds_bounds,'signed dword',tostr(currval));
  3997. {$endif x86_64}
  3998. if assigned(currsym) then
  3999. objdata_writereloc(currval,4,currsym,currabsreloc32)
  4000. else
  4001. objdata.writebytes(currval,4);
  4002. end;
  4003. &300,&301,&302:
  4004. begin
  4005. {$if defined(x86_64) or defined(i8086)}
  4006. if (oper[c and 3]^.ot and OT_SIZE_MASK)=OT_BITS32 then
  4007. write0x67prefix(objdata);
  4008. {$endif x86_64 or i8086}
  4009. end;
  4010. &310 : { fixed 16-bit addr }
  4011. {$if defined(x86_64)}
  4012. { every insentry having code 0310 must be marked with NOX86_64 }
  4013. InternalError(2011051302);
  4014. {$elseif defined(i386)}
  4015. write0x67prefix(objdata);
  4016. {$elseif defined(i8086)}
  4017. {nothing};
  4018. {$endif}
  4019. &311 : { fixed 32-bit addr }
  4020. {$if defined(x86_64) or defined(i8086)}
  4021. write0x67prefix(objdata)
  4022. {$endif x86_64 or i8086}
  4023. ;
  4024. &320,&321,&322 :
  4025. begin
  4026. case oper[c-&320]^.ot and OT_SIZE_MASK of
  4027. {$if defined(i386) or defined(x86_64)}
  4028. OT_BITS16 :
  4029. {$elseif defined(i8086)}
  4030. OT_BITS32 :
  4031. {$endif}
  4032. write0x66prefix(objdata);
  4033. {$ifndef x86_64}
  4034. OT_BITS64 :
  4035. Message(asmw_e_64bit_not_supported);
  4036. {$endif x86_64}
  4037. end;
  4038. end;
  4039. &323 : {no action needed};
  4040. &325:
  4041. {$ifdef i8086}
  4042. write0x66prefix(objdata);
  4043. {$else i8086}
  4044. {no action needed};
  4045. {$endif i8086}
  4046. &324,
  4047. &361:
  4048. begin
  4049. {$ifndef i8086}
  4050. if not(needed_VEX or needed_EVEX) then
  4051. write0x66prefix(objdata);
  4052. {$endif not i8086}
  4053. end;
  4054. &326 :
  4055. begin
  4056. {$ifndef x86_64}
  4057. Message(asmw_e_64bit_not_supported);
  4058. {$endif x86_64}
  4059. end;
  4060. &333 :
  4061. begin
  4062. if not(needed_VEX or needed_EVEX) then
  4063. begin
  4064. bytes[0]:=$f3;
  4065. objdata.writebytes(bytes,1);
  4066. end;
  4067. end;
  4068. &334 :
  4069. begin
  4070. if not(needed_VEX or needed_EVEX) then
  4071. begin
  4072. bytes[0]:=$f2;
  4073. objdata.writebytes(bytes,1);
  4074. end;
  4075. end;
  4076. &335:
  4077. ;
  4078. &336: ; // indicates 32-bit scalar vector operand {no action needed}
  4079. &337: ; // indicates 64-bit scalar vector operand {no action needed}
  4080. &312,
  4081. &327,
  4082. &331,&332 :
  4083. begin
  4084. { these are dissambler hints or 32 bit prefixes which
  4085. are not needed }
  4086. end;
  4087. &362..&364: ; // VEX flags =>> nothing todo
  4088. &366, &367:
  4089. begin
  4090. opidx:=c-&364; { 0366->operand 2, 0367->operand 3 }
  4091. if (needed_VEX or needed_EVEX) and
  4092. (ops=4) and
  4093. (oper[opidx]^.typ=top_reg) and
  4094. (
  4095. ((oper[opidx]^.ot and OT_REG_EXTRA_MASK)=otf_reg_xmm) or
  4096. ((oper[opidx]^.ot and OT_REG_EXTRA_MASK)=otf_reg_ymm) or
  4097. ((oper[opidx]^.ot and OT_REG_EXTRA_MASK)=otf_reg_zmm)
  4098. ) then
  4099. begin
  4100. bytes[0] := ((getsupreg(oper[opidx]^.reg) and 15) shl 4);
  4101. objdata.writebytes(bytes,1);
  4102. end
  4103. else
  4104. Internalerror(2014032001);
  4105. end;
  4106. &350..&352: ; // EVEX flags =>> nothing todo
  4107. &370..&372: ; // VEX flags =>> nothing todo
  4108. &37:
  4109. begin
  4110. {$ifdef i8086}
  4111. if assigned(currsym) then
  4112. objdata_writereloc(0,2,currsym,RELOC_SEG)
  4113. else
  4114. InternalError(2015041503);
  4115. {$else i8086}
  4116. InternalError(2020100822);
  4117. {$endif i8086}
  4118. end;
  4119. else
  4120. begin
  4121. { rex should be written at this point }
  4122. {$ifdef x86_64}
  4123. if not(needed_VEX or needed_EVEX) then // TG
  4124. if (rex<>0) and not(rexwritten) then
  4125. internalerror(200603191);
  4126. {$endif x86_64}
  4127. if (c>=&100) and (c<=&227) then // 0100..0227
  4128. begin
  4129. if (c<&177) then // 0177
  4130. begin
  4131. if (oper[c and 7]^.typ=top_reg) then
  4132. rfield:=regval(oper[c and 7]^.reg)
  4133. else
  4134. rfield:=regval(oper[c and 7]^.ref^.base);
  4135. end
  4136. else
  4137. rfield:=c and 7;
  4138. opidx:=(c shr 3) and 7;
  4139. if not process_ea(oper[opidx]^,ea_data,rfield, EVEXTupleState = etsNotTuple) then
  4140. Message(asmw_e_invalid_effective_address);
  4141. pb:=@bytes[0];
  4142. pb^:=ea_data.modrm;
  4143. inc(pb);
  4144. if ea_data.sib_present then
  4145. begin
  4146. pb^:=ea_data.sib;
  4147. inc(pb);
  4148. end;
  4149. s:=pb-@bytes[0];
  4150. objdata.writebytes(bytes,s);
  4151. case ea_data.bytes of
  4152. 0 : ;
  4153. 1 :
  4154. begin
  4155. if (oper[opidx]^.ot and OT_MEMORY)=OT_MEMORY then
  4156. begin
  4157. currsym:=objdata.symbolref(oper[opidx]^.ref^.symbol);
  4158. {$ifdef i386}
  4159. if (oper[opidx]^.ref^.refaddr=addr_pic) and
  4160. (tf_pic_uses_got in target_info.flags) then
  4161. currabsreloc:=RELOC_GOT32
  4162. else
  4163. {$endif i386}
  4164. {$ifdef x86_64}
  4165. if oper[opidx]^.ref^.refaddr=addr_pic then
  4166. currabsreloc:=RELOC_GOTPCREL
  4167. else
  4168. {$endif x86_64}
  4169. currabsreloc:=RELOC_ABSOLUTE;
  4170. objdata_writereloc(oper[opidx]^.ref^.offset,1,currsym,currabsreloc);
  4171. end
  4172. else
  4173. begin
  4174. bytes[0]:=oper[opidx]^.ref^.offset;
  4175. objdata.writebytes(bytes,1);
  4176. end;
  4177. inc(s);
  4178. end;
  4179. 2,4 :
  4180. begin
  4181. currsym:=objdata.symbolref(oper[opidx]^.ref^.symbol);
  4182. currval:=oper[opidx]^.ref^.offset;
  4183. {$ifdef x86_64}
  4184. if oper[opidx]^.ref^.refaddr=addr_pic then
  4185. currabsreloc:=RELOC_GOTPCREL
  4186. else if oper[opidx]^.ref^.refaddr=addr_tlsgd then
  4187. currabsreloc:=RELOC_TLSGD
  4188. else if oper[opidx]^.ref^.refaddr=addr_tpoff then
  4189. currabsreloc:=RELOC_TPOFF
  4190. else
  4191. if oper[opidx]^.ref^.base=NR_RIP then
  4192. begin
  4193. currabsreloc:=RELOC_RELATIVE;
  4194. { Adjust reloc value by number of bytes following the displacement,
  4195. but not if displacement is specified by literal constant }
  4196. if Assigned(currsym) then
  4197. Dec(currval,InsEnd-objdata.CurrObjSec.Size-ea_data.bytes);
  4198. end
  4199. else
  4200. {$endif x86_64}
  4201. {$ifdef i386}
  4202. if (oper[opidx]^.ref^.refaddr=addr_pic) and
  4203. (tf_pic_uses_got in target_info.flags) then
  4204. currabsreloc:=RELOC_GOT32
  4205. else if oper[opidx]^.ref^.refaddr=addr_tlsgd then
  4206. currabsreloc:=RELOC_TLSGD
  4207. else if oper[opidx]^.ref^.refaddr=addr_ntpoff then
  4208. currabsreloc:=RELOC_NTPOFF
  4209. else
  4210. {$endif i386}
  4211. {$ifdef i8086}
  4212. if ea_data.bytes=2 then
  4213. currabsreloc:=RELOC_ABSOLUTE
  4214. else
  4215. {$endif i8086}
  4216. currabsreloc:=RELOC_ABSOLUTE32;
  4217. if (currabsreloc in [RELOC_ABSOLUTE32{$ifdef i8086},RELOC_ABSOLUTE{$endif}]) and
  4218. (Assigned(oper[opidx]^.ref^.relsymbol)) then
  4219. begin
  4220. relsym:=objdata.symbolref(oper[opidx]^.ref^.relsymbol);
  4221. if relsym.objsection=objdata.CurrObjSec then
  4222. begin
  4223. currval:=objdata.CurrObjSec.size+ea_data.bytes-relsym.offset+currval;
  4224. {$ifdef i8086}
  4225. if ea_data.bytes=4 then
  4226. currabsreloc:=RELOC_RELATIVE32
  4227. else
  4228. {$endif i8086}
  4229. currabsreloc:=RELOC_RELATIVE;
  4230. end
  4231. else
  4232. begin
  4233. currabsreloc:=RELOC_PIC_PAIR;
  4234. currval:=relsym.offset;
  4235. end;
  4236. end;
  4237. objdata_writereloc(currval,ea_data.bytes,currsym,currabsreloc);
  4238. inc(s,ea_data.bytes);
  4239. end;
  4240. end;
  4241. end
  4242. else
  4243. InternalError(777007);
  4244. end;
  4245. end;
  4246. until false;
  4247. end;
  4248. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  4249. begin
  4250. result:=(((opcode=A_MOV) or (opcode=A_XCHG)) and
  4251. (regtype = R_INTREGISTER) and
  4252. (ops=2) and
  4253. (oper[0]^.typ=top_reg) and
  4254. (oper[1]^.typ=top_reg) and
  4255. (oper[0]^.reg=oper[1]^.reg)
  4256. ) or
  4257. ({ checking the opcodes is a long "or" chain, so check first the registers which is more selective }
  4258. ((regtype = R_MMREGISTER) and
  4259. (ops=2) and
  4260. (oper[0]^.typ=top_reg) and
  4261. (oper[1]^.typ=top_reg) and
  4262. (oper[0]^.reg=oper[1]^.reg)) and
  4263. (
  4264. (opcode=A_MOVSS) or (opcode=A_MOVSD) or
  4265. (opcode=A_MOVQ) or (opcode=A_MOVD) or
  4266. (opcode=A_MOVAPS) or (opcode=A_MOVAPD) or
  4267. (opcode=A_MOVUPS) or (opcode=A_MOVUPD) or
  4268. (opcode=A_MOVDQA) or (opcode=A_MOVDQU) or
  4269. (opcode=A_VMOVSS) or (opcode=A_VMOVSD) or
  4270. (opcode=A_VMOVQ) or (opcode=A_VMOVD) or
  4271. (opcode=A_VMOVAPS) or (opcode=A_VMOVAPD) or
  4272. (opcode=A_VMOVUPS) or (opcode=A_VMOVUPD) or
  4273. (opcode=A_VMOVDQA) or (opcode=A_VMOVDQU)
  4274. )
  4275. );
  4276. end;
  4277. procedure build_spilling_operation_type_table;
  4278. var
  4279. opcode : tasmop;
  4280. begin
  4281. new(operation_type_table);
  4282. fillchar(operation_type_table^,sizeof(toperation_type_table),byte(operand_read));
  4283. for opcode:=low(tasmop) to high(tasmop) do
  4284. with InsProp[opcode] do
  4285. begin
  4286. if Ch_Rop1 in Ch then
  4287. operation_type_table^[opcode,0]:=operand_read;
  4288. if Ch_Wop1 in Ch then
  4289. operation_type_table^[opcode,0]:=operand_write;
  4290. if [Ch_RWop1,Ch_Mop1]*Ch<>[] then
  4291. operation_type_table^[opcode,0]:=operand_readwrite;
  4292. if Ch_Rop2 in Ch then
  4293. operation_type_table^[opcode,1]:=operand_read;
  4294. if Ch_Wop2 in Ch then
  4295. operation_type_table^[opcode,1]:=operand_write;
  4296. if [Ch_RWop2,Ch_Mop2]*Ch<>[] then
  4297. operation_type_table^[opcode,1]:=operand_readwrite;
  4298. if Ch_Rop3 in Ch then
  4299. operation_type_table^[opcode,2]:=operand_read;
  4300. if Ch_Wop3 in Ch then
  4301. operation_type_table^[opcode,2]:=operand_write;
  4302. if [Ch_RWop3,Ch_Mop3]*Ch<>[] then
  4303. operation_type_table^[opcode,2]:=operand_readwrite;
  4304. if Ch_Rop4 in Ch then
  4305. operation_type_table^[opcode,3]:=operand_read;
  4306. if Ch_Wop4 in Ch then
  4307. operation_type_table^[opcode,3]:=operand_write;
  4308. if [Ch_RWop4,Ch_Mop4]*Ch<>[] then
  4309. operation_type_table^[opcode,3]:=operand_readwrite;
  4310. end;
  4311. end;
  4312. function taicpu.spilling_get_operation_type(opnr: longint): topertype;
  4313. begin
  4314. { the information in the instruction table is made for the string copy
  4315. operation MOVSD so hack here (FK)
  4316. VMOVSS and VMOVSD has two and three operand flavours, this cannot modelled by x86ins.dat
  4317. so fix it here (FK)
  4318. }
  4319. if ((opcode=A_MOVSD) or (opcode=A_VMOVSS) or (opcode=A_VMOVSD)) and (ops=2) then
  4320. begin
  4321. case opnr of
  4322. 0:
  4323. result:=operand_read;
  4324. 1:
  4325. result:=operand_write;
  4326. else
  4327. internalerror(200506055);
  4328. end
  4329. end
  4330. { IMUL has 1, 2 and 3-operand forms }
  4331. else if opcode=A_IMUL then
  4332. begin
  4333. case ops of
  4334. 1:
  4335. if opnr=0 then
  4336. result:=operand_read
  4337. else
  4338. internalerror(2014011802);
  4339. 2:
  4340. begin
  4341. case opnr of
  4342. 0:
  4343. result:=operand_read;
  4344. 1:
  4345. result:=operand_readwrite;
  4346. else
  4347. internalerror(2014011803);
  4348. end;
  4349. end;
  4350. 3:
  4351. begin
  4352. case opnr of
  4353. 0,1:
  4354. result:=operand_read;
  4355. 2:
  4356. result:=operand_write;
  4357. else
  4358. internalerror(2014011804);
  4359. end;
  4360. end;
  4361. else
  4362. internalerror(2014011805);
  4363. end;
  4364. end
  4365. else
  4366. result:=operation_type_table^[opcode,opnr];
  4367. end;
  4368. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  4369. var
  4370. tmpref: treference;
  4371. begin
  4372. tmpref:=ref;
  4373. {$ifdef i8086}
  4374. if tmpref.segment=NR_SS then
  4375. tmpref.segment:=NR_NO;
  4376. {$endif i8086}
  4377. case getregtype(r) of
  4378. R_INTREGISTER :
  4379. begin
  4380. if getsubreg(r)=R_SUBH then
  4381. inc(tmpref.offset);
  4382. { we don't need special code here for 32 bit loads on x86_64, since
  4383. those will automatically zero-extend the upper 32 bits. }
  4384. result:=taicpu.op_ref_reg(A_MOV,reg2opsize(r),tmpref,r);
  4385. end;
  4386. R_MMREGISTER :
  4387. if current_settings.fputype in fpu_avx_instructionsets then
  4388. case getsubreg(r) of
  4389. R_SUBMMD:
  4390. result:=taicpu.op_ref_reg(A_VMOVSD,S_NO,tmpref,r);
  4391. R_SUBMMS:
  4392. result:=taicpu.op_ref_reg(A_VMOVSS,S_NO,tmpref,r);
  4393. R_SUBQ,
  4394. R_SUBMMWHOLE:
  4395. result:=taicpu.op_ref_reg(A_VMOVQ,S_NO,tmpref,r);
  4396. R_SUBMMY:
  4397. if ref.alignment>=32 then
  4398. result:=taicpu.op_ref_reg(A_VMOVDQA,S_NO,tmpref,r)
  4399. else
  4400. result:=taicpu.op_ref_reg(A_VMOVDQU,S_NO,tmpref,r);
  4401. R_SUBMMZ:
  4402. if ref.alignment>=64 then
  4403. result:=taicpu.op_ref_reg(A_VMOVDQA64,S_NO,tmpref,r)
  4404. else
  4405. result:=taicpu.op_ref_reg(A_VMOVDQU64,S_NO,tmpref,r);
  4406. R_SUBMMX:
  4407. result:=taicpu.op_ref_reg(A_VMOVDQU,S_NO,tmpref,r);
  4408. else
  4409. internalerror(200506043);
  4410. end
  4411. else
  4412. case getsubreg(r) of
  4413. R_SUBMMD:
  4414. result:=taicpu.op_ref_reg(A_MOVSD,S_NO,tmpref,r);
  4415. R_SUBMMS:
  4416. result:=taicpu.op_ref_reg(A_MOVSS,S_NO,tmpref,r);
  4417. R_SUBQ,
  4418. R_SUBMMWHOLE:
  4419. result:=taicpu.op_ref_reg(A_MOVQ,S_NO,tmpref,r);
  4420. R_SUBMMX:
  4421. result:=taicpu.op_ref_reg(A_MOVDQA,S_NO,tmpref,r);
  4422. else
  4423. internalerror(2005060405);
  4424. end;
  4425. else
  4426. internalerror(2004010411);
  4427. end;
  4428. end;
  4429. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  4430. var
  4431. size: topsize;
  4432. tmpref: treference;
  4433. begin
  4434. tmpref:=ref;
  4435. {$ifdef i8086}
  4436. if tmpref.segment=NR_SS then
  4437. tmpref.segment:=NR_NO;
  4438. {$endif i8086}
  4439. case getregtype(r) of
  4440. R_INTREGISTER :
  4441. begin
  4442. if getsubreg(r)=R_SUBH then
  4443. inc(tmpref.offset);
  4444. size:=reg2opsize(r);
  4445. {$ifdef x86_64}
  4446. { even if it's a 32 bit reg, we still have to spill 64 bits
  4447. because we often perform 64 bit operations on them }
  4448. if (size=S_L) then
  4449. begin
  4450. size:=S_Q;
  4451. r:=newreg(getregtype(r),getsupreg(r),R_SUBWHOLE);
  4452. end;
  4453. {$endif x86_64}
  4454. result:=taicpu.op_reg_ref(A_MOV,size,r,tmpref);
  4455. end;
  4456. R_MMREGISTER :
  4457. if current_settings.fputype in fpu_avx_instructionsets then
  4458. case getsubreg(r) of
  4459. R_SUBMMD:
  4460. result:=taicpu.op_reg_ref(A_VMOVSD,S_NO,r,tmpref);
  4461. R_SUBMMS:
  4462. result:=taicpu.op_reg_ref(A_VMOVSS,S_NO,r,tmpref);
  4463. R_SUBMMY:
  4464. if ref.alignment>=32 then
  4465. result:=taicpu.op_reg_ref(A_VMOVDQA,S_NO,r,tmpref)
  4466. else
  4467. result:=taicpu.op_reg_ref(A_VMOVDQU,S_NO,r,tmpref);
  4468. R_SUBMMZ:
  4469. if ref.alignment>=64 then
  4470. result:=taicpu.op_reg_ref(A_VMOVDQA64,S_NO,r,tmpref)
  4471. else
  4472. result:=taicpu.op_reg_ref(A_VMOVDQU64,S_NO,r,tmpref);
  4473. R_SUBQ,
  4474. R_SUBMMWHOLE:
  4475. result:=taicpu.op_reg_ref(A_VMOVQ,S_NO,r,tmpref);
  4476. else
  4477. internalerror(200506042);
  4478. end
  4479. else
  4480. case getsubreg(r) of
  4481. R_SUBMMD:
  4482. result:=taicpu.op_reg_ref(A_MOVSD,S_NO,r,tmpref);
  4483. R_SUBMMS:
  4484. result:=taicpu.op_reg_ref(A_MOVSS,S_NO,r,tmpref);
  4485. R_SUBQ,
  4486. R_SUBMMWHOLE:
  4487. result:=taicpu.op_reg_ref(A_MOVQ,S_NO,r,tmpref);
  4488. else
  4489. internalerror(2005060404);
  4490. end;
  4491. else
  4492. internalerror(2004010412);
  4493. end;
  4494. end;
  4495. {$ifdef i8086}
  4496. procedure taicpu.loadsegsymbol(opidx:longint;s:tasmsymbol);
  4497. var
  4498. r: treference;
  4499. begin
  4500. reference_reset_symbol(r,s,0,1,[]);
  4501. r.refaddr:=addr_seg;
  4502. loadref(opidx,r);
  4503. end;
  4504. {$endif i8086}
  4505. {*****************************************************************************
  4506. Instruction table
  4507. *****************************************************************************}
  4508. procedure BuildInsTabCache;
  4509. var
  4510. i : longint;
  4511. begin
  4512. new(instabcache);
  4513. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  4514. i:=0;
  4515. while (i<InsTabEntries) do
  4516. begin
  4517. if InsTabCache^[InsTab[i].OPcode]=-1 then
  4518. InsTabCache^[InsTab[i].OPcode]:=i;
  4519. inc(i);
  4520. end;
  4521. end;
  4522. procedure BuildInsTabMemRefSizeInfoCache;
  4523. var
  4524. AsmOp: TasmOp;
  4525. i,j: longint;
  4526. iCntOpcodeValError: longint;
  4527. insentry : PInsEntry;
  4528. MRefInfo: TMemRefSizeInfo;
  4529. SConstInfo: TConstSizeInfo;
  4530. actRegSize: int64;
  4531. actMemSize: int64;
  4532. actConstSize: int64;
  4533. actRegCount: integer;
  4534. actMemCount: integer;
  4535. actConstCount: integer;
  4536. actRegTypes : int64;
  4537. actRegMemTypes: int64;
  4538. NewRegSize: int64;
  4539. actVMemCount : integer;
  4540. actVMemTypes : int64;
  4541. RegMMXSizeMask: int64;
  4542. RegXMMSizeMask: int64;
  4543. RegYMMSizeMask: int64;
  4544. RegZMMSizeMask: int64;
  4545. RegMMXConstSizeMask: int64;
  4546. RegXMMConstSizeMask: int64;
  4547. RegYMMConstSizeMask: int64;
  4548. RegZMMConstSizeMask: int64;
  4549. RegBCSTSizeMask: int64;
  4550. RegBCSTXMMSizeMask: int64;
  4551. RegBCSTYMMSizeMask: int64;
  4552. RegBCSTZMMSizeMask: int64;
  4553. ExistsMemRef : boolean;
  4554. bitcount : integer;
  4555. ExistsCode336 : boolean;
  4556. ExistsCode337 : boolean;
  4557. ExistsSSEAVXReg : boolean;
  4558. hs1,hs2 : String;
  4559. function bitcnt(aValue: int64): integer;
  4560. var
  4561. i: integer;
  4562. begin
  4563. result := 0;
  4564. for i := 0 to 63 do
  4565. begin
  4566. if (aValue mod 2) = 1 then
  4567. begin
  4568. inc(result);
  4569. end;
  4570. aValue := aValue shr 1;
  4571. end;
  4572. end;
  4573. begin
  4574. new(InsTabMemRefSizeInfoCache);
  4575. FillChar(InsTabMemRefSizeInfoCache^,sizeof(TInsTabMemRefSizeInfoCache),0);
  4576. iCntOpcodeValError := 0;
  4577. for AsmOp := low(TAsmOp) to high(TAsmOp) do
  4578. begin
  4579. i := InsTabCache^[AsmOp];
  4580. if i >= 0 then
  4581. begin
  4582. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnknown;
  4583. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbUnknown;
  4584. InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 0;
  4585. InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnknown;
  4586. InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := false;
  4587. InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := [];
  4588. insentry:=@instab[i];
  4589. RegMMXSizeMask := 0;
  4590. RegXMMSizeMask := 0;
  4591. RegYMMSizeMask := 0;
  4592. RegZMMSizeMask := 0;
  4593. RegMMXConstSizeMask := 0;
  4594. RegXMMConstSizeMask := 0;
  4595. RegYMMConstSizeMask := 0;
  4596. RegZMMConstSizeMask := 0;
  4597. RegBCSTSizeMask:= 0;
  4598. RegBCSTXMMSizeMask := 0;
  4599. RegBCSTYMMSizeMask := 0;
  4600. RegBCSTZMMSizeMask := 0;
  4601. ExistsMemRef := false;
  4602. while (insentry^.opcode=AsmOp) do
  4603. begin
  4604. MRefInfo := msiUnknown;
  4605. actRegSize := 0;
  4606. actRegCount := 0;
  4607. actRegTypes := 0;
  4608. NewRegSize := 0;
  4609. actMemSize := 0;
  4610. actMemCount := 0;
  4611. actRegMemTypes := 0;
  4612. actVMemCount := 0;
  4613. actVMemTypes := 0;
  4614. actConstSize := 0;
  4615. actConstCount := 0;
  4616. ExistsCode336 := false; // indicate fixed operand size 32 bit
  4617. ExistsCode337 := false; // indicate fixed operand size 64 bit
  4618. ExistsSSEAVXReg := false;
  4619. // parse insentry^.code for &336 and &337
  4620. // &336 (octal) = 222 (decimal) == fixed operand size 32 bit
  4621. // &337 (octal) = 223 (decimal) == fixed operand size 64 bit
  4622. for i := low(insentry^.code) to high(insentry^.code) do
  4623. begin
  4624. case insentry^.code[i] of
  4625. #222: ExistsCode336 := true;
  4626. #223: ExistsCode337 := true;
  4627. #0,#1,#2,#3: break;
  4628. end;
  4629. end;
  4630. for i := 0 to insentry^.ops -1 do
  4631. begin
  4632. if (insentry^.optypes[i] and OT_REGISTER) = OT_REGISTER then
  4633. case insentry^.optypes[i] and (OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK) of
  4634. OT_XMMREG,
  4635. OT_YMMREG,
  4636. OT_ZMMREG: ExistsSSEAVXReg := true;
  4637. else;
  4638. end;
  4639. end;
  4640. for j := 0 to insentry^.ops -1 do
  4641. begin
  4642. if ((insentry^.optypes[j] and OT_XMEM32) = OT_XMEM32) OR
  4643. ((insentry^.optypes[j] and OT_XMEM64) = OT_XMEM64) OR
  4644. ((insentry^.optypes[j] and OT_YMEM32) = OT_YMEM32) OR
  4645. ((insentry^.optypes[j] and OT_YMEM64) = OT_YMEM64) OR
  4646. ((insentry^.optypes[j] and OT_ZMEM32) = OT_ZMEM32) OR
  4647. ((insentry^.optypes[j] and OT_ZMEM64) = OT_ZMEM64) then
  4648. begin
  4649. inc(actVMemCount);
  4650. case insentry^.optypes[j] and (OT_XMEM32 OR OT_XMEM64 OR OT_YMEM32 OR OT_YMEM64 OR OT_ZMEM32 OR OT_ZMEM64) of
  4651. OT_XMEM32: actVMemTypes := actVMemTypes or OT_XMEM32;
  4652. OT_XMEM64: actVMemTypes := actVMemTypes or OT_XMEM64;
  4653. OT_YMEM32: actVMemTypes := actVMemTypes or OT_YMEM32;
  4654. OT_YMEM64: actVMemTypes := actVMemTypes or OT_YMEM64;
  4655. OT_ZMEM32: actVMemTypes := actVMemTypes or OT_ZMEM32;
  4656. OT_ZMEM64: actVMemTypes := actVMemTypes or OT_ZMEM64;
  4657. else InternalError(777206);
  4658. end;
  4659. end
  4660. else if (insentry^.optypes[j] and OT_REGISTER) = OT_REGISTER then
  4661. begin
  4662. inc(actRegCount);
  4663. NewRegSize := (insentry^.optypes[j] and OT_SIZE_MASK);
  4664. if NewRegSize = 0 then
  4665. begin
  4666. case insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK) of
  4667. OT_MMXREG: begin
  4668. NewRegSize := OT_BITS64;
  4669. end;
  4670. OT_XMMREG: begin
  4671. NewRegSize := OT_BITS128;
  4672. InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true;
  4673. end;
  4674. OT_YMMREG: begin
  4675. NewRegSize := OT_BITS256;
  4676. InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true;
  4677. end;
  4678. OT_ZMMREG: begin
  4679. NewRegSize := OT_BITS512;
  4680. InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true;
  4681. end;
  4682. OT_KREG: begin
  4683. InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX := true;
  4684. end;
  4685. else NewRegSize := not(0);
  4686. end;
  4687. end;
  4688. actRegSize := actRegSize or NewRegSize;
  4689. actRegTypes := actRegTypes or (insentry^.optypes[j] and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_KREG or OT_REG_EXTRA_MASK));
  4690. end
  4691. else if ((insentry^.optypes[j] and OT_MEMORY) <> 0) then
  4692. begin
  4693. inc(actMemCount);
  4694. if ExistsSSEAVXReg and ExistsCode336 then
  4695. actMemSize := actMemSize or OT_BITS32
  4696. else if ExistsSSEAVXReg and ExistsCode337 then
  4697. actMemSize := actMemSize or OT_BITS64
  4698. else
  4699. actMemSize:=actMemSize or (insentry^.optypes[j] and (OT_SIZE_MASK OR OT_VECTORBCST));
  4700. if (insentry^.optypes[j] and OT_REGMEM) = OT_REGMEM then
  4701. begin
  4702. actRegMemTypes := actRegMemTypes or insentry^.optypes[j];
  4703. end;
  4704. end
  4705. else if ((insentry^.optypes[j] and OT_IMMEDIATE) = OT_IMMEDIATE) then
  4706. begin
  4707. inc(actConstCount);
  4708. actConstSize := actConstSize or (insentry^.optypes[j] and OT_SIZE_MASK);
  4709. end
  4710. end;
  4711. if actConstCount > 0 then
  4712. begin
  4713. case actConstSize of
  4714. 0: SConstInfo := csiNoSize;
  4715. OT_BITS8: SConstInfo := csiMem8;
  4716. OT_BITS16: SConstInfo := csiMem16;
  4717. OT_BITS32: SConstInfo := csiMem32;
  4718. OT_BITS64: SConstInfo := csiMem64;
  4719. else SConstInfo := csiMultiple;
  4720. end;
  4721. if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize = csiUnknown then
  4722. begin
  4723. InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := SConstInfo;
  4724. end
  4725. else if InsTabMemRefSizeInfoCache^[AsmOp].ConstSize <> SConstInfo then
  4726. begin
  4727. InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiMultiple;
  4728. end;
  4729. end;
  4730. if actVMemCount > 0 then
  4731. begin
  4732. if actVMemCount = 1 then
  4733. begin
  4734. if actVMemTypes > 0 then
  4735. begin
  4736. case actVMemTypes of
  4737. OT_XMEM32: MRefInfo := msiXMem32;
  4738. OT_XMEM64: MRefInfo := msiXMem64;
  4739. OT_YMEM32: MRefInfo := msiYMem32;
  4740. OT_YMEM64: MRefInfo := msiYMem64;
  4741. OT_ZMEM32: MRefInfo := msiZMem32;
  4742. OT_ZMEM64: MRefInfo := msiZMem64;
  4743. else InternalError(777208);
  4744. end;
  4745. case actRegTypes of
  4746. OT_XMMREG: case MRefInfo of
  4747. msiXMem32,
  4748. msiXMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS128;
  4749. msiYMem32,
  4750. msiYMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS256;
  4751. msiZMem32,
  4752. msiZMem64: RegXMMSizeMask := RegXMMSizeMask or OT_BITS512;
  4753. else InternalError(777210);
  4754. end;
  4755. OT_YMMREG: case MRefInfo of
  4756. msiXMem32,
  4757. msiXMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS128;
  4758. msiYMem32,
  4759. msiYMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS256;
  4760. msiZMem32,
  4761. msiZMem64: RegYMMSizeMask := RegYMMSizeMask or OT_BITS512;
  4762. else InternalError(2020100823);
  4763. end;
  4764. OT_ZMMREG: case MRefInfo of
  4765. msiXMem32,
  4766. msiXMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS128;
  4767. msiYMem32,
  4768. msiYMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS256;
  4769. msiZMem32,
  4770. msiZMem64: RegZMMSizeMask := RegZMMSizeMask or OT_BITS512;
  4771. else InternalError(2020100824);
  4772. end;
  4773. //else InternalError(777209);
  4774. end;
  4775. if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown then
  4776. begin
  4777. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo;
  4778. end
  4779. else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then
  4780. begin
  4781. if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in [msiXMem32, msiXMem64, msiYMem32, msiYMem64, msiZMem32, msiZMem64] then
  4782. begin
  4783. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemMultiple;
  4784. end
  4785. else if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> msiVMemMultiple then InternalError(777212);
  4786. end;
  4787. end;
  4788. end
  4789. else InternalError(777207);
  4790. end
  4791. else
  4792. begin
  4793. if (actMemCount=2) and ((AsmOp=A_MOVS) or (AsmOp=A_CMPS)) then actMemCount:=1;
  4794. ExistsMemRef := ExistsMemRef or (actMemCount > 0);
  4795. case actMemCount of
  4796. 0: ; // nothing todo
  4797. 1: begin
  4798. MRefInfo := msiUnknown;
  4799. if not(ExistsCode336 or ExistsCode337) then
  4800. case actRegMemTypes and (OT_MMXRM or OT_XMMRM or OT_YMMRM or OT_ZMMRM or OT_REG_EXTRA_MASK) of
  4801. OT_MMXRM: actMemSize := actMemSize or OT_BITS64;
  4802. OT_XMMRM: actMemSize := actMemSize or OT_BITS128;
  4803. OT_YMMRM: actMemSize := actMemSize or OT_BITS256;
  4804. OT_ZMMRM: actMemSize := actMemSize or OT_BITS512;
  4805. end;
  4806. case actMemSize of
  4807. 0: MRefInfo := msiNoSize;
  4808. OT_BITS8: MRefInfo := msiMem8;
  4809. OT_BITS16: MRefInfo := msiMem16;
  4810. OT_BITS32: MRefInfo := msiMem32;
  4811. OT_BITSB32: MRefInfo := msiBMem32;
  4812. OT_BITS64: MRefInfo := msiMem64;
  4813. OT_BITSB64: MRefInfo := msiBMem64;
  4814. OT_BITS128: MRefInfo := msiMem128;
  4815. OT_BITS256: MRefInfo := msiMem256;
  4816. OT_BITS512: MRefInfo := msiMem512;
  4817. OT_BITS80,
  4818. OT_FAR,
  4819. OT_NEAR,
  4820. OT_SHORT: ; // ignore
  4821. else
  4822. begin
  4823. bitcount := bitcnt(actMemSize);
  4824. if bitcount > 1 then MRefInfo := msiMultiple
  4825. else InternalError(777203);
  4826. end;
  4827. end;
  4828. if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown then
  4829. begin
  4830. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := MRefInfo;
  4831. end
  4832. else
  4833. begin
  4834. // ignore broadcast-memory
  4835. if not(MRefInfo in [msiBMem32, msiBMem64]) then
  4836. begin
  4837. if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize <> MRefInfo then
  4838. begin
  4839. with InsTabMemRefSizeInfoCache^[AsmOp] do
  4840. begin
  4841. if ((MemRefSize in [msiMem8, msiMULTIPLEMinSize8]) OR (MRefInfo = msiMem8)) then MemRefSize := msiMultipleMinSize8
  4842. else if ((MemRefSize in [ msiMem16, msiMULTIPLEMinSize16]) OR (MRefInfo = msiMem16)) then MemRefSize := msiMultipleMinSize16
  4843. else if ((MemRefSize in [ msiMem32, msiMULTIPLEMinSize32]) OR (MRefInfo = msiMem32)) then MemRefSize := msiMultipleMinSize32
  4844. else if ((MemRefSize in [ msiMem64, msiMULTIPLEMinSize64]) OR (MRefInfo = msiMem64)) then MemRefSize := msiMultipleMinSize64
  4845. else if ((MemRefSize in [msiMem128, msiMULTIPLEMinSize128]) OR (MRefInfo = msiMem128)) then MemRefSize := msiMultipleMinSize128
  4846. else if ((MemRefSize in [msiMem256, msiMULTIPLEMinSize256]) OR (MRefInfo = msiMem256)) then MemRefSize := msiMultipleMinSize256
  4847. else if ((MemRefSize in [msiMem512, msiMULTIPLEMinSize512]) OR (MRefInfo = msiMem512)) then MemRefSize := msiMultipleMinSize512
  4848. else MemRefSize := msiMultiple;
  4849. end;
  4850. end;
  4851. end;
  4852. end;
  4853. //if not(MRefInfo in [msiBMem32, msiBMem64]) and (actRegCount > 0) then
  4854. if actRegCount > 0 then
  4855. begin
  4856. if MRefInfo in [msiBMem32, msiBMem64] then
  4857. begin
  4858. if IF_BCST2 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to2];
  4859. if IF_BCST4 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to4];
  4860. if IF_BCST8 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to8];
  4861. if IF_BCST16 in insentry^.flags then InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes := InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes + [bt1to16];
  4862. //InsTabMemRefSizeInfoCache^[AsmOp].BCSTTypes
  4863. // BROADCAST - OPERAND
  4864. RegBCSTSizeMask := RegBCSTSizeMask or actMemSize;
  4865. case actRegTypes and (OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of
  4866. OT_XMMREG: RegBCSTXMMSizeMask := RegBCSTXMMSizeMask or actMemSize;
  4867. OT_YMMREG: RegBCSTYMMSizeMask := RegBCSTYMMSizeMask or actMemSize;
  4868. OT_ZMMREG: RegBCSTZMMSizeMask := RegBCSTZMMSizeMask or actMemSize;
  4869. else begin
  4870. RegBCSTXMMSizeMask := not(0);
  4871. RegBCSTYMMSizeMask := not(0);
  4872. RegBCSTZMMSizeMask := not(0);
  4873. end;
  4874. end;
  4875. end
  4876. else
  4877. case actRegTypes and (OT_MMXREG or OT_XMMREG or OT_YMMREG or OT_ZMMREG or OT_REG_EXTRA_MASK) of
  4878. OT_MMXREG: if actConstCount > 0 then RegMMXConstSizeMask := RegMMXConstSizeMask or actMemSize
  4879. else RegMMXSizeMask := RegMMXSizeMask or actMemSize;
  4880. OT_XMMREG: if actConstCount > 0 then RegXMMConstSizeMask := RegXMMConstSizeMask or actMemSize
  4881. else RegXMMSizeMask := RegXMMSizeMask or actMemSize;
  4882. OT_YMMREG: if actConstCount > 0 then RegYMMConstSizeMask := RegYMMConstSizeMask or actMemSize
  4883. else RegYMMSizeMask := RegYMMSizeMask or actMemSize;
  4884. OT_ZMMREG: if actConstCount > 0 then RegZMMConstSizeMask := RegZMMConstSizeMask or actMemSize
  4885. else RegZMMSizeMask := RegZMMSizeMask or actMemSize;
  4886. else begin
  4887. RegMMXSizeMask := not(0);
  4888. RegXMMSizeMask := not(0);
  4889. RegYMMSizeMask := not(0);
  4890. RegZMMSizeMask := not(0);
  4891. RegMMXConstSizeMask := not(0);
  4892. RegXMMConstSizeMask := not(0);
  4893. RegYMMConstSizeMask := not(0);
  4894. RegZMMConstSizeMask := not(0);
  4895. end;
  4896. end;
  4897. end
  4898. else
  4899. end
  4900. else InternalError(777202);
  4901. end;
  4902. end;
  4903. inc(insentry);
  4904. end;
  4905. if InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX then
  4906. begin
  4907. case RegBCSTSizeMask of
  4908. 0: ; // ignore;
  4909. OT_BITSB32: begin
  4910. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbBCST32;
  4911. InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 4;
  4912. end;
  4913. OT_BITSB64: begin
  4914. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbBCST64;
  4915. InsTabMemRefSizeInfoCache^[AsmOp].BCSTXMMMultiplicator := 2;
  4916. end;
  4917. else begin
  4918. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSizeBCST := msbMultiple;
  4919. end;
  4920. end;
  4921. end;
  4922. if (InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in MemRefMultiples) and
  4923. (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX)then
  4924. begin
  4925. if InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiVMemMultiple then
  4926. begin
  4927. if ((RegXMMSizeMask = OT_BITS128) or (RegXMMSizeMask = 0)) and
  4928. ((RegYMMSizeMask = OT_BITS256) or (RegYMMSizeMask = 0)) and
  4929. ((RegZMMSizeMask = OT_BITS512) or (RegZMMSizeMask = 0)) and
  4930. ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) <> 0) then
  4931. begin
  4932. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiVMemRegSize;
  4933. end;
  4934. end
  4935. else if (RegMMXSizeMask or RegMMXConstSizeMask) <> 0 then
  4936. begin
  4937. if ((RegMMXSizeMask or RegMMXConstSizeMask) = OT_BITS64) and
  4938. ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS128) and
  4939. ((RegYMMSizeMask or RegYMMConstSizeMask) = 0) and
  4940. ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then
  4941. begin
  4942. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize;
  4943. end;
  4944. end
  4945. else if (((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS128) or ((RegXMMSizeMask or RegXMMConstSizeMask) = 0)) and
  4946. (((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) or ((RegYMMSizeMask or RegYMMConstSizeMask) = 0)) and
  4947. (((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS512) or ((RegZMMSizeMask or RegZMMConstSizeMask) = 0)) and
  4948. (((RegXMMSizeMask or RegXMMConstSizeMask or
  4949. RegYMMSizeMask or RegYMMConstSizeMask or
  4950. RegZMMSizeMask or RegZMMConstSizeMask)) <> 0) then
  4951. begin
  4952. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegSize;
  4953. end
  4954. else if (RegXMMSizeMask or RegXMMConstSizeMask = OT_BITS16) and
  4955. (RegYMMSizeMask or RegYMMConstSizeMask = OT_BITS32) and
  4956. (RegZMMSizeMask or RegZMMConstSizeMask = 0) then
  4957. begin
  4958. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx16y32;
  4959. end
  4960. else if (RegXMMSizeMask or RegXMMConstSizeMask = OT_BITS16) and
  4961. (RegYMMSizeMask or RegYMMConstSizeMask = OT_BITS32) and
  4962. (RegZMMSizeMask or RegZMMConstSizeMask = OT_BITS64) then
  4963. begin
  4964. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx16y32z64;
  4965. end
  4966. else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS32) and
  4967. ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS64) then
  4968. begin
  4969. if ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then
  4970. begin
  4971. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx32y64;
  4972. end
  4973. else if ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS128) then
  4974. begin
  4975. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx32y64z128;
  4976. end;
  4977. end
  4978. else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and
  4979. ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS128) and
  4980. ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then
  4981. begin
  4982. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128;
  4983. end
  4984. else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and
  4985. ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS128) and
  4986. ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS256) then
  4987. begin
  4988. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y128z256;
  4989. end
  4990. else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and
  4991. ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) and
  4992. ((RegZMMSizeMask or RegZMMConstSizeMask) = 0) then
  4993. begin
  4994. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y256;
  4995. end
  4996. else if ((RegXMMSizeMask or RegXMMConstSizeMask) = OT_BITS64) and
  4997. ((RegYMMSizeMask or RegYMMConstSizeMask) = OT_BITS256) and
  4998. ((RegZMMSizeMask or RegZMMConstSizeMask) = OT_BITS512) then
  4999. begin
  5000. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegx64y256z512;
  5001. end
  5002. else if ((RegXMMConstSizeMask = 0) or (RegXMMConstSizeMask = OT_BITS128)) and
  5003. ((RegYMMConstSizeMask = 0) or (RegYMMConstSizeMask = OT_BITS256)) and
  5004. ((RegZMMConstSizeMask = 0) or (RegZMMConstSizeMask = OT_BITS512)) and
  5005. ((RegXMMConstSizeMask or RegYMMConstSizeMask or RegZMMConstSizeMask) <> 0) and
  5006. (
  5007. ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS128) or
  5008. ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS256) or
  5009. ((RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask) = OT_BITS512)
  5010. ) then
  5011. begin
  5012. case RegXMMSizeMask or RegYMMSizeMask or RegZMMSizeMask of
  5013. OT_BITS128: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst128;
  5014. OT_BITS256: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst256;
  5015. OT_BITS512: InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMemRegConst512;
  5016. else InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiMultiple;
  5017. end;
  5018. end
  5019. else
  5020. begin
  5021. if not(
  5022. (AsmOp = A_CVTSI2SS) or
  5023. (AsmOp = A_CVTSI2SD) or
  5024. (AsmOp = A_CVTPD2DQ) or
  5025. (AsmOp = A_VCVTPD2DQ) or
  5026. (AsmOp = A_VCVTPD2PS) or
  5027. (AsmOp = A_VCVTSI2SD) or
  5028. (AsmOp = A_VCVTSI2SS) or
  5029. (AsmOp = A_VCVTTPD2DQ) or
  5030. (AsmOp = A_VCVTPD2UDQ) or
  5031. (AsmOp = A_VCVTQQ2PS) or
  5032. (AsmOp = A_VCVTTPD2UDQ) or
  5033. (AsmOp = A_VCVTUQQ2PS) or
  5034. (AsmOp = A_VCVTUSI2SD) or
  5035. (AsmOp = A_VCVTUSI2SS) or
  5036. // TODO check
  5037. (AsmOp = A_VCMPSS)
  5038. ) then
  5039. InternalError(777205);
  5040. end;
  5041. end
  5042. else if (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) and
  5043. (InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize = msiUnknown) and
  5044. (not(ExistsMemRef)) then
  5045. begin
  5046. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiNoMemRef;
  5047. end;
  5048. InsTabMemRefSizeInfoCache^[AsmOp].RegXMMSizeMask:=RegXMMSizeMask;
  5049. InsTabMemRefSizeInfoCache^[AsmOp].RegYMMSizeMask:=RegYMMSizeMask;
  5050. InsTabMemRefSizeInfoCache^[AsmOp].RegZMMSizeMask:=RegZMMSizeMask;
  5051. if (InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) and
  5052. (gas_needsuffix[AsmOp] <> AttSufNONE) and
  5053. (not(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize in MemRefMultiples)) then
  5054. begin
  5055. // combination (attsuffix <> "AttSufNONE") and (MemRefSize is not in MemRefMultiples) is not supported =>> check opcode-definition in x86ins.dat
  5056. if (AsmOp <> A_CVTSI2SD) and
  5057. (AsmOp <> A_CVTSI2SS) then
  5058. begin
  5059. inc(iCntOpcodeValError);
  5060. Str(gas_needsuffix[AsmOp],hs1);
  5061. Str(InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize,hs2);
  5062. Message3(asmr_e_not_supported_combination_attsuffix_memrefsize_type,
  5063. std_op2str[AsmOp],hs1,hs2);
  5064. end;
  5065. end;
  5066. end;
  5067. end;
  5068. if iCntOpcodeValError > 0 then
  5069. InternalError(2021011201);
  5070. for AsmOp := low(TAsmOp) to high(TAsmOp) do
  5071. begin
  5072. // only supported intructiones with SSE- or AVX-operands
  5073. if not(InsTabMemRefSizeInfoCache^[AsmOp].ExistsSSEAVX) then
  5074. begin
  5075. InsTabMemRefSizeInfoCache^[AsmOp].MemRefSize := msiUnknown;
  5076. InsTabMemRefSizeInfoCache^[AsmOp].ConstSize := csiUnknown;
  5077. end;
  5078. end;
  5079. end;
  5080. procedure InitAsm;
  5081. begin
  5082. build_spilling_operation_type_table;
  5083. if not assigned(instabcache) then
  5084. BuildInsTabCache;
  5085. if not assigned(InsTabMemRefSizeInfoCache) then
  5086. BuildInsTabMemRefSizeInfoCache;
  5087. end;
  5088. procedure DoneAsm;
  5089. begin
  5090. if assigned(operation_type_table) then
  5091. begin
  5092. dispose(operation_type_table);
  5093. operation_type_table:=nil;
  5094. end;
  5095. if assigned(instabcache) then
  5096. begin
  5097. dispose(instabcache);
  5098. instabcache:=nil;
  5099. end;
  5100. if assigned(InsTabMemRefSizeInfoCache) then
  5101. begin
  5102. dispose(InsTabMemRefSizeInfoCache);
  5103. InsTabMemRefSizeInfoCache:=nil;
  5104. end;
  5105. end;
  5106. begin
  5107. cai_align:=tai_align;
  5108. cai_cpu:=taicpu;
  5109. end.