aasmcpu.pas 96 KB

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  1. {
  2. Copyright (c) 2003 by Florian Klaempfl
  3. Contains the assembler object for the ARM
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit aasmcpu;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. globtype,globals,verbose,
  22. aasmbase,aasmtai,aasmdata,aasmsym,
  23. ogbase,
  24. symtype,
  25. cpubase,cpuinfo,cgbase,cgutils;
  26. const
  27. { "mov reg,reg" source operand number }
  28. O_MOV_SOURCE = 1;
  29. { "mov reg,reg" source operand number }
  30. O_MOV_DEST = 0;
  31. { Operand types }
  32. OT_NONE = $00000000;
  33. OT_BITS8 = $00000001; { size, and other attributes, of the operand }
  34. OT_BITS16 = $00000002;
  35. OT_BITS32 = $00000004;
  36. OT_BITS64 = $00000008; { FPU only }
  37. OT_BITS80 = $00000010;
  38. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  39. OT_NEAR = $00000040;
  40. OT_SHORT = $00000080;
  41. OT_BITSTINY = $00000100; { fpu constant }
  42. OT_BITSSHIFTER =
  43. $00000200;
  44. OT_SIZE_MASK = $000003FF; { all the size attributes }
  45. OT_NON_SIZE = longint(not OT_SIZE_MASK);
  46. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  47. OT_TO = $00000200; { operand is followed by a colon }
  48. { reverse effect in FADD, FSUB &c }
  49. OT_COLON = $00000400;
  50. OT_SHIFTEROP = $00000800;
  51. OT_REGISTER = $00001000;
  52. OT_IMMEDIATE = $00002000;
  53. OT_REGLIST = $00008000;
  54. OT_IMM8 = $00002001;
  55. OT_IMM24 = $00002002;
  56. OT_IMM32 = $00002004;
  57. OT_IMM64 = $00002008;
  58. OT_IMM80 = $00002010;
  59. OT_IMMTINY = $00002100;
  60. OT_IMMSHIFTER= $00002200;
  61. OT_IMMEDIATE24 = OT_IMM24;
  62. OT_SHIFTIMM = OT_SHIFTEROP or OT_IMMSHIFTER;
  63. OT_SHIFTIMMEDIATE = OT_SHIFTIMM;
  64. OT_IMMEDIATESHIFTER = OT_IMMSHIFTER;
  65. OT_IMMEDIATEFPU = OT_IMMTINY;
  66. OT_REGMEM = $00200000; { for r/m, ie EA, operands }
  67. OT_REGNORM = $00201000; { 'normal' reg, qualifies as EA }
  68. OT_REG8 = $00201001;
  69. OT_REG16 = $00201002;
  70. OT_REG32 = $00201004;
  71. OT_REG64 = $00201008;
  72. OT_VREG = $00201010; { vector register }
  73. OT_REGF = $00201020; { coproc register }
  74. OT_MEMORY = $00204000; { register number in 'basereg' }
  75. OT_MEM8 = $00204001;
  76. OT_MEM16 = $00204002;
  77. OT_MEM32 = $00204004;
  78. OT_MEM64 = $00204008;
  79. OT_MEM80 = $00204010;
  80. { word/byte load/store }
  81. OT_AM2 = $00010000;
  82. { misc ld/st operations }
  83. OT_AM3 = $00020000;
  84. { multiple ld/st operations }
  85. OT_AM4 = $00040000;
  86. { co proc. ld/st operations }
  87. OT_AM5 = $00080000;
  88. OT_AMMASK = $000f0000;
  89. { IT instruction }
  90. OT_CONDITION = $00100000;
  91. OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
  92. OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
  93. OT_MEMORYAM4 = OT_MEMORY or OT_AM4;
  94. OT_MEMORYAM5 = OT_MEMORY or OT_AM5;
  95. OT_FPUREG = $01000000; { floating point stack registers }
  96. OT_REG_SMASK = $00070000; { special register operands: these may be treated differently }
  97. { a mask for the following }
  98. OT_MEM_OFFS = $00604000; { special type of EA }
  99. { simple [address] offset }
  100. OT_ONENESS = $00800000; { special type of immediate operand }
  101. { so UNITY == IMMEDIATE | ONENESS }
  102. OT_UNITY = $00802000; { for shift/rotate instructions }
  103. instabentries = {$i armnop.inc}
  104. maxinfolen = 5;
  105. IF_NONE = $00000000;
  106. IF_ARMMASK = $000F0000;
  107. IF_ARM7 = $00070000;
  108. IF_FPMASK = $00F00000;
  109. IF_FPA = $00100000;
  110. { if the instruction can change in a second pass }
  111. IF_PASS2 = longint($80000000);
  112. type
  113. TInsTabCache=array[TasmOp] of longint;
  114. PInsTabCache=^TInsTabCache;
  115. tinsentry = record
  116. opcode : tasmop;
  117. ops : byte;
  118. optypes : array[0..3] of longint;
  119. code : array[0..maxinfolen] of char;
  120. flags : longint;
  121. end;
  122. pinsentry=^tinsentry;
  123. const
  124. InsTab : array[0..instabentries-1] of TInsEntry={$i armtab.inc}
  125. var
  126. InsTabCache : PInsTabCache;
  127. type
  128. taicpu = class(tai_cpu_abstract_sym)
  129. oppostfix : TOpPostfix;
  130. wideformat : boolean;
  131. roundingmode : troundingmode;
  132. procedure loadshifterop(opidx:longint;const so:tshifterop);
  133. procedure loadregset(opidx:longint; regsetregtype: tregistertype; regsetsubregtype: tsubregister; const s:tcpuregisterset; ausermode: boolean=false);
  134. procedure loadconditioncode(opidx:longint;const cond:tasmcond);
  135. procedure loadmodeflags(opidx:longint;const flags:tcpumodeflags);
  136. procedure loadspecialreg(opidx:longint;const areg:tregister; const aflags:tspecialregflags);
  137. constructor op_none(op : tasmop);
  138. constructor op_reg(op : tasmop;_op1 : tregister);
  139. constructor op_ref(op : tasmop;const _op1 : treference);
  140. constructor op_const(op : tasmop;_op1 : longint);
  141. constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  142. constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  143. constructor op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  144. constructor op_regset(op:tasmop; regtype: tregistertype; subreg: tsubregister; _op1: tcpuregisterset);
  145. constructor op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
  146. constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  147. constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  148. constructor op_reg_const_const(op : tasmop;_op1 : tregister; _op2,_op3: aint);
  149. constructor op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  150. constructor op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  151. constructor op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  152. constructor op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
  153. { SFM/LFM }
  154. constructor op_reg_const_ref(op : tasmop;_op1 : tregister;_op2 : aint;_op3 : treference);
  155. { ITxxx }
  156. constructor op_cond(op: tasmop; cond: tasmcond);
  157. { CPSxx }
  158. constructor op_modeflags(op: tasmop; flags: tcpumodeflags);
  159. constructor op_modeflags_const(op: tasmop; flags: tcpumodeflags; a: aint);
  160. { MSR }
  161. constructor op_specialreg_reg(op: tasmop; specialreg: tregister; specialregflags: tspecialregflags; _op2: tregister);
  162. { *M*LL }
  163. constructor op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  164. { this is for Jmp instructions }
  165. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  166. constructor op_sym(op : tasmop;_op1 : tasmsymbol);
  167. constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  168. constructor op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  169. constructor op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  170. function is_same_reg_move(regtype: Tregistertype):boolean; override;
  171. function spilling_get_operation_type(opnr: longint): topertype;override;
  172. { assembler }
  173. public
  174. { the next will reset all instructions that can change in pass 2 }
  175. procedure ResetPass1;override;
  176. procedure ResetPass2;override;
  177. function CheckIfValid:boolean;
  178. function GetString:string;
  179. function Pass1(objdata:TObjData):longint;override;
  180. procedure Pass2(objdata:TObjData);override;
  181. protected
  182. procedure ppuloadoper(ppufile:tcompilerppufile;var o:toper);override;
  183. procedure ppuwriteoper(ppufile:tcompilerppufile;const o:toper);override;
  184. procedure ppubuildderefimploper(var o:toper);override;
  185. procedure ppuderefoper(var o:toper);override;
  186. private
  187. { next fields are filled in pass1, so pass2 is faster }
  188. inssize : shortint;
  189. insoffset : longint;
  190. LastInsOffset : longint; { need to be public to be reset }
  191. insentry : PInsEntry;
  192. function InsEnd:longint;
  193. procedure create_ot(objdata:TObjData);
  194. function Matches(p:PInsEntry):longint;
  195. function calcsize(p:PInsEntry):shortint;
  196. procedure gencode(objdata:TObjData);
  197. function NeedAddrPrefix(opidx:byte):boolean;
  198. procedure Swapoperands;
  199. function FindInsentry(objdata:TObjData):boolean;
  200. end;
  201. tai_align = class(tai_align_abstract)
  202. { nothing to add }
  203. end;
  204. tai_thumb_func = class(tai)
  205. constructor create;
  206. end;
  207. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  208. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  209. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  210. function setroundingmode(i : taicpu;rm : troundingmode) : taicpu;
  211. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  212. { inserts pc relative symbols at places where they are reachable
  213. and transforms special instructions to valid instruction encodings }
  214. procedure finalizearmcode(list,listtoinsert : TAsmList);
  215. { inserts .pdata section and dummy function prolog needed for arm-wince exception handling }
  216. procedure InsertPData;
  217. procedure InitAsm;
  218. procedure DoneAsm;
  219. implementation
  220. uses
  221. itcpugas,aoptcpu;
  222. procedure taicpu.loadshifterop(opidx:longint;const so:tshifterop);
  223. begin
  224. allocate_oper(opidx+1);
  225. with oper[opidx]^ do
  226. begin
  227. if typ<>top_shifterop then
  228. begin
  229. clearop(opidx);
  230. new(shifterop);
  231. end;
  232. shifterop^:=so;
  233. typ:=top_shifterop;
  234. if assigned(add_reg_instruction_hook) then
  235. add_reg_instruction_hook(self,shifterop^.rs);
  236. end;
  237. end;
  238. procedure taicpu.loadregset(opidx:longint; regsetregtype: tregistertype; regsetsubregtype: tsubregister; const s:tcpuregisterset; ausermode: boolean);
  239. var
  240. i : byte;
  241. begin
  242. allocate_oper(opidx+1);
  243. with oper[opidx]^ do
  244. begin
  245. if typ<>top_regset then
  246. begin
  247. clearop(opidx);
  248. new(regset);
  249. end;
  250. regset^:=s;
  251. regtyp:=regsetregtype;
  252. subreg:=regsetsubregtype;
  253. usermode:=ausermode;
  254. typ:=top_regset;
  255. case regsetregtype of
  256. R_INTREGISTER:
  257. for i:=RS_R0 to RS_R15 do
  258. begin
  259. if assigned(add_reg_instruction_hook) and (i in regset^) then
  260. add_reg_instruction_hook(self,newreg(R_INTREGISTER,i,regsetsubregtype));
  261. end;
  262. R_MMREGISTER:
  263. { both RS_S0 and RS_D0 range from 0 to 31 }
  264. for i:=RS_D0 to RS_D31 do
  265. begin
  266. if assigned(add_reg_instruction_hook) and (i in regset^) then
  267. add_reg_instruction_hook(self,newreg(R_MMREGISTER,i,regsetsubregtype));
  268. end;
  269. end;
  270. end;
  271. end;
  272. procedure taicpu.loadconditioncode(opidx:longint;const cond:tasmcond);
  273. begin
  274. allocate_oper(opidx+1);
  275. with oper[opidx]^ do
  276. begin
  277. if typ<>top_conditioncode then
  278. clearop(opidx);
  279. cc:=cond;
  280. typ:=top_conditioncode;
  281. end;
  282. end;
  283. procedure taicpu.loadmodeflags(opidx: longint; const flags: tcpumodeflags);
  284. begin
  285. allocate_oper(opidx+1);
  286. with oper[opidx]^ do
  287. begin
  288. if typ<>top_modeflags then
  289. clearop(opidx);
  290. modeflags:=flags;
  291. typ:=top_modeflags;
  292. end;
  293. end;
  294. procedure taicpu.loadspecialreg(opidx: longint; const areg: tregister; const aflags: tspecialregflags);
  295. begin
  296. allocate_oper(opidx+1);
  297. with oper[opidx]^ do
  298. begin
  299. if typ<>top_specialreg then
  300. clearop(opidx);
  301. specialreg:=areg;
  302. specialflags:=aflags;
  303. typ:=top_specialreg;
  304. end;
  305. end;
  306. {*****************************************************************************
  307. taicpu Constructors
  308. *****************************************************************************}
  309. constructor taicpu.op_none(op : tasmop);
  310. begin
  311. inherited create(op);
  312. end;
  313. { for pld }
  314. constructor taicpu.op_ref(op : tasmop;const _op1 : treference);
  315. begin
  316. inherited create(op);
  317. ops:=1;
  318. loadref(0,_op1);
  319. end;
  320. constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
  321. begin
  322. inherited create(op);
  323. ops:=1;
  324. loadreg(0,_op1);
  325. end;
  326. constructor taicpu.op_const(op : tasmop;_op1 : longint);
  327. begin
  328. inherited create(op);
  329. ops:=1;
  330. loadconst(0,aint(_op1));
  331. end;
  332. constructor taicpu.op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  333. begin
  334. inherited create(op);
  335. ops:=2;
  336. loadreg(0,_op1);
  337. loadreg(1,_op2);
  338. end;
  339. constructor taicpu.op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  340. begin
  341. inherited create(op);
  342. ops:=2;
  343. loadreg(0,_op1);
  344. loadconst(1,aint(_op2));
  345. end;
  346. constructor taicpu.op_regset(op: tasmop; regtype: tregistertype; subreg: tsubregister; _op1: tcpuregisterset);
  347. begin
  348. inherited create(op);
  349. ops:=1;
  350. loadregset(0,regtype,subreg,_op1);
  351. end;
  352. constructor taicpu.op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
  353. begin
  354. inherited create(op);
  355. ops:=2;
  356. loadref(0,_op1);
  357. loadregset(1,regtype,subreg,_op2);
  358. end;
  359. constructor taicpu.op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  360. begin
  361. inherited create(op);
  362. ops:=2;
  363. loadreg(0,_op1);
  364. loadref(1,_op2);
  365. end;
  366. constructor taicpu.op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  367. begin
  368. inherited create(op);
  369. ops:=3;
  370. loadreg(0,_op1);
  371. loadreg(1,_op2);
  372. loadreg(2,_op3);
  373. end;
  374. constructor taicpu.op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  375. begin
  376. inherited create(op);
  377. ops:=4;
  378. loadreg(0,_op1);
  379. loadreg(1,_op2);
  380. loadreg(2,_op3);
  381. loadreg(3,_op4);
  382. end;
  383. constructor taicpu.op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  384. begin
  385. inherited create(op);
  386. ops:=3;
  387. loadreg(0,_op1);
  388. loadreg(1,_op2);
  389. loadconst(2,aint(_op3));
  390. end;
  391. constructor taicpu.op_reg_const_const(op : tasmop;_op1 : tregister; _op2,_op3: aint);
  392. begin
  393. inherited create(op);
  394. ops:=3;
  395. loadreg(0,_op1);
  396. loadconst(1,aint(_op2));
  397. loadconst(2,aint(_op3));
  398. end;
  399. constructor taicpu.op_reg_const_ref(op : tasmop;_op1 : tregister;_op2 : aint;_op3 : treference);
  400. begin
  401. inherited create(op);
  402. ops:=3;
  403. loadreg(0,_op1);
  404. loadconst(1,_op2);
  405. loadref(2,_op3);
  406. end;
  407. constructor taicpu.op_cond(op: tasmop; cond: tasmcond);
  408. begin
  409. inherited create(op);
  410. ops:=1;
  411. loadconditioncode(0, cond);
  412. end;
  413. constructor taicpu.op_modeflags(op: tasmop; flags: tcpumodeflags);
  414. begin
  415. inherited create(op);
  416. ops := 1;
  417. loadmodeflags(0,flags);
  418. end;
  419. constructor taicpu.op_modeflags_const(op: tasmop; flags: tcpumodeflags; a: aint);
  420. begin
  421. inherited create(op);
  422. ops := 2;
  423. loadmodeflags(0,flags);
  424. loadconst(1,a);
  425. end;
  426. constructor taicpu.op_specialreg_reg(op: tasmop; specialreg: tregister; specialregflags: tspecialregflags; _op2: tregister);
  427. begin
  428. inherited create(op);
  429. ops:=2;
  430. loadspecialreg(0,specialreg,specialregflags);
  431. loadreg(1,_op2);
  432. end;
  433. constructor taicpu.op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  434. begin
  435. inherited create(op);
  436. ops:=3;
  437. loadreg(0,_op1);
  438. loadreg(1,_op2);
  439. loadsymbol(0,_op3,_op3ofs);
  440. end;
  441. constructor taicpu.op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  442. begin
  443. inherited create(op);
  444. ops:=3;
  445. loadreg(0,_op1);
  446. loadreg(1,_op2);
  447. loadref(2,_op3);
  448. end;
  449. constructor taicpu.op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  450. begin
  451. inherited create(op);
  452. ops:=3;
  453. loadreg(0,_op1);
  454. loadreg(1,_op2);
  455. loadshifterop(2,_op3);
  456. end;
  457. constructor taicpu.op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
  458. begin
  459. inherited create(op);
  460. ops:=4;
  461. loadreg(0,_op1);
  462. loadreg(1,_op2);
  463. loadreg(2,_op3);
  464. loadshifterop(3,_op4);
  465. end;
  466. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  467. begin
  468. inherited create(op);
  469. condition:=cond;
  470. ops:=1;
  471. loadsymbol(0,_op1,0);
  472. end;
  473. constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
  474. begin
  475. inherited create(op);
  476. ops:=1;
  477. loadsymbol(0,_op1,0);
  478. end;
  479. constructor taicpu.op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  480. begin
  481. inherited create(op);
  482. ops:=1;
  483. loadsymbol(0,_op1,_op1ofs);
  484. end;
  485. constructor taicpu.op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  486. begin
  487. inherited create(op);
  488. ops:=2;
  489. loadreg(0,_op1);
  490. loadsymbol(1,_op2,_op2ofs);
  491. end;
  492. constructor taicpu.op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  493. begin
  494. inherited create(op);
  495. ops:=2;
  496. loadsymbol(0,_op1,_op1ofs);
  497. loadref(1,_op2);
  498. end;
  499. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  500. begin
  501. { allow the register allocator to remove unnecessary moves }
  502. result:=(
  503. ((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
  504. ((opcode=A_MVF) and (regtype = R_FPUREGISTER)) or
  505. ((opcode in [A_FCPYS, A_FCPYD]) and (regtype = R_MMREGISTER))
  506. ) and
  507. (oppostfix in [PF_None,PF_D]) and
  508. (condition=C_None) and
  509. (ops=2) and
  510. (oper[0]^.typ=top_reg) and
  511. (oper[1]^.typ=top_reg) and
  512. (oper[0]^.reg=oper[1]^.reg);
  513. end;
  514. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  515. var
  516. op: tasmop;
  517. begin
  518. case getregtype(r) of
  519. R_INTREGISTER :
  520. result:=taicpu.op_reg_ref(A_LDR,r,ref);
  521. R_FPUREGISTER :
  522. { use lfm because we don't know the current internal format
  523. and avoid exceptions
  524. }
  525. result:=taicpu.op_reg_const_ref(A_LFM,r,1,ref);
  526. R_MMREGISTER :
  527. begin
  528. case getsubreg(r) of
  529. R_SUBFD:
  530. op:=A_FLDD;
  531. R_SUBFS:
  532. op:=A_FLDS;
  533. R_SUBNONE:
  534. op:=A_VLDR;
  535. else
  536. internalerror(2009112905);
  537. end;
  538. result:=taicpu.op_reg_ref(op,r,ref);
  539. end;
  540. else
  541. internalerror(200401041);
  542. end;
  543. end;
  544. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  545. var
  546. op: tasmop;
  547. begin
  548. case getregtype(r) of
  549. R_INTREGISTER :
  550. result:=taicpu.op_reg_ref(A_STR,r,ref);
  551. R_FPUREGISTER :
  552. { use sfm because we don't know the current internal format
  553. and avoid exceptions
  554. }
  555. result:=taicpu.op_reg_const_ref(A_SFM,r,1,ref);
  556. R_MMREGISTER :
  557. begin
  558. case getsubreg(r) of
  559. R_SUBFD:
  560. op:=A_FSTD;
  561. R_SUBFS:
  562. op:=A_FSTS;
  563. R_SUBNONE:
  564. op:=A_VSTR;
  565. else
  566. internalerror(2009112904);
  567. end;
  568. result:=taicpu.op_reg_ref(op,r,ref);
  569. end;
  570. else
  571. internalerror(200401041);
  572. end;
  573. end;
  574. function taicpu.spilling_get_operation_type(opnr: longint): topertype;
  575. begin
  576. case opcode of
  577. A_ADC,A_ADD,A_AND,A_BIC,
  578. A_EOR,A_CLZ,A_RBIT,
  579. A_LDR,A_LDRB,A_LDRBT,A_LDRH,A_LDRSB,
  580. A_LDRSH,A_LDRT,
  581. A_MOV,A_MVN,A_MLA,A_MUL,
  582. A_ORR,A_RSB,A_RSC,A_SBC,A_SUB,
  583. A_SWP,A_SWPB,
  584. A_LDF,A_FLT,A_FIX,
  585. A_ADF,A_DVF,A_FDV,A_FML,
  586. A_RFS,A_RFC,A_RDF,
  587. A_RMF,A_RPW,A_RSF,A_SUF,A_ABS,A_ACS,A_ASN,A_ATN,A_COS,
  588. A_EXP,A_LOG,A_LGN,A_MVF,A_MNF,A_FRD,A_MUF,A_POL,A_RND,A_SIN,A_SQT,A_TAN,
  589. A_LFM,
  590. A_FLDS,A_FLDD,
  591. A_FMRX,A_FMXR,A_FMSTAT,
  592. A_FMSR,A_FMRS,A_FMDRR,
  593. A_FCPYS,A_FCPYD,A_FCVTSD,A_FCVTDS,
  594. A_FABSS,A_FABSD,A_FSQRTS,A_FSQRTD,A_FMULS,A_FMULD,
  595. A_FADDS,A_FADDD,A_FSUBS,A_FSUBD,A_FDIVS,A_FDIVD,
  596. A_FMACS,A_FMACD,A_FMSCS,A_FMSCD,A_FNMACS,A_FNMACD,
  597. A_FNMSCS,A_FNMSCD,A_FNMULS,A_FNMULD,
  598. A_FMDHR,A_FMRDH,A_FMDLR,A_FMRDL,
  599. A_FNEGS,A_FNEGD,
  600. A_FSITOS,A_FSITOD,A_FTOSIS,A_FTOSID,
  601. A_FTOUIS,A_FTOUID,A_FUITOS,A_FUITOD,
  602. A_SXTB16,A_UXTB16,
  603. A_UXTB,A_UXTH,A_SXTB,A_SXTH,
  604. A_NEG,
  605. A_VABS,A_VADD,A_VCVT,A_VDIV,A_VLDR,A_VMOV,A_VMUL,A_VNEG,A_VSQRT,A_VSUB:
  606. if opnr=0 then
  607. result:=operand_write
  608. else
  609. result:=operand_read;
  610. A_BKPT,A_B,A_BL,A_BLX,A_BX,
  611. A_CMN,A_CMP,A_TEQ,A_TST,
  612. A_CMF,A_CMFE,A_WFS,A_CNF,
  613. A_FCMPS,A_FCMPD,A_FCMPES,A_FCMPED,A_FCMPEZS,A_FCMPEZD,
  614. A_FCMPZS,A_FCMPZD,
  615. A_VCMP,A_VCMPE:
  616. result:=operand_read;
  617. A_SMLAL,A_UMLAL:
  618. if opnr in [0,1] then
  619. result:=operand_readwrite
  620. else
  621. result:=operand_read;
  622. A_SMULL,A_UMULL,
  623. A_FMRRD:
  624. if opnr in [0,1] then
  625. result:=operand_write
  626. else
  627. result:=operand_read;
  628. A_STR,A_STRB,A_STRBT,
  629. A_STRH,A_STRT,A_STF,A_SFM,
  630. A_FSTS,A_FSTD,
  631. A_VSTR:
  632. { important is what happens with the involved registers }
  633. if opnr=0 then
  634. result := operand_read
  635. else
  636. { check for pre/post indexed }
  637. result := operand_read;
  638. //Thumb2
  639. A_LSL, A_LSR, A_ROR, A_ASR, A_SDIV, A_UDIV, A_MOVW, A_MOVT, A_MLS, A_BFI:
  640. if opnr in [0] then
  641. result:=operand_write
  642. else
  643. result:=operand_read;
  644. A_BFC:
  645. if opnr in [0] then
  646. result:=operand_readwrite
  647. else
  648. result:=operand_read;
  649. A_LDREX:
  650. if opnr in [0] then
  651. result:=operand_write
  652. else
  653. result:=operand_read;
  654. A_STREX:
  655. if opnr in [0,1,2] then
  656. result:=operand_write;
  657. else
  658. internalerror(200403151);
  659. end;
  660. end;
  661. procedure BuildInsTabCache;
  662. var
  663. i : longint;
  664. begin
  665. new(instabcache);
  666. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  667. i:=0;
  668. while (i<InsTabEntries) do
  669. begin
  670. if InsTabCache^[InsTab[i].Opcode]=-1 then
  671. InsTabCache^[InsTab[i].Opcode]:=i;
  672. inc(i);
  673. end;
  674. end;
  675. procedure InitAsm;
  676. begin
  677. if not assigned(instabcache) then
  678. BuildInsTabCache;
  679. end;
  680. procedure DoneAsm;
  681. begin
  682. if assigned(instabcache) then
  683. begin
  684. dispose(instabcache);
  685. instabcache:=nil;
  686. end;
  687. end;
  688. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  689. begin
  690. i.oppostfix:=pf;
  691. result:=i;
  692. end;
  693. function setroundingmode(i : taicpu;rm : troundingmode) : taicpu;
  694. begin
  695. i.roundingmode:=rm;
  696. result:=i;
  697. end;
  698. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  699. begin
  700. i.condition:=c;
  701. result:=i;
  702. end;
  703. Function SimpleGetNextInstruction(Current: tai; Var Next: tai): Boolean;
  704. Begin
  705. Current:=tai(Current.Next);
  706. While Assigned(Current) And (Current.typ In SkipInstr) Do
  707. Current:=tai(Current.Next);
  708. Next:=Current;
  709. If Assigned(Next) And Not(Next.typ In SkipInstr) Then
  710. Result:=True
  711. Else
  712. Begin
  713. Next:=Nil;
  714. Result:=False;
  715. End;
  716. End;
  717. (*
  718. function armconstequal(hp1,hp2: tai): boolean;
  719. begin
  720. result:=false;
  721. if hp1.typ<>hp2.typ then
  722. exit;
  723. case hp1.typ of
  724. tai_const:
  725. result:=
  726. (tai_const(hp2).sym=tai_const(hp).sym) and
  727. (tai_const(hp2).value=tai_const(hp).value) and
  728. (tai(hp2.previous).typ=ait_label);
  729. tai_const:
  730. result:=
  731. (tai_const(hp2).sym=tai_const(hp).sym) and
  732. (tai_const(hp2).value=tai_const(hp).value) and
  733. (tai(hp2.previous).typ=ait_label);
  734. end;
  735. end;
  736. *)
  737. procedure insertpcrelativedata(list,listtoinsert : TAsmList);
  738. var
  739. curinspos,
  740. penalty,
  741. lastinspos,
  742. { increased for every data element > 4 bytes inserted }
  743. currentsize,
  744. extradataoffset,
  745. limit: longint;
  746. curop : longint;
  747. curtai : tai;
  748. ai_label : tai_label;
  749. curdatatai,hp,hp2 : tai;
  750. curdata : TAsmList;
  751. l : tasmlabel;
  752. doinsert,
  753. removeref : boolean;
  754. multiplier : byte;
  755. begin
  756. curdata:=TAsmList.create;
  757. lastinspos:=-1;
  758. curinspos:=0;
  759. extradataoffset:=0;
  760. if GenerateThumbCode then
  761. begin
  762. multiplier:=2;
  763. limit:=504;
  764. end
  765. else
  766. begin
  767. limit:=1016;
  768. multiplier:=1;
  769. end;
  770. curtai:=tai(list.first);
  771. doinsert:=false;
  772. while assigned(curtai) do
  773. begin
  774. { instruction? }
  775. case curtai.typ of
  776. ait_instruction:
  777. begin
  778. { walk through all operand of the instruction }
  779. for curop:=0 to taicpu(curtai).ops-1 do
  780. begin
  781. { reference? }
  782. if (taicpu(curtai).oper[curop]^.typ=top_ref) then
  783. begin
  784. { pc relative symbol? }
  785. curdatatai:=tai(taicpu(curtai).oper[curop]^.ref^.symboldata);
  786. if assigned(curdatatai) then
  787. begin
  788. { create a new copy of a data entry on arm thumb if the entry has been inserted already
  789. before because arm thumb does not allow pc relative negative offsets }
  790. if (GenerateThumbCode) and
  791. tai_label(curdatatai).inserted then
  792. begin
  793. current_asmdata.getjumplabel(l);
  794. hp:=tai_label.create(l);
  795. listtoinsert.Concat(hp);
  796. hp2:=tai(curdatatai.Next.GetCopy);
  797. hp2.Next:=nil;
  798. hp2.Previous:=nil;
  799. listtoinsert.Concat(hp2);
  800. taicpu(curtai).oper[curop]^.ref^.symboldata:=hp;
  801. taicpu(curtai).oper[curop]^.ref^.symbol:=l;
  802. curdatatai:=hp;
  803. end;
  804. { move only if we're at the first reference of a label }
  805. if not(tai_label(curdatatai).moved) then
  806. begin
  807. tai_label(curdatatai).moved:=true;
  808. { check if symbol already used. }
  809. { if yes, reuse the symbol }
  810. hp:=tai(curdatatai.next);
  811. removeref:=false;
  812. if assigned(hp) then
  813. begin
  814. case hp.typ of
  815. ait_const:
  816. begin
  817. if (tai_const(hp).consttype=aitconst_64bit) then
  818. inc(extradataoffset,multiplier);
  819. end;
  820. ait_comp_64bit,
  821. ait_real_64bit:
  822. begin
  823. inc(extradataoffset,multiplier);
  824. end;
  825. ait_real_80bit:
  826. begin
  827. inc(extradataoffset,2*multiplier);
  828. end;
  829. end;
  830. { check if the same constant has been already inserted into the currently handled list,
  831. if yes, reuse it }
  832. if (hp.typ=ait_const) then
  833. begin
  834. hp2:=tai(curdata.first);
  835. while assigned(hp2) do
  836. begin
  837. if (hp2.typ=ait_const) and (tai_const(hp2).sym=tai_const(hp).sym)
  838. and (tai_const(hp2).value=tai_const(hp).value) and (tai(hp2.previous).typ=ait_label)
  839. then
  840. begin
  841. with taicpu(curtai).oper[curop]^.ref^ do
  842. begin
  843. symboldata:=hp2.previous;
  844. symbol:=tai_label(hp2.previous).labsym;
  845. end;
  846. removeref:=true;
  847. break;
  848. end;
  849. hp2:=tai(hp2.next);
  850. end;
  851. end;
  852. end;
  853. { move or remove symbol reference }
  854. repeat
  855. hp:=tai(curdatatai.next);
  856. listtoinsert.remove(curdatatai);
  857. if removeref then
  858. curdatatai.free
  859. else
  860. curdata.concat(curdatatai);
  861. curdatatai:=hp;
  862. until (curdatatai=nil) or (curdatatai.typ=ait_label);
  863. if lastinspos=-1 then
  864. lastinspos:=curinspos;
  865. end;
  866. end;
  867. end;
  868. end;
  869. inc(curinspos,multiplier);
  870. end;
  871. ait_align:
  872. begin
  873. { code is always 4 byte aligned, so we don't have to take care of .align 2 which would
  874. requires also incrementing curinspos by 1 }
  875. inc(curinspos,(tai_align(curtai).aligntype div 4)*multiplier);
  876. end;
  877. ait_const:
  878. begin
  879. inc(curinspos,multiplier);
  880. if (tai_const(curtai).consttype=aitconst_64bit) then
  881. inc(curinspos,multiplier);
  882. end;
  883. ait_real_32bit:
  884. begin
  885. inc(curinspos,multiplier);
  886. end;
  887. ait_comp_64bit,
  888. ait_real_64bit:
  889. begin
  890. inc(curinspos,2*multiplier);
  891. end;
  892. ait_real_80bit:
  893. begin
  894. inc(curinspos,3*multiplier);
  895. end;
  896. end;
  897. { special case for case jump tables }
  898. if SimpleGetNextInstruction(curtai,hp) and
  899. (tai(hp).typ=ait_instruction) then
  900. begin
  901. case taicpu(hp).opcode of
  902. A_BX,
  903. A_LDR:
  904. { approximation if we hit a case jump table }
  905. if ((taicpu(hp).opcode=A_LDR) and not(GenerateThumbCode or GenerateThumb2Code) and
  906. (taicpu(hp).oper[0]^.typ=top_reg) and
  907. (taicpu(hp).oper[0]^.reg=NR_PC)) or
  908. ((taicpu(hp).opcode=A_BX) and (GenerateThumbCode) and
  909. (taicpu(hp).oper[0]^.typ=top_reg))
  910. then
  911. begin
  912. penalty:=multiplier;
  913. hp:=tai(hp.next);
  914. { skip register allocations and comments inserted by the optimizer as well as a label
  915. as jump tables for thumb might have }
  916. while assigned(hp) and (hp.typ in [ait_comment,ait_regalloc,ait_label]) do
  917. hp:=tai(hp.next);
  918. while assigned(hp) and (hp.typ=ait_const) do
  919. begin
  920. inc(penalty,multiplier);
  921. hp:=tai(hp.next);
  922. end;
  923. end;
  924. A_IT:
  925. if GenerateThumb2Code then
  926. penalty:=multiplier;
  927. A_ITE,
  928. A_ITT:
  929. if GenerateThumb2Code then
  930. penalty:=2*multiplier;
  931. A_ITEE,
  932. A_ITTE,
  933. A_ITET,
  934. A_ITTT:
  935. if GenerateThumb2Code then
  936. penalty:=3*multiplier;
  937. A_ITEEE,
  938. A_ITTEE,
  939. A_ITETE,
  940. A_ITTTE,
  941. A_ITEET,
  942. A_ITTET,
  943. A_ITETT,
  944. A_ITTTT:
  945. if GenerateThumb2Code then
  946. penalty:=4*multiplier;
  947. else
  948. penalty:=0;
  949. end;
  950. end
  951. else
  952. penalty:=0;
  953. { FLD/FST VFP instructions have a limit of +/- 1024, not 4096 }
  954. if SimpleGetNextInstruction(curtai,hp) and
  955. (tai(hp).typ=ait_instruction) and
  956. ((taicpu(hp).opcode=A_FLDS) or
  957. (taicpu(hp).opcode=A_FLDD) or
  958. (taicpu(hp).opcode=A_VLDR)) then
  959. limit:=254;
  960. { don't miss an insert }
  961. doinsert:=doinsert or
  962. (not(curdata.empty) and
  963. (curinspos-lastinspos+penalty+extradataoffset>limit));
  964. { split only at real instructions else the test below fails }
  965. if doinsert and (curtai.typ=ait_instruction) and
  966. (
  967. { don't split loads of pc to lr and the following move }
  968. not(
  969. (taicpu(curtai).opcode=A_MOV) and
  970. (taicpu(curtai).oper[0]^.typ=top_reg) and
  971. (taicpu(curtai).oper[0]^.reg=NR_R14) and
  972. (taicpu(curtai).oper[1]^.typ=top_reg) and
  973. (taicpu(curtai).oper[1]^.reg=NR_PC)
  974. )
  975. ) and
  976. (
  977. { do not insert data after a B instruction due to their limited range }
  978. not((GenerateThumbCode) and
  979. (taicpu(curtai).opcode=A_B)
  980. )
  981. ) then
  982. begin
  983. lastinspos:=-1;
  984. extradataoffset:=0;
  985. if GenerateThumbCode then
  986. limit:=502
  987. else
  988. limit:=1016;
  989. { on arm thumb, insert the data always after all labels etc. following an instruction so it
  990. is prevent that a bxx yyy; bl xxx; yyyy: sequence gets separated ( we never insert on arm thumb after
  991. bxx) and the distance of bxx gets too long }
  992. if GenerateThumbCode then
  993. while assigned(tai(curtai.Next)) and (tai(curtai.Next).typ in SkipInstr+[ait_label]) do
  994. curtai:=tai(curtai.next);
  995. doinsert:=false;
  996. current_asmdata.getjumplabel(l);
  997. { align thumb in thumb .text section to 4 bytes }
  998. if not(curdata.empty) and (GenerateThumbCode) then
  999. curdata.Insert(tai_align.Create(4));
  1000. curdata.insert(taicpu.op_sym(A_B,l));
  1001. curdata.concat(tai_label.create(l));
  1002. { mark all labels as inserted, arm thumb
  1003. needs this, so data referencing an already inserted label can be
  1004. duplicated because arm thumb does not allow negative pc relative offset }
  1005. hp2:=tai(curdata.first);
  1006. while assigned(hp2) do
  1007. begin
  1008. if hp2.typ=ait_label then
  1009. tai_label(hp2).inserted:=true;
  1010. hp2:=tai(hp2.next);
  1011. end;
  1012. { continue with the last inserted label because we use later
  1013. on SimpleGetNextInstruction, so if we used curtai.next (which
  1014. is then equal curdata.last.previous) we could over see one
  1015. instruction }
  1016. hp:=tai(curdata.Last);
  1017. list.insertlistafter(curtai,curdata);
  1018. curtai:=hp;
  1019. end
  1020. else
  1021. curtai:=tai(curtai.next);
  1022. end;
  1023. { align thumb in thumb .text section to 4 bytes }
  1024. if not(curdata.empty) and (GenerateThumbCode or GenerateThumb2Code) then
  1025. curdata.Insert(tai_align.Create(4));
  1026. list.concatlist(curdata);
  1027. curdata.free;
  1028. end;
  1029. procedure ensurethumb2encodings(list: TAsmList);
  1030. var
  1031. curtai: tai;
  1032. op2reg: TRegister;
  1033. begin
  1034. { Do Thumb-2 16bit -> 32bit transformations }
  1035. curtai:=tai(list.first);
  1036. while assigned(curtai) do
  1037. begin
  1038. case curtai.typ of
  1039. ait_instruction:
  1040. begin
  1041. case taicpu(curtai).opcode of
  1042. A_ADD:
  1043. begin
  1044. { Set wide flag for ADD Rd,Rn,Rm where registers are over R7(high register set) }
  1045. if taicpu(curtai).ops = 3 then
  1046. begin
  1047. if taicpu(curtai).oper[2]^.typ in [top_reg,top_shifterop] then
  1048. begin
  1049. if taicpu(curtai).oper[2]^.typ = top_reg then
  1050. op2reg := taicpu(curtai).oper[2]^.reg
  1051. else if taicpu(curtai).oper[2]^.shifterop^.rs <> NR_NO then
  1052. op2reg := taicpu(curtai).oper[2]^.shifterop^.rs
  1053. else
  1054. op2reg := NR_NO;
  1055. if op2reg <> NR_NO then
  1056. begin
  1057. if (taicpu(curtai).oper[0]^.reg >= NR_R8) or
  1058. (taicpu(curtai).oper[1]^.reg >= NR_R8) or
  1059. (op2reg >= NR_R8) then
  1060. begin
  1061. taicpu(curtai).wideformat:=true;
  1062. { Handle special cases where register rules are violated by optimizer/user }
  1063. { if d == 13 || (d == 15 && S == ‘0’) || n == 15 || m IN [13,15] then UNPREDICTABLE; }
  1064. { Transform ADD.W Rx, Ry, R13 into ADD.W Rx, R13, Ry }
  1065. if (op2reg = NR_R13) and (taicpu(curtai).oper[2]^.typ = top_reg) then
  1066. begin
  1067. taicpu(curtai).oper[2]^.reg := taicpu(curtai).oper[1]^.reg;
  1068. taicpu(curtai).oper[1]^.reg := op2reg;
  1069. end;
  1070. end;
  1071. end;
  1072. end;
  1073. end;
  1074. end;
  1075. end;
  1076. end;
  1077. end;
  1078. curtai:=tai(curtai.Next);
  1079. end;
  1080. end;
  1081. function getMergedInstruction(FirstOp,LastOp:TAsmOp;InvertLast:boolean) : TAsmOp;
  1082. const
  1083. opTable: array[A_IT..A_ITTTT] of string =
  1084. ('T','TE','TT','TEE','TTE','TET','TTT',
  1085. 'TEEE','TTEE','TETE','TTTE',
  1086. 'TEET','TTET','TETT','TTTT');
  1087. invertedOpTable: array[A_IT..A_ITTTT] of string =
  1088. ('E','ET','EE','ETT','EET','ETE','EEE',
  1089. 'ETTT','EETT','ETET','EEET',
  1090. 'ETTE','EETE','ETEE','EEEE');
  1091. var
  1092. resStr : string;
  1093. i : TAsmOp;
  1094. begin
  1095. if InvertLast then
  1096. resStr := opTable[FirstOp]+invertedOpTable[LastOp]
  1097. else
  1098. resStr := opTable[FirstOp]+opTable[LastOp];
  1099. if length(resStr) > 4 then
  1100. internalerror(2012100805);
  1101. for i := low(opTable) to high(opTable) do
  1102. if opTable[i] = resStr then
  1103. exit(i);
  1104. internalerror(2012100806);
  1105. end;
  1106. procedure foldITInstructions(list: TAsmList);
  1107. var
  1108. curtai,hp1 : tai;
  1109. levels,i : LongInt;
  1110. begin
  1111. curtai:=tai(list.First);
  1112. while assigned(curtai) do
  1113. begin
  1114. case curtai.typ of
  1115. ait_instruction:
  1116. if IsIT(taicpu(curtai).opcode) then
  1117. begin
  1118. levels := GetITLevels(taicpu(curtai).opcode);
  1119. if levels < 4 then
  1120. begin
  1121. i:=levels;
  1122. hp1:=tai(curtai.Next);
  1123. while assigned(hp1) and
  1124. (i > 0) do
  1125. begin
  1126. if hp1.typ=ait_instruction then
  1127. begin
  1128. dec(i);
  1129. if (i = 0) and
  1130. mustbelast(hp1) then
  1131. begin
  1132. hp1:=nil;
  1133. break;
  1134. end;
  1135. end;
  1136. hp1:=tai(hp1.Next);
  1137. end;
  1138. if assigned(hp1) then
  1139. begin
  1140. // We are pointing at the first instruction after the IT block
  1141. while assigned(hp1) and
  1142. (hp1.typ<>ait_instruction) do
  1143. hp1:=tai(hp1.Next);
  1144. if assigned(hp1) and
  1145. (hp1.typ=ait_instruction) and
  1146. IsIT(taicpu(hp1).opcode) then
  1147. begin
  1148. if (levels+GetITLevels(taicpu(hp1).opcode) <= 4) and
  1149. ((taicpu(curtai).oper[0]^.cc=taicpu(hp1).oper[0]^.cc) or
  1150. (taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc))) then
  1151. begin
  1152. taicpu(curtai).opcode:=getMergedInstruction(taicpu(curtai).opcode,
  1153. taicpu(hp1).opcode,
  1154. taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc));
  1155. list.Remove(hp1);
  1156. hp1.Free;
  1157. end;
  1158. end;
  1159. end;
  1160. end;
  1161. end;
  1162. end;
  1163. curtai:=tai(curtai.Next);
  1164. end;
  1165. end;
  1166. procedure finalizearmcode(list, listtoinsert: TAsmList);
  1167. begin
  1168. { Do Thumb-2 16bit -> 32bit transformations }
  1169. if GenerateThumb2Code then
  1170. begin
  1171. ensurethumb2encodings(list);
  1172. foldITInstructions(list);
  1173. end;
  1174. insertpcrelativedata(list, listtoinsert);
  1175. end;
  1176. procedure InsertPData;
  1177. var
  1178. prolog: TAsmList;
  1179. begin
  1180. prolog:=TAsmList.create;
  1181. new_section(prolog,sec_code,'FPC_EH_PROLOG',sizeof(pint),secorder_begin);
  1182. prolog.concat(Tai_const.Createname('_ARM_ExceptionHandler', 0));
  1183. prolog.concat(Tai_const.Create_32bit(0));
  1184. prolog.concat(Tai_symbol.Createname_global('FPC_EH_CODE_START',AT_DATA,0));
  1185. { dummy function }
  1186. prolog.concat(taicpu.op_reg_reg(A_MOV,NR_R15,NR_R14));
  1187. current_asmdata.asmlists[al_start].insertList(prolog);
  1188. prolog.Free;
  1189. new_section(current_asmdata.asmlists[al_end],sec_pdata,'',sizeof(pint));
  1190. current_asmdata.asmlists[al_end].concat(Tai_const.Createname('FPC_EH_CODE_START', 0));
  1191. current_asmdata.asmlists[al_end].concat(Tai_const.Create_32bit(longint($ffffff01)));
  1192. end;
  1193. (*
  1194. Floating point instruction format information, taken from the linux kernel
  1195. ARM Floating Point Instruction Classes
  1196. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  1197. |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
  1198. |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
  1199. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  1200. |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
  1201. |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
  1202. |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
  1203. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  1204. CPDT data transfer instructions
  1205. LDF, STF, LFM (copro 2), SFM (copro 2)
  1206. CPDO dyadic arithmetic instructions
  1207. ADF, MUF, SUF, RSF, DVF, RDF,
  1208. POW, RPW, RMF, FML, FDV, FRD, POL
  1209. CPDO monadic arithmetic instructions
  1210. MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
  1211. SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
  1212. CPRT joint arithmetic/data transfer instructions
  1213. FIX (arithmetic followed by load/store)
  1214. FLT (load/store followed by arithmetic)
  1215. CMF, CNF CMFE, CNFE (comparisons)
  1216. WFS, RFS (write/read floating point status register)
  1217. WFC, RFC (write/read floating point control register)
  1218. cond condition codes
  1219. P pre/post index bit: 0 = postindex, 1 = preindex
  1220. U up/down bit: 0 = stack grows down, 1 = stack grows up
  1221. W write back bit: 1 = update base register (Rn)
  1222. L load/store bit: 0 = store, 1 = load
  1223. Rn base register
  1224. Rd destination/source register
  1225. Fd floating point destination register
  1226. Fn floating point source register
  1227. Fm floating point source register or floating point constant
  1228. uv transfer length (TABLE 1)
  1229. wx register count (TABLE 2)
  1230. abcd arithmetic opcode (TABLES 3 & 4)
  1231. ef destination size (rounding precision) (TABLE 5)
  1232. gh rounding mode (TABLE 6)
  1233. j dyadic/monadic bit: 0 = dyadic, 1 = monadic
  1234. i constant bit: 1 = constant (TABLE 6)
  1235. */
  1236. /*
  1237. TABLE 1
  1238. +-------------------------+---+---+---------+---------+
  1239. | Precision | u | v | FPSR.EP | length |
  1240. +-------------------------+---+---+---------+---------+
  1241. | Single | 0 | 0 | x | 1 words |
  1242. | Double | 1 | 1 | x | 2 words |
  1243. | Extended | 1 | 1 | x | 3 words |
  1244. | Packed decimal | 1 | 1 | 0 | 3 words |
  1245. | Expanded packed decimal | 1 | 1 | 1 | 4 words |
  1246. +-------------------------+---+---+---------+---------+
  1247. Note: x = don't care
  1248. */
  1249. /*
  1250. TABLE 2
  1251. +---+---+---------------------------------+
  1252. | w | x | Number of registers to transfer |
  1253. +---+---+---------------------------------+
  1254. | 0 | 1 | 1 |
  1255. | 1 | 0 | 2 |
  1256. | 1 | 1 | 3 |
  1257. | 0 | 0 | 4 |
  1258. +---+---+---------------------------------+
  1259. */
  1260. /*
  1261. TABLE 3: Dyadic Floating Point Opcodes
  1262. +---+---+---+---+----------+-----------------------+-----------------------+
  1263. | a | b | c | d | Mnemonic | Description | Operation |
  1264. +---+---+---+---+----------+-----------------------+-----------------------+
  1265. | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
  1266. | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
  1267. | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
  1268. | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
  1269. | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
  1270. | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
  1271. | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
  1272. | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
  1273. | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
  1274. | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
  1275. | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
  1276. | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
  1277. | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
  1278. | 1 | 1 | 0 | 1 | | undefined instruction | trap |
  1279. | 1 | 1 | 1 | 0 | | undefined instruction | trap |
  1280. | 1 | 1 | 1 | 1 | | undefined instruction | trap |
  1281. +---+---+---+---+----------+-----------------------+-----------------------+
  1282. Note: POW, RPW, POL are deprecated, and are available for backwards
  1283. compatibility only.
  1284. */
  1285. /*
  1286. TABLE 4: Monadic Floating Point Opcodes
  1287. +---+---+---+---+----------+-----------------------+-----------------------+
  1288. | a | b | c | d | Mnemonic | Description | Operation |
  1289. +---+---+---+---+----------+-----------------------+-----------------------+
  1290. | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
  1291. | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
  1292. | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
  1293. | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
  1294. | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
  1295. | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
  1296. | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
  1297. | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
  1298. | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
  1299. | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
  1300. | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
  1301. | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
  1302. | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
  1303. | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
  1304. | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
  1305. | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
  1306. +---+---+---+---+----------+-----------------------+-----------------------+
  1307. Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
  1308. available for backwards compatibility only.
  1309. */
  1310. /*
  1311. TABLE 5
  1312. +-------------------------+---+---+
  1313. | Rounding Precision | e | f |
  1314. +-------------------------+---+---+
  1315. | IEEE Single precision | 0 | 0 |
  1316. | IEEE Double precision | 0 | 1 |
  1317. | IEEE Extended precision | 1 | 0 |
  1318. | undefined (trap) | 1 | 1 |
  1319. +-------------------------+---+---+
  1320. */
  1321. /*
  1322. TABLE 5
  1323. +---------------------------------+---+---+
  1324. | Rounding Mode | g | h |
  1325. +---------------------------------+---+---+
  1326. | Round to nearest (default) | 0 | 0 |
  1327. | Round toward plus infinity | 0 | 1 |
  1328. | Round toward negative infinity | 1 | 0 |
  1329. | Round toward zero | 1 | 1 |
  1330. +---------------------------------+---+---+
  1331. *)
  1332. function taicpu.GetString:string;
  1333. var
  1334. i : longint;
  1335. s : string;
  1336. addsize : boolean;
  1337. begin
  1338. s:='['+gas_op2str[opcode];
  1339. for i:=0 to ops-1 do
  1340. begin
  1341. with oper[i]^ do
  1342. begin
  1343. if i=0 then
  1344. s:=s+' '
  1345. else
  1346. s:=s+',';
  1347. { type }
  1348. addsize:=false;
  1349. if (ot and OT_VREG)=OT_VREG then
  1350. s:=s+'vreg'
  1351. else
  1352. if (ot and OT_FPUREG)=OT_FPUREG then
  1353. s:=s+'fpureg'
  1354. else
  1355. if (ot and OT_REGISTER)=OT_REGISTER then
  1356. begin
  1357. s:=s+'reg';
  1358. addsize:=true;
  1359. end
  1360. else
  1361. if (ot and OT_REGLIST)=OT_REGLIST then
  1362. begin
  1363. s:=s+'reglist';
  1364. addsize:=false;
  1365. end
  1366. else
  1367. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  1368. begin
  1369. s:=s+'imm';
  1370. addsize:=true;
  1371. end
  1372. else
  1373. if (ot and OT_MEMORY)=OT_MEMORY then
  1374. begin
  1375. s:=s+'mem';
  1376. addsize:=true;
  1377. if (ot and OT_AM2)<>0 then
  1378. s:=s+' am2 ';
  1379. end
  1380. else
  1381. s:=s+'???';
  1382. { size }
  1383. if addsize then
  1384. begin
  1385. if (ot and OT_BITS8)<>0 then
  1386. s:=s+'8'
  1387. else
  1388. if (ot and OT_BITS16)<>0 then
  1389. s:=s+'24'
  1390. else
  1391. if (ot and OT_BITS32)<>0 then
  1392. s:=s+'32'
  1393. else
  1394. if (ot and OT_BITSSHIFTER)<>0 then
  1395. s:=s+'shifter'
  1396. else
  1397. s:=s+'??';
  1398. { signed }
  1399. if (ot and OT_SIGNED)<>0 then
  1400. s:=s+'s';
  1401. end;
  1402. end;
  1403. end;
  1404. GetString:=s+']';
  1405. end;
  1406. procedure taicpu.ResetPass1;
  1407. begin
  1408. { we need to reset everything here, because the choosen insentry
  1409. can be invalid for a new situation where the previously optimized
  1410. insentry is not correct }
  1411. InsEntry:=nil;
  1412. InsSize:=0;
  1413. LastInsOffset:=-1;
  1414. end;
  1415. procedure taicpu.ResetPass2;
  1416. begin
  1417. { we are here in a second pass, check if the instruction can be optimized }
  1418. if assigned(InsEntry) and
  1419. ((InsEntry^.flags and IF_PASS2)<>0) then
  1420. begin
  1421. InsEntry:=nil;
  1422. InsSize:=0;
  1423. end;
  1424. LastInsOffset:=-1;
  1425. end;
  1426. function taicpu.CheckIfValid:boolean;
  1427. begin
  1428. Result:=False; { unimplemented }
  1429. end;
  1430. function taicpu.Pass1(objdata:TObjData):longint;
  1431. var
  1432. ldr2op : array[PF_B..PF_T] of tasmop = (
  1433. A_LDRB,A_LDRSB,A_LDRBT,A_LDRH,A_LDRSH,A_LDRT);
  1434. str2op : array[PF_B..PF_T] of tasmop = (
  1435. A_STRB,A_None,A_STRBT,A_STRH,A_None,A_STRT);
  1436. begin
  1437. Pass1:=0;
  1438. { Save the old offset and set the new offset }
  1439. InsOffset:=ObjData.CurrObjSec.Size;
  1440. { Error? }
  1441. if (Insentry=nil) and (InsSize=-1) then
  1442. exit;
  1443. { set the file postion }
  1444. current_filepos:=fileinfo;
  1445. { tranlate LDR+postfix to complete opcode }
  1446. if (opcode=A_LDR) and (oppostfix<>PF_None) then
  1447. begin
  1448. if (oppostfix in [low(ldr2op)..high(ldr2op)]) then
  1449. opcode:=ldr2op[oppostfix]
  1450. else
  1451. internalerror(2005091001);
  1452. if opcode=A_None then
  1453. internalerror(2005091004);
  1454. { postfix has been added to opcode }
  1455. oppostfix:=PF_None;
  1456. end
  1457. else if (opcode=A_STR) and (oppostfix<>PF_None) then
  1458. begin
  1459. if (oppostfix in [low(str2op)..high(str2op)]) then
  1460. opcode:=str2op[oppostfix]
  1461. else
  1462. internalerror(2005091002);
  1463. if opcode=A_None then
  1464. internalerror(2005091003);
  1465. { postfix has been added to opcode }
  1466. oppostfix:=PF_None;
  1467. end;
  1468. { Get InsEntry }
  1469. if FindInsEntry(objdata) then
  1470. begin
  1471. InsSize:=4;
  1472. LastInsOffset:=InsOffset;
  1473. Pass1:=InsSize;
  1474. exit;
  1475. end;
  1476. LastInsOffset:=-1;
  1477. end;
  1478. procedure taicpu.Pass2(objdata:TObjData);
  1479. begin
  1480. { error in pass1 ? }
  1481. if insentry=nil then
  1482. exit;
  1483. current_filepos:=fileinfo;
  1484. { Generate the instruction }
  1485. GenCode(objdata);
  1486. end;
  1487. procedure taicpu.ppuloadoper(ppufile:tcompilerppufile;var o:toper);
  1488. begin
  1489. end;
  1490. procedure taicpu.ppuwriteoper(ppufile:tcompilerppufile;const o:toper);
  1491. begin
  1492. end;
  1493. procedure taicpu.ppubuildderefimploper(var o:toper);
  1494. begin
  1495. end;
  1496. procedure taicpu.ppuderefoper(var o:toper);
  1497. begin
  1498. end;
  1499. function taicpu.InsEnd:longint;
  1500. begin
  1501. Result:=0; { unimplemented }
  1502. end;
  1503. procedure taicpu.create_ot(objdata:TObjData);
  1504. var
  1505. i,l,relsize : longint;
  1506. dummy : byte;
  1507. currsym : TObjSymbol;
  1508. begin
  1509. if ops=0 then
  1510. exit;
  1511. { update oper[].ot field }
  1512. for i:=0 to ops-1 do
  1513. with oper[i]^ do
  1514. begin
  1515. case typ of
  1516. top_regset:
  1517. begin
  1518. ot:=OT_REGLIST;
  1519. end;
  1520. top_reg :
  1521. begin
  1522. case getregtype(reg) of
  1523. R_INTREGISTER:
  1524. ot:=OT_REG32 or OT_SHIFTEROP;
  1525. R_FPUREGISTER:
  1526. ot:=OT_FPUREG;
  1527. else
  1528. internalerror(2005090901);
  1529. end;
  1530. end;
  1531. top_ref :
  1532. begin
  1533. if ref^.refaddr=addr_no then
  1534. begin
  1535. { create ot field }
  1536. { we should get the size here dependend on the
  1537. instruction }
  1538. if (ot and OT_SIZE_MASK)=0 then
  1539. ot:=OT_MEMORY or OT_BITS32
  1540. else
  1541. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  1542. if (ref^.base=NR_NO) and (ref^.index=NR_NO) then
  1543. ot:=ot or OT_MEM_OFFS;
  1544. { if we need to fix a reference, we do it here }
  1545. { pc relative addressing }
  1546. if (ref^.base=NR_NO) and
  1547. (ref^.index=NR_NO) and
  1548. (ref^.shiftmode=SM_None)
  1549. { at least we should check if the destination symbol
  1550. is in a text section }
  1551. { and
  1552. (ref^.symbol^.owner="text") } then
  1553. ref^.base:=NR_PC;
  1554. { determine possible address modes }
  1555. if (ref^.base<>NR_NO) and
  1556. (
  1557. (
  1558. (ref^.index=NR_NO) and
  1559. (ref^.shiftmode=SM_None) and
  1560. (ref^.offset>=-4097) and
  1561. (ref^.offset<=4097)
  1562. ) or
  1563. (
  1564. (ref^.shiftmode=SM_None) and
  1565. (ref^.offset=0)
  1566. ) or
  1567. (
  1568. (ref^.index<>NR_NO) and
  1569. (ref^.shiftmode<>SM_None) and
  1570. (ref^.shiftimm<=31) and
  1571. (ref^.offset=0)
  1572. )
  1573. ) then
  1574. ot:=ot or OT_AM2;
  1575. if (ref^.index<>NR_NO) and
  1576. (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
  1577. (
  1578. (ref^.base=NR_NO) and
  1579. (ref^.shiftmode=SM_None) and
  1580. (ref^.offset=0)
  1581. ) then
  1582. ot:=ot or OT_AM4;
  1583. end
  1584. else
  1585. begin
  1586. l:=ref^.offset;
  1587. currsym:=ObjData.symbolref(ref^.symbol);
  1588. if assigned(currsym) then
  1589. inc(l,currsym.address);
  1590. relsize:=(InsOffset+2)-l;
  1591. if (relsize<-33554428) or (relsize>33554428) then
  1592. ot:=OT_IMM32
  1593. else
  1594. ot:=OT_IMM24;
  1595. end;
  1596. end;
  1597. top_local :
  1598. begin
  1599. { we should get the size here dependend on the
  1600. instruction }
  1601. if (ot and OT_SIZE_MASK)=0 then
  1602. ot:=OT_MEMORY or OT_BITS32
  1603. else
  1604. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  1605. end;
  1606. top_const :
  1607. begin
  1608. ot:=OT_IMMEDIATE;
  1609. if is_shifter_const(val,dummy) then
  1610. ot:=OT_IMMSHIFTER
  1611. else
  1612. ot:=OT_IMM32
  1613. end;
  1614. top_none :
  1615. begin
  1616. { generated when there was an error in the
  1617. assembler reader. It never happends when generating
  1618. assembler }
  1619. end;
  1620. top_shifterop:
  1621. begin
  1622. ot:=OT_SHIFTEROP;
  1623. end;
  1624. else
  1625. internalerror(200402261);
  1626. end;
  1627. end;
  1628. end;
  1629. function taicpu.Matches(p:PInsEntry):longint;
  1630. { * IF_SM stands for Size Match: any operand whose size is not
  1631. * explicitly specified by the template is `really' intended to be
  1632. * the same size as the first size-specified operand.
  1633. * Non-specification is tolerated in the input instruction, but
  1634. * _wrong_ specification is not.
  1635. *
  1636. * IF_SM2 invokes Size Match on only the first _two_ operands, for
  1637. * three-operand instructions such as SHLD: it implies that the
  1638. * first two operands must match in size, but that the third is
  1639. * required to be _unspecified_.
  1640. *
  1641. * IF_SB invokes Size Byte: operands with unspecified size in the
  1642. * template are really bytes, and so no non-byte specification in
  1643. * the input instruction will be tolerated. IF_SW similarly invokes
  1644. * Size Word, and IF_SD invokes Size Doubleword.
  1645. *
  1646. * (The default state if neither IF_SM nor IF_SM2 is specified is
  1647. * that any operand with unspecified size in the template is
  1648. * required to have unspecified size in the instruction too...)
  1649. }
  1650. var
  1651. i{,j,asize,oprs} : longint;
  1652. {siz : array[0..3] of longint;}
  1653. begin
  1654. Matches:=100;
  1655. writeln(getstring,'---');
  1656. { Check the opcode and operands }
  1657. if (p^.opcode<>opcode) or (p^.ops<>ops) then
  1658. begin
  1659. Matches:=0;
  1660. exit;
  1661. end;
  1662. { Check that no spurious colons or TOs are present }
  1663. for i:=0 to p^.ops-1 do
  1664. if (oper[i]^.ot and (not p^.optypes[i]) and (OT_COLON or OT_TO))<>0 then
  1665. begin
  1666. Matches:=0;
  1667. exit;
  1668. end;
  1669. { Check that the operand flags all match up }
  1670. for i:=0 to p^.ops-1 do
  1671. begin
  1672. if ((p^.optypes[i] and (not oper[i]^.ot)) or
  1673. ((p^.optypes[i] and OT_SIZE_MASK) and
  1674. ((p^.optypes[i] xor oper[i]^.ot) and OT_SIZE_MASK)))<>0 then
  1675. begin
  1676. if ((p^.optypes[i] and (not oper[i]^.ot) and OT_NON_SIZE) or
  1677. (oper[i]^.ot and OT_SIZE_MASK))<>0 then
  1678. begin
  1679. Matches:=0;
  1680. exit;
  1681. end
  1682. else
  1683. Matches:=1;
  1684. end;
  1685. end;
  1686. { check postfixes:
  1687. the existance of a certain postfix requires a
  1688. particular code }
  1689. { update condition flags
  1690. or floating point single }
  1691. if (oppostfix=PF_S) and
  1692. not(p^.code[0] in [#$04]) then
  1693. begin
  1694. Matches:=0;
  1695. exit;
  1696. end;
  1697. { floating point size }
  1698. if (oppostfix in [PF_D,PF_E,PF_P,PF_EP]) and
  1699. not(p^.code[0] in []) then
  1700. begin
  1701. Matches:=0;
  1702. exit;
  1703. end;
  1704. { multiple load/store address modes }
  1705. if (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
  1706. not(p^.code[0] in [
  1707. // ldr,str,ldrb,strb
  1708. #$17,
  1709. // stm,ldm
  1710. #$26
  1711. ]) then
  1712. begin
  1713. Matches:=0;
  1714. exit;
  1715. end;
  1716. { we shouldn't see any opsize prefixes here }
  1717. if (oppostfix in [PF_B,PF_SB,PF_BT,PF_H,PF_SH,PF_T]) then
  1718. begin
  1719. Matches:=0;
  1720. exit;
  1721. end;
  1722. if (roundingmode<>RM_None) and not(p^.code[0] in []) then
  1723. begin
  1724. Matches:=0;
  1725. exit;
  1726. end;
  1727. { Check operand sizes }
  1728. { as default an untyped size can get all the sizes, this is different
  1729. from nasm, but else we need to do a lot checking which opcodes want
  1730. size or not with the automatic size generation }
  1731. (*
  1732. asize:=longint($ffffffff);
  1733. if (p^.flags and IF_SB)<>0 then
  1734. asize:=OT_BITS8
  1735. else if (p^.flags and IF_SW)<>0 then
  1736. asize:=OT_BITS16
  1737. else if (p^.flags and IF_SD)<>0 then
  1738. asize:=OT_BITS32;
  1739. if (p^.flags and IF_ARMASK)<>0 then
  1740. begin
  1741. siz[0]:=0;
  1742. siz[1]:=0;
  1743. siz[2]:=0;
  1744. if (p^.flags and IF_AR0)<>0 then
  1745. siz[0]:=asize
  1746. else if (p^.flags and IF_AR1)<>0 then
  1747. siz[1]:=asize
  1748. else if (p^.flags and IF_AR2)<>0 then
  1749. siz[2]:=asize;
  1750. end
  1751. else
  1752. begin
  1753. { we can leave because the size for all operands is forced to be
  1754. the same
  1755. but not if IF_SB IF_SW or IF_SD is set PM }
  1756. if asize=-1 then
  1757. exit;
  1758. siz[0]:=asize;
  1759. siz[1]:=asize;
  1760. siz[2]:=asize;
  1761. end;
  1762. if (p^.flags and (IF_SM or IF_SM2))<>0 then
  1763. begin
  1764. if (p^.flags and IF_SM2)<>0 then
  1765. oprs:=2
  1766. else
  1767. oprs:=p^.ops;
  1768. for i:=0 to oprs-1 do
  1769. if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
  1770. begin
  1771. for j:=0 to oprs-1 do
  1772. siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
  1773. break;
  1774. end;
  1775. end
  1776. else
  1777. oprs:=2;
  1778. { Check operand sizes }
  1779. for i:=0 to p^.ops-1 do
  1780. begin
  1781. if ((p^.optypes[i] and OT_SIZE_MASK)=0) and
  1782. ((oper[i]^.ot and OT_SIZE_MASK and (not siz[i]))<>0) and
  1783. { Immediates can always include smaller size }
  1784. ((oper[i]^.ot and OT_IMMEDIATE)=0) and
  1785. (((p^.optypes[i] and OT_SIZE_MASK) or siz[i])<(oper[i]^.ot and OT_SIZE_MASK)) then
  1786. Matches:=2;
  1787. end;
  1788. *)
  1789. end;
  1790. function taicpu.calcsize(p:PInsEntry):shortint;
  1791. begin
  1792. result:=4;
  1793. end;
  1794. function taicpu.NeedAddrPrefix(opidx:byte):boolean;
  1795. begin
  1796. Result:=False; { unimplemented }
  1797. end;
  1798. procedure taicpu.Swapoperands;
  1799. begin
  1800. end;
  1801. function taicpu.FindInsentry(objdata:TObjData):boolean;
  1802. var
  1803. i : longint;
  1804. begin
  1805. result:=false;
  1806. { Things which may only be done once, not when a second pass is done to
  1807. optimize }
  1808. if (Insentry=nil) or ((InsEntry^.flags and IF_PASS2)<>0) then
  1809. begin
  1810. { create the .ot fields }
  1811. create_ot(objdata);
  1812. { set the file postion }
  1813. current_filepos:=fileinfo;
  1814. end
  1815. else
  1816. begin
  1817. { we've already an insentry so it's valid }
  1818. result:=true;
  1819. exit;
  1820. end;
  1821. { Lookup opcode in the table }
  1822. InsSize:=-1;
  1823. i:=instabcache^[opcode];
  1824. if i=-1 then
  1825. begin
  1826. Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
  1827. exit;
  1828. end;
  1829. insentry:=@instab[i];
  1830. while (insentry^.opcode=opcode) do
  1831. begin
  1832. if matches(insentry)=100 then
  1833. begin
  1834. result:=true;
  1835. exit;
  1836. end;
  1837. inc(i);
  1838. insentry:=@instab[i];
  1839. end;
  1840. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1841. { No instruction found, set insentry to nil and inssize to -1 }
  1842. insentry:=nil;
  1843. inssize:=-1;
  1844. end;
  1845. procedure taicpu.gencode(objdata:TObjData);
  1846. var
  1847. bytes : dword;
  1848. i_field : byte;
  1849. procedure setshifterop(op : byte);
  1850. begin
  1851. case oper[op]^.typ of
  1852. top_const:
  1853. begin
  1854. i_field:=1;
  1855. bytes:=bytes or dword(oper[op]^.val and $fff);
  1856. end;
  1857. top_reg:
  1858. begin
  1859. i_field:=0;
  1860. bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16);
  1861. { does a real shifter op follow? }
  1862. if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then
  1863. begin
  1864. end;
  1865. end;
  1866. else
  1867. internalerror(2005091103);
  1868. end;
  1869. end;
  1870. begin
  1871. bytes:=$0;
  1872. { evaluate and set condition code }
  1873. { condition code allowed? }
  1874. { setup rest of the instruction }
  1875. case insentry^.code[0] of
  1876. #$08:
  1877. begin
  1878. { set instruction code }
  1879. bytes:=bytes or (ord(insentry^.code[1]) shl 26);
  1880. bytes:=bytes or (ord(insentry^.code[2]) shl 21);
  1881. { set destination }
  1882. bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
  1883. { create shifter op }
  1884. setshifterop(1);
  1885. { set i field }
  1886. bytes:=bytes or (i_field shl 25);
  1887. { set s if necessary }
  1888. if oppostfix=PF_S then
  1889. bytes:=bytes or (1 shl 20);
  1890. end;
  1891. #$ff:
  1892. internalerror(2005091101);
  1893. else
  1894. internalerror(2005091102);
  1895. end;
  1896. { we're finished, write code }
  1897. objdata.writebytes(bytes,sizeof(bytes));
  1898. end;
  1899. {$ifdef dummy}
  1900. (*
  1901. static void gencode (long segment, long offset, int bits,
  1902. insn *ins, char *codes, long insn_end)
  1903. {
  1904. int has_S_code; /* S - setflag */
  1905. int has_B_code; /* B - setflag */
  1906. int has_T_code; /* T - setflag */
  1907. int has_W_code; /* ! => W flag */
  1908. int has_F_code; /* ^ => S flag */
  1909. int keep;
  1910. unsigned char c;
  1911. unsigned char bytes[4];
  1912. long data, size;
  1913. static int cc_code[] = /* bit pattern of cc */
  1914. { /* order as enum in */
  1915. 0x0E, 0x03, 0x02, 0x00, /* nasm.h */
  1916. 0x0A, 0x0C, 0x08, 0x0D,
  1917. 0x09, 0x0B, 0x04, 0x01,
  1918. 0x05, 0x07, 0x06,
  1919. };
  1920. #ifdef DEBUG
  1921. static char *CC[] =
  1922. { /* condition code names */
  1923. "AL", "CC", "CS", "EQ",
  1924. "GE", "GT", "HI", "LE",
  1925. "LS", "LT", "MI", "NE",
  1926. "PL", "VC", "VS", "",
  1927. "S"
  1928. };
  1929. has_S_code = (ins->condition & C_SSETFLAG);
  1930. has_B_code = (ins->condition & C_BSETFLAG);
  1931. has_T_code = (ins->condition & C_TSETFLAG);
  1932. has_W_code = (ins->condition & C_EXSETFLAG);
  1933. has_F_code = (ins->condition & C_FSETFLAG);
  1934. ins->condition = (ins->condition & 0x0F);
  1935. if (rt_debug)
  1936. {
  1937. printf ("gencode: instruction: %s%s", insn_names[ins->opcode],
  1938. CC[ins->condition & 0x0F]);
  1939. if (has_S_code)
  1940. printf ("S");
  1941. if (has_B_code)
  1942. printf ("B");
  1943. if (has_T_code)
  1944. printf ("T");
  1945. if (has_W_code)
  1946. printf ("!");
  1947. if (has_F_code)
  1948. printf ("^");
  1949. printf ("\n");
  1950. c = *codes;
  1951. printf (" (%d) decode - '0x%02X'\n", ins->operands, c);
  1952. bytes[0] = 0xB;
  1953. bytes[1] = 0xE;
  1954. bytes[2] = 0xE;
  1955. bytes[3] = 0xF;
  1956. }
  1957. // First condition code in upper nibble
  1958. if (ins->condition < C_NONE)
  1959. {
  1960. c = cc_code[ins->condition] << 4;
  1961. }
  1962. else
  1963. {
  1964. c = cc_code[C_AL] << 4; // is often ALWAYS but not always
  1965. }
  1966. switch (keep = *codes)
  1967. {
  1968. case 1:
  1969. // B, BL
  1970. ++codes;
  1971. c |= *codes++;
  1972. bytes[0] = c;
  1973. if (ins->oprs[0].segment != segment)
  1974. {
  1975. // fais une relocation
  1976. c = 1;
  1977. data = 0; // Let the linker locate ??
  1978. }
  1979. else
  1980. {
  1981. c = 0;
  1982. data = ins->oprs[0].offset - (offset + 8);
  1983. if (data % 4)
  1984. {
  1985. errfunc (ERR_NONFATAL, "offset not aligned on 4 bytes");
  1986. }
  1987. }
  1988. if (data >= 0x1000)
  1989. {
  1990. errfunc (ERR_NONFATAL, "too long offset");
  1991. }
  1992. data = data >> 2;
  1993. bytes[1] = (data >> 16) & 0xFF;
  1994. bytes[2] = (data >> 8) & 0xFF;
  1995. bytes[3] = (data ) & 0xFF;
  1996. if (c == 1)
  1997. {
  1998. // out (offset, segment, &bytes[0], OUT_RAWDATA+1, NO_SEG, NO_SEG);
  1999. out (offset, segment, &bytes[0], OUT_REL3ADR+4, ins->oprs[0].segment, NO_SEG);
  2000. }
  2001. else
  2002. {
  2003. out (offset, segment, &bytes[0], OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2004. }
  2005. return;
  2006. case 2:
  2007. // SWI
  2008. ++codes;
  2009. c |= *codes++;
  2010. bytes[0] = c;
  2011. data = ins->oprs[0].offset;
  2012. bytes[1] = (data >> 16) & 0xFF;
  2013. bytes[2] = (data >> 8) & 0xFF;
  2014. bytes[3] = (data) & 0xFF;
  2015. out (offset, segment, &bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2016. return;
  2017. case 3:
  2018. // BX
  2019. ++codes;
  2020. c |= *codes++;
  2021. bytes[0] = c;
  2022. bytes[1] = *codes++;
  2023. bytes[2] = *codes++;
  2024. bytes[3] = *codes++;
  2025. c = regval (&ins->oprs[0],1);
  2026. if (c == 15) // PC
  2027. {
  2028. errfunc (ERR_WARNING, "'BX' with R15 has undefined behaviour");
  2029. }
  2030. else if (c > 15)
  2031. {
  2032. errfunc (ERR_NONFATAL, "Illegal register specified for 'BX'");
  2033. }
  2034. bytes[3] |= (c & 0x0F);
  2035. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2036. return;
  2037. case 4: // AND Rd,Rn,Rm
  2038. case 5: // AND Rd,Rn,Rm,<shift>Rs
  2039. case 6: // AND Rd,Rn,Rm,<shift>imm
  2040. case 7: // AND Rd,Rn,<shift>imm
  2041. ++codes;
  2042. #ifdef DEBUG
  2043. if (rt_debug)
  2044. {
  2045. printf (" decode - '0x%02X'\n", keep);
  2046. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  2047. }
  2048. #endif
  2049. bytes[0] = c | *codes;
  2050. ++codes;
  2051. bytes[1] = *codes;
  2052. if (has_S_code)
  2053. bytes[1] |= 0x10;
  2054. c = regval (&ins->oprs[1],1);
  2055. // Rn in low nibble
  2056. bytes[1] |= c;
  2057. // Rd in high nibble
  2058. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2059. if (keep != 7)
  2060. {
  2061. // Rm in low nibble
  2062. bytes[3] = regval (&ins->oprs[2],1);
  2063. }
  2064. // Shifts if any
  2065. if (keep == 5 || keep == 6)
  2066. {
  2067. // Shift in bytes 2 and 3
  2068. if (keep == 5)
  2069. {
  2070. // Rs
  2071. c = regval (&ins->oprs[3],1);
  2072. bytes[2] |= c;
  2073. c = 0x10; // Set bit 4 in byte[3]
  2074. }
  2075. if (keep == 6)
  2076. {
  2077. c = (ins->oprs[3].offset) & 0x1F;
  2078. // #imm
  2079. bytes[2] |= c >> 1;
  2080. if (c & 0x01)
  2081. {
  2082. bytes[3] |= 0x80;
  2083. }
  2084. c = 0; // Clr bit 4 in byte[3]
  2085. }
  2086. // <shift>
  2087. c |= shiftval (&ins->oprs[3]) << 5;
  2088. bytes[3] |= c;
  2089. }
  2090. // reg,reg,imm
  2091. if (keep == 7)
  2092. {
  2093. int shimm;
  2094. shimm = imm_shift (ins->oprs[2].offset);
  2095. if (shimm == -1)
  2096. {
  2097. errfunc (ERR_NONFATAL, "cannot create that constant");
  2098. }
  2099. bytes[3] = shimm & 0xFF;
  2100. bytes[2] |= (shimm & 0xF00) >> 8;
  2101. }
  2102. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2103. return;
  2104. case 8: // MOV Rd,Rm
  2105. case 9: // MOV Rd,Rm,<shift>Rs
  2106. case 0xA: // MOV Rd,Rm,<shift>imm
  2107. case 0xB: // MOV Rd,<shift>imm
  2108. ++codes;
  2109. #ifdef DEBUG
  2110. if (rt_debug)
  2111. {
  2112. printf (" decode - '0x%02X'\n", keep);
  2113. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  2114. }
  2115. #endif
  2116. bytes[0] = c | *codes;
  2117. ++codes;
  2118. bytes[1] = *codes;
  2119. if (has_S_code)
  2120. bytes[1] |= 0x10;
  2121. // Rd in high nibble
  2122. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2123. if (keep != 0x0B)
  2124. {
  2125. // Rm in low nibble
  2126. bytes[3] = regval (&ins->oprs[1],1);
  2127. }
  2128. // Shifts if any
  2129. if (keep == 0x09 || keep == 0x0A)
  2130. {
  2131. // Shift in bytes 2 and 3
  2132. if (keep == 0x09)
  2133. {
  2134. // Rs
  2135. c = regval (&ins->oprs[2],1);
  2136. bytes[2] |= c;
  2137. c = 0x10; // Set bit 4 in byte[3]
  2138. }
  2139. if (keep == 0x0A)
  2140. {
  2141. c = (ins->oprs[2].offset) & 0x1F;
  2142. // #imm
  2143. bytes[2] |= c >> 1;
  2144. if (c & 0x01)
  2145. {
  2146. bytes[3] |= 0x80;
  2147. }
  2148. c = 0; // Clr bit 4 in byte[3]
  2149. }
  2150. // <shift>
  2151. c |= shiftval (&ins->oprs[2]) << 5;
  2152. bytes[3] |= c;
  2153. }
  2154. // reg,imm
  2155. if (keep == 0x0B)
  2156. {
  2157. int shimm;
  2158. shimm = imm_shift (ins->oprs[1].offset);
  2159. if (shimm == -1)
  2160. {
  2161. errfunc (ERR_NONFATAL, "cannot create that constant");
  2162. }
  2163. bytes[3] = shimm & 0xFF;
  2164. bytes[2] |= (shimm & 0xF00) >> 8;
  2165. }
  2166. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2167. return;
  2168. case 0xC: // CMP Rn,Rm
  2169. case 0xD: // CMP Rn,Rm,<shift>Rs
  2170. case 0xE: // CMP Rn,Rm,<shift>imm
  2171. case 0xF: // CMP Rn,<shift>imm
  2172. ++codes;
  2173. bytes[0] = c | *codes++;
  2174. bytes[1] = *codes;
  2175. // Implicit S code
  2176. bytes[1] |= 0x10;
  2177. c = regval (&ins->oprs[0],1);
  2178. // Rn in low nibble
  2179. bytes[1] |= c;
  2180. // No destination
  2181. bytes[2] = 0;
  2182. if (keep != 0x0B)
  2183. {
  2184. // Rm in low nibble
  2185. bytes[3] = regval (&ins->oprs[1],1);
  2186. }
  2187. // Shifts if any
  2188. if (keep == 0x0D || keep == 0x0E)
  2189. {
  2190. // Shift in bytes 2 and 3
  2191. if (keep == 0x0D)
  2192. {
  2193. // Rs
  2194. c = regval (&ins->oprs[2],1);
  2195. bytes[2] |= c;
  2196. c = 0x10; // Set bit 4 in byte[3]
  2197. }
  2198. if (keep == 0x0E)
  2199. {
  2200. c = (ins->oprs[2].offset) & 0x1F;
  2201. // #imm
  2202. bytes[2] |= c >> 1;
  2203. if (c & 0x01)
  2204. {
  2205. bytes[3] |= 0x80;
  2206. }
  2207. c = 0; // Clr bit 4 in byte[3]
  2208. }
  2209. // <shift>
  2210. c |= shiftval (&ins->oprs[2]) << 5;
  2211. bytes[3] |= c;
  2212. }
  2213. // reg,imm
  2214. if (keep == 0x0F)
  2215. {
  2216. int shimm;
  2217. shimm = imm_shift (ins->oprs[1].offset);
  2218. if (shimm == -1)
  2219. {
  2220. errfunc (ERR_NONFATAL, "cannot create that constant");
  2221. }
  2222. bytes[3] = shimm & 0xFF;
  2223. bytes[2] |= (shimm & 0xF00) >> 8;
  2224. }
  2225. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2226. return;
  2227. case 0x10: // MRS Rd,<psr>
  2228. ++codes;
  2229. bytes[0] = c | *codes++;
  2230. bytes[1] = *codes++;
  2231. // Rd
  2232. c = regval (&ins->oprs[0],1);
  2233. bytes[2] = c << 4;
  2234. bytes[3] = 0;
  2235. c = ins->oprs[1].basereg;
  2236. if (c == R_CPSR || c == R_SPSR)
  2237. {
  2238. if (c == R_SPSR)
  2239. {
  2240. bytes[1] |= 0x40;
  2241. }
  2242. }
  2243. else
  2244. {
  2245. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  2246. }
  2247. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2248. return;
  2249. case 0x11: // MSR <psr>,Rm
  2250. case 0x12: // MSR <psrf>,Rm
  2251. case 0x13: // MSR <psrf>,#expression
  2252. ++codes;
  2253. bytes[0] = c | *codes++;
  2254. bytes[1] = *codes++;
  2255. bytes[2] = *codes;
  2256. if (keep == 0x11 || keep == 0x12)
  2257. {
  2258. // Rm
  2259. c = regval (&ins->oprs[1],1);
  2260. bytes[3] = c;
  2261. }
  2262. else
  2263. {
  2264. int shimm;
  2265. shimm = imm_shift (ins->oprs[1].offset);
  2266. if (shimm == -1)
  2267. {
  2268. errfunc (ERR_NONFATAL, "cannot create that constant");
  2269. }
  2270. bytes[3] = shimm & 0xFF;
  2271. bytes[2] |= (shimm & 0xF00) >> 8;
  2272. }
  2273. c = ins->oprs[0].basereg;
  2274. if ( keep == 0x11)
  2275. {
  2276. if ( c == R_CPSR || c == R_SPSR)
  2277. {
  2278. if ( c== R_SPSR)
  2279. {
  2280. bytes[1] |= 0x40;
  2281. }
  2282. }
  2283. else
  2284. {
  2285. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  2286. }
  2287. }
  2288. else
  2289. {
  2290. if ( c == R_CPSR_FLG || c == R_SPSR_FLG)
  2291. {
  2292. if ( c== R_SPSR_FLG)
  2293. {
  2294. bytes[1] |= 0x40;
  2295. }
  2296. }
  2297. else
  2298. {
  2299. errfunc (ERR_NONFATAL, "CPSR_flg or SPSR_flg expected");
  2300. }
  2301. }
  2302. break;
  2303. case 0x14: // MUL Rd,Rm,Rs
  2304. case 0x15: // MULA Rd,Rm,Rs,Rn
  2305. ++codes;
  2306. bytes[0] = c | *codes++;
  2307. bytes[1] = *codes++;
  2308. bytes[3] = *codes;
  2309. // Rd
  2310. bytes[1] |= regval (&ins->oprs[0],1);
  2311. if (has_S_code)
  2312. bytes[1] |= 0x10;
  2313. // Rm
  2314. bytes[3] |= regval (&ins->oprs[1],1);
  2315. // Rs
  2316. bytes[2] = regval (&ins->oprs[2],1);
  2317. if (keep == 0x15)
  2318. {
  2319. bytes[2] |= regval (&ins->oprs[3],1) << 4;
  2320. }
  2321. break;
  2322. case 0x16: // SMLAL RdHi,RdLo,Rm,Rs
  2323. ++codes;
  2324. bytes[0] = c | *codes++;
  2325. bytes[1] = *codes++;
  2326. bytes[3] = *codes;
  2327. // RdHi
  2328. bytes[1] |= regval (&ins->oprs[1],1);
  2329. if (has_S_code)
  2330. bytes[1] |= 0x10;
  2331. // RdLo
  2332. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2333. // Rm
  2334. bytes[3] |= regval (&ins->oprs[2],1);
  2335. // Rs
  2336. bytes[2] |= regval (&ins->oprs[3],1);
  2337. break;
  2338. case 0x17: // LDR Rd, expression
  2339. ++codes;
  2340. bytes[0] = c | *codes++;
  2341. bytes[1] = *codes++;
  2342. // Rd
  2343. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2344. if (has_B_code)
  2345. bytes[1] |= 0x40;
  2346. if (has_T_code)
  2347. {
  2348. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  2349. }
  2350. if (has_W_code)
  2351. {
  2352. errfunc (ERR_NONFATAL, "'!' not allowed");
  2353. }
  2354. // Rn - implicit R15
  2355. bytes[1] |= 0xF;
  2356. if (ins->oprs[1].segment != segment)
  2357. {
  2358. errfunc (ERR_NONFATAL, "label not in same segment");
  2359. }
  2360. data = ins->oprs[1].offset - (offset + 8);
  2361. if (data < 0)
  2362. {
  2363. data = -data;
  2364. }
  2365. else
  2366. {
  2367. bytes[1] |= 0x80;
  2368. }
  2369. if (data >= 0x1000)
  2370. {
  2371. errfunc (ERR_NONFATAL, "too long offset");
  2372. }
  2373. bytes[2] |= ((data & 0xF00) >> 8);
  2374. bytes[3] = data & 0xFF;
  2375. break;
  2376. case 0x18: // LDR Rd, [Rn]
  2377. ++codes;
  2378. bytes[0] = c | *codes++;
  2379. bytes[1] = *codes++;
  2380. // Rd
  2381. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2382. if (has_B_code)
  2383. bytes[1] |= 0x40;
  2384. if (has_T_code)
  2385. {
  2386. bytes[1] |= 0x20; // write-back
  2387. }
  2388. else
  2389. {
  2390. bytes[0] |= 0x01; // implicit pre-index mode
  2391. }
  2392. if (has_W_code)
  2393. {
  2394. bytes[1] |= 0x20; // write-back
  2395. }
  2396. // Rn
  2397. c = regval (&ins->oprs[1],1);
  2398. bytes[1] |= c;
  2399. if (c == 0x15) // R15
  2400. data = -8;
  2401. else
  2402. data = 0;
  2403. if (data < 0)
  2404. {
  2405. data = -data;
  2406. }
  2407. else
  2408. {
  2409. bytes[1] |= 0x80;
  2410. }
  2411. bytes[2] |= ((data & 0xF00) >> 8);
  2412. bytes[3] = data & 0xFF;
  2413. break;
  2414. case 0x19: // LDR Rd, [Rn,#expression]
  2415. case 0x20: // LDR Rd, [Rn,Rm]
  2416. case 0x21: // LDR Rd, [Rn,Rm,shift]
  2417. ++codes;
  2418. bytes[0] = c | *codes++;
  2419. bytes[1] = *codes++;
  2420. // Rd
  2421. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2422. if (has_B_code)
  2423. bytes[1] |= 0x40;
  2424. // Rn
  2425. c = regval (&ins->oprs[1],1);
  2426. bytes[1] |= c;
  2427. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  2428. {
  2429. bytes[0] |= 0x01; // pre-index mode
  2430. if (has_W_code)
  2431. {
  2432. bytes[1] |= 0x20;
  2433. }
  2434. if (has_T_code)
  2435. {
  2436. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  2437. }
  2438. }
  2439. else
  2440. {
  2441. if (has_T_code) // Forced write-back in post-index mode
  2442. {
  2443. bytes[1] |= 0x20;
  2444. }
  2445. if (has_W_code)
  2446. {
  2447. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  2448. }
  2449. }
  2450. if (keep == 0x19)
  2451. {
  2452. data = ins->oprs[2].offset;
  2453. if (data < 0)
  2454. {
  2455. data = -data;
  2456. }
  2457. else
  2458. {
  2459. bytes[1] |= 0x80;
  2460. }
  2461. if (data >= 0x1000)
  2462. {
  2463. errfunc (ERR_NONFATAL, "too long offset");
  2464. }
  2465. bytes[2] |= ((data & 0xF00) >> 8);
  2466. bytes[3] = data & 0xFF;
  2467. }
  2468. else
  2469. {
  2470. if (ins->oprs[2].minus == 0)
  2471. {
  2472. bytes[1] |= 0x80;
  2473. }
  2474. c = regval (&ins->oprs[2],1);
  2475. bytes[3] = c;
  2476. if (keep == 0x21)
  2477. {
  2478. c = ins->oprs[3].offset;
  2479. if (c > 0x1F)
  2480. {
  2481. errfunc (ERR_NONFATAL, "too large shiftvalue");
  2482. c = c & 0x1F;
  2483. }
  2484. bytes[2] |= c >> 1;
  2485. if (c & 0x01)
  2486. {
  2487. bytes[3] |= 0x80;
  2488. }
  2489. bytes[3] |= shiftval (&ins->oprs[3]) << 5;
  2490. }
  2491. }
  2492. break;
  2493. case 0x22: // LDRH Rd, expression
  2494. ++codes;
  2495. bytes[0] = c | 0x01; // Implicit pre-index
  2496. bytes[1] = *codes++;
  2497. // Rd
  2498. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2499. // Rn - implicit R15
  2500. bytes[1] |= 0xF;
  2501. if (ins->oprs[1].segment != segment)
  2502. {
  2503. errfunc (ERR_NONFATAL, "label not in same segment");
  2504. }
  2505. data = ins->oprs[1].offset - (offset + 8);
  2506. if (data < 0)
  2507. {
  2508. data = -data;
  2509. }
  2510. else
  2511. {
  2512. bytes[1] |= 0x80;
  2513. }
  2514. if (data >= 0x100)
  2515. {
  2516. errfunc (ERR_NONFATAL, "too long offset");
  2517. }
  2518. bytes[3] = *codes++;
  2519. bytes[2] |= ((data & 0xF0) >> 4);
  2520. bytes[3] |= data & 0xF;
  2521. break;
  2522. case 0x23: // LDRH Rd, Rn
  2523. ++codes;
  2524. bytes[0] = c | 0x01; // Implicit pre-index
  2525. bytes[1] = *codes++;
  2526. // Rd
  2527. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2528. // Rn
  2529. c = regval (&ins->oprs[1],1);
  2530. bytes[1] |= c;
  2531. if (c == 0x15) // R15
  2532. data = -8;
  2533. else
  2534. data = 0;
  2535. if (data < 0)
  2536. {
  2537. data = -data;
  2538. }
  2539. else
  2540. {
  2541. bytes[1] |= 0x80;
  2542. }
  2543. if (data >= 0x100)
  2544. {
  2545. errfunc (ERR_NONFATAL, "too long offset");
  2546. }
  2547. bytes[3] = *codes++;
  2548. bytes[2] |= ((data & 0xF0) >> 4);
  2549. bytes[3] |= data & 0xF;
  2550. break;
  2551. case 0x24: // LDRH Rd, Rn, expression
  2552. case 0x25: // LDRH Rd, Rn, Rm
  2553. ++codes;
  2554. bytes[0] = c;
  2555. bytes[1] = *codes++;
  2556. // Rd
  2557. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2558. // Rn
  2559. c = regval (&ins->oprs[1],1);
  2560. bytes[1] |= c;
  2561. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  2562. {
  2563. bytes[0] |= 0x01; // pre-index mode
  2564. if (has_W_code)
  2565. {
  2566. bytes[1] |= 0x20;
  2567. }
  2568. }
  2569. else
  2570. {
  2571. if (has_W_code)
  2572. {
  2573. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  2574. }
  2575. }
  2576. bytes[3] = *codes++;
  2577. if (keep == 0x24)
  2578. {
  2579. data = ins->oprs[2].offset;
  2580. if (data < 0)
  2581. {
  2582. data = -data;
  2583. }
  2584. else
  2585. {
  2586. bytes[1] |= 0x80;
  2587. }
  2588. if (data >= 0x100)
  2589. {
  2590. errfunc (ERR_NONFATAL, "too long offset");
  2591. }
  2592. bytes[2] |= ((data & 0xF0) >> 4);
  2593. bytes[3] |= data & 0xF;
  2594. }
  2595. else
  2596. {
  2597. if (ins->oprs[2].minus == 0)
  2598. {
  2599. bytes[1] |= 0x80;
  2600. }
  2601. c = regval (&ins->oprs[2],1);
  2602. bytes[3] |= c;
  2603. }
  2604. break;
  2605. case 0x26: // LDM/STM Rn, {reg-list}
  2606. ++codes;
  2607. bytes[0] = c;
  2608. bytes[0] |= ( *codes >> 4) & 0xF;
  2609. bytes[1] = ( *codes << 4) & 0xF0;
  2610. ++codes;
  2611. if (has_W_code)
  2612. {
  2613. bytes[1] |= 0x20;
  2614. }
  2615. if (has_F_code)
  2616. {
  2617. bytes[1] |= 0x40;
  2618. }
  2619. // Rn
  2620. bytes[1] |= regval (&ins->oprs[0],1);
  2621. data = ins->oprs[1].basereg;
  2622. bytes[2] = ((data >> 8) & 0xFF);
  2623. bytes[3] = (data & 0xFF);
  2624. break;
  2625. case 0x27: // SWP Rd, Rm, [Rn]
  2626. ++codes;
  2627. bytes[0] = c;
  2628. bytes[0] |= *codes++;
  2629. bytes[1] = regval (&ins->oprs[2],1);
  2630. if (has_B_code)
  2631. {
  2632. bytes[1] |= 0x40;
  2633. }
  2634. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2635. bytes[3] = *codes++;
  2636. bytes[3] |= regval (&ins->oprs[1],1);
  2637. break;
  2638. default:
  2639. errfunc (ERR_FATAL, "unknown decoding of instruction");
  2640. bytes[0] = c;
  2641. // And a fix nibble
  2642. ++codes;
  2643. bytes[0] |= *codes++;
  2644. if ( *codes == 0x01) // An I bit
  2645. {
  2646. }
  2647. if ( *codes == 0x02) // An I bit
  2648. {
  2649. }
  2650. ++codes;
  2651. }
  2652. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2653. }
  2654. *)
  2655. {$endif dummy}
  2656. constructor tai_thumb_func.create;
  2657. begin
  2658. inherited create;
  2659. typ:=ait_thumb_func;
  2660. end;
  2661. begin
  2662. cai_align:=tai_align;
  2663. end.