m68k.inc 16 KB

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  1. {
  2. This file is part of the Free Pascal run time library.
  3. Copyright (c) 1999-2000 by Carl-Eric Codere,
  4. member of the Free Pascal development team.
  5. See the file COPYING.FPC, included in this distribution,
  6. for details about the copyright.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  10. **********************************************************************}
  11. {****************************************************************************
  12. m68k.inc : Processor dependent implementation of system unit
  13. For Motorola 680x0 Processor.
  14. *****************************************************************************}
  15. {****************************************************************************}
  16. { Credit where credit is due: }
  17. { -Some of the copy routines taken from the Atari dlib source code: }
  18. { Dale Schumacher (alias: Dalnefre') [email protected] }
  19. { 399 Beacon Ave. St. Paul, MN 55104,USA }
  20. { -Some of the routines taken from the freeware ATARI Sozobon C compiler }
  21. { 1988 by Sozobon, Limited. Author: Johann Ruegg (freeware) }
  22. { Thanks to all these people wherever they maybe today! }
  23. {****************************************************************************}
  24. { 68881/2 FPCR Encodings
  25. Rounding Mode Rounding Precision
  26. (RND Field) Encoding (PREC Field)
  27. To Nearest (RN) 0 0 Extend (X)
  28. To Zero (RZ) 0 1 Single (S)
  29. To Minus Infinity (RM) 1 0 Double (D)
  30. To Plus Infinity (RP) 1 1 Undefined
  31. }
  32. { 68881/2 FPCR layout }
  33. { Exception Enable Byte: }
  34. { 15 - BSUN - Branch/Set on Unordered }
  35. { 14 - SNAN - Signal Not A Number }
  36. { 13 - OPERR - Operand Error }
  37. { 12 - OVFL - Overflow }
  38. { 11 - UNFL - Underflow }
  39. { 10 - DZ - Divide by Zero }
  40. { 09 - INEX2 - Inexact Operation }
  41. { 08 - INEX1 - Inexact Decimal Input }
  42. { Mode Control Byte: }
  43. { 07 - PREC - Rounding Precision }
  44. { 06 - PREC - Rounding Precision }
  45. { 05 - RND - Rounding Mode }
  46. { 04 - RND - Rounding Mode }
  47. { 03 - 0 - Reserved, Set to zero }
  48. { 02 - 0 - Reserved, Set to zero }
  49. { 01 - 0 - Reserved, Set to zero }
  50. { 00 - 0 - Reserved, Set to zero }
  51. {$IFDEF FPU68881}
  52. {$DEFINE FPC_SYSTEM_HAS_SYSRESETFPU}
  53. procedure SysResetFPU; assembler;
  54. asm
  55. clr.l d0
  56. fmove.l d0,fpcr
  57. end;
  58. {$DEFINE FPC_SYSTEM_HAS_SYSINITFPU}
  59. procedure SysInitFPU; assembler;
  60. asm
  61. clr.l d0
  62. // FIX ME:
  63. // move.w 0,d0 // enable a sane set of exception flags here
  64. fmove.l d0,fpcr
  65. end;
  66. {$ENDIF}
  67. procedure fpc_cpuinit;
  68. begin
  69. SysResetFPU;
  70. if (not IsLibrary) then
  71. SysInitFPU;
  72. end;
  73. {$define FPC_SYSTEM_HAS_GET_FRAME}
  74. function get_frame : pointer; assembler;nostackframe;
  75. asm
  76. {$if defined(amiga)}
  77. move.l a5,d0
  78. {$else}
  79. move.l a6,d0
  80. {$endif}
  81. end;
  82. {$define FPC_SYSTEM_HAS_GET_CALLER_ADDR}
  83. function get_caller_addr(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  84. asm
  85. move.l framebp,d0
  86. tst.l d0
  87. beq @Lnul_address
  88. move.l d0,a0
  89. move.l 4(a0),d0
  90. @Lnul_address:
  91. end;
  92. {$define FPC_SYSTEM_HAS_GET_CALLER_FRAME}
  93. function get_caller_frame(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  94. asm
  95. move.l framebp,d0
  96. tst.l d0
  97. beq @Lnul_frame
  98. move.l d0,a0
  99. move.l (a0),d0
  100. @Lnul_frame:
  101. end;
  102. {$define FPC_SYSTEM_HAS_SPTR}
  103. function Sptr : pointer; assembler;nostackframe;
  104. asm
  105. move.l sp,d0
  106. end;
  107. {$define FPC_SYSTEM_HAS_GET_PC_ADDR}
  108. function get_pc_addr : pointer;assembler;nostackframe;
  109. asm
  110. move.l (sp),d0
  111. end;
  112. {$define FPC_SYSTEM_HAS_FILLCHAR}
  113. procedure FillChar(var x; count : longint; value : byte); assembler;
  114. asm
  115. move.l x, a0 { destination }
  116. move.b value, d1 { fill data }
  117. move.l count, d0 { number of bytes to fill }
  118. ble @LMEMSET5 { anything to fill at all? }
  119. {$ifdef CPUM68K_HAS_DBRA}
  120. { FIXME: Any reason why not always just use DBRA mode on
  121. CPUs which support it? (KB)
  122. - DBRA does only 16-bit decrements, so handling more than 65535 bytes
  123. requires additional code anyway (Sergei) }
  124. cmpi.l #65535, d0 { check, if this is a word move }
  125. ble @LMEMSET3 { use fast dbra mode }
  126. {$endif CPUM68K_HAS_DBRA}
  127. bra @LMEMSET2
  128. @LMEMSET1:
  129. move.b d1,(a0)+
  130. @LMEMSET2:
  131. subq.l #1,d0
  132. bpl @LMEMSET1
  133. bra @LMEMSET5 { finished slow mode , exit }
  134. {$ifdef CPUM68K_HAS_DBRA}
  135. @LMEMSET4: { fast loop mode section 68010+ }
  136. move.b d1,(a0)+
  137. @LMEMSET3:
  138. dbra d0,@LMEMSET4
  139. {$endif CPUM68K_HAS_DBRA}
  140. @LMEMSET5:
  141. end;
  142. {$ifdef dummy}
  143. { procedure strcopy(dstr,sstr : pointer;len : longint);[public,alias: 'STRCOPY'];}
  144. procedure strcopy; assembler;[public,alias: 'FPC_STRCOPY'];
  145. {---------------------------------------------------}
  146. { Low-level routine to copy a string to another }
  147. { string with maximum length. Never call directly! }
  148. { On Entry: }
  149. { a1.l = string to copy to }
  150. { a0.l = source string }
  151. { d0.l = maximum length of copy }
  152. { registers destroyed: a0,a1,d0,d1 }
  153. {---------------------------------------------------}
  154. asm
  155. { move.l sstr,a0
  156. move.l dstr,a1
  157. move.l len,d1 }
  158. move.l d0,d1
  159. move.b (a0)+,d0 { Get source length }
  160. and.w #$ff,d0
  161. cmp.w d1,d0 { This is a signed comparison! }
  162. ble @LM4
  163. move.b d1,d0 { If longer than maximum size of target, cut
  164. source length }
  165. @LM4:
  166. andi.l #$ff,d0 { zero extend d0-byte }
  167. move.l d0,d1 { save length to copy }
  168. move.b d0,(a1)+ { save new length }
  169. { Check if copying length is zero - if so then }
  170. { exit without copying anything. }
  171. tst.b d1
  172. beq @Lend
  173. bra @LMSTRCOPY55
  174. @LMSTRCOPY56: { 68010 Fast loop mode }
  175. move.b (a0)+,(a1)+
  176. @LMSTRCOPY55:
  177. {$ifndef CPUM68K_HAS_DBRA}
  178. sub.l #1,d1
  179. bpl @LMSTRCOPY56
  180. {$else CPUM68K_HAS_DBRA}
  181. dbra d1,@LMSTRCOPY56
  182. {$endif CPUM68K_HAS_DBRA}
  183. @Lend:
  184. end;
  185. { Concatenate Strings }
  186. { PARAMETERS ARE REVERSED COMPARED TO NORMAL! }
  187. { therefore online assembler may not parse the params as normal }
  188. procedure strconcat(s1,s2 : pointer);[public,alias: 'STRCONCAT'];
  189. begin
  190. asm
  191. move.b #255,d0
  192. move.l s1,a0 { a0 = destination }
  193. move.l s2,a1 { a1 = source }
  194. sub.b (a0),d0 { copyl:= 255 -length(s1) }
  195. move.b (a1),d6
  196. and.w #$ff,d0 { Sign flags are checked! }
  197. and.w #$ff,d6
  198. cmp.w d6,d0 { if copyl > length(s2) then }
  199. ble @Lcontinue
  200. move.b (a1),d0 { copyl:=length(s2) }
  201. @Lcontinue:
  202. move.b (a0),d6
  203. and.l #$ff,d6
  204. lea 1(a0,d6),a0 { s1[length(s1)+1] }
  205. add.l #1,a1 { s2[1] }
  206. move.b d0,d6
  207. { Check if copying length is zero - if so then }
  208. { exit without copying anything. }
  209. tst.b d6
  210. beq @Lend
  211. bra @ALoop
  212. @Loop:
  213. move.b (a1)+,(a0)+ { s1[i] := s2[i]; }
  214. @ALoop:
  215. {$ifndef CPUM68K_HAS_DBRA}
  216. sub.l #1,d6
  217. bpl @Loop
  218. {$else CPUM68K_HAS_DBRA}
  219. dbra d6,@Loop
  220. {$endif CPUM68K_HAS_DBRA}
  221. move.l s1,a0
  222. add.b d0,(a0) { change to new string length }
  223. @Lend:
  224. end ['d0','d1','a0','a1','d6'];
  225. end;
  226. { Compares strings }
  227. { DO NOT CALL directly. }
  228. { a0 = pointer to first string to compare }
  229. { a1 = pointer to second string to compare }
  230. { ALL FLAGS are set appropriately. }
  231. { ZF = strings are equal }
  232. { REGISTERS DESTROYED: a0, a1, d0, d1, d6 }
  233. procedure strcmp; assembler;[public,alias:'FPC_STRCMP'];
  234. asm
  235. move.b (a0)+,d0 { Get length of first string }
  236. move.b (a1)+,d6 { Get length of 2nd string }
  237. move.b d6,d1 { Save length of string for final compare }
  238. cmp.b d0,d6 { Get shortest string length }
  239. ble @LSTRCONCAT1
  240. move.b d0,d6 { Set length to shortest string }
  241. @LSTRCONCAT1:
  242. tst.b d6 { Both strings have a length of zero, exit }
  243. beq @LSTRCONCAT2
  244. andi.l #$ff,d6
  245. subq.l #1,d6 { subtract first attempt }
  246. { if value is -1 then don't loop and just compare lengths of }
  247. { both strings before exiting. }
  248. bmi @LSTRCONCAT2
  249. or.l d0,d0 { Make sure to set Zerfo flag to 0 }
  250. @LSTRCONCAT5:
  251. { Workaroung for GAS v.134 bug }
  252. { old: cmp.b (a1)+,(a0)+ }
  253. cmpm.b (a1)+,(a0)+
  254. @LSTRCONCAT4:
  255. dbne d6,@LSTRCONCAT5 { Repeat until not equal }
  256. bne @LSTRCONCAT3
  257. @LSTRCONCAT2:
  258. { If length of both string are equal }
  259. { Then set zero flag }
  260. cmp.b d1,d0 { Compare length - set flag if equal length strings }
  261. @LSTRCONCAT3:
  262. end;
  263. {$endif dummy}
  264. {$define FPC_SYSTEM_HAS_MOVE}
  265. procedure move(const source;var dest;count : longint); assembler;
  266. { base pointer+8 = source }
  267. { base pointer+12 = destination }
  268. { base pointer+16 = number of bytes to move}
  269. asm
  270. move.l count, d0 { number of bytes }
  271. ble @LMOVE5 { anything to copy at all? }
  272. move.l dest, a1 { destination }
  273. move.l source, a0 { source }
  274. {$ifdef CPUM68K_HAS_DBRA}
  275. cmpi.l #65535, d0 { check, if this is a word move }
  276. ble @LMEMSET00 { use fast dbra mode 68010+ }
  277. {$endif CPUM68K_HAS_DBRA}
  278. cmp.l a0,a1 { check copy direction }
  279. bls @LMOVE3
  280. add.l d0,a0 { move pointers to end }
  281. add.l d0,a1
  282. @LMOVE1:
  283. move.b -(a0),-(a1) { (s < d) copy loop }
  284. subq.l #1,d0
  285. bne @LMOVE1
  286. bra @LMOVE5
  287. @LMOVE3:
  288. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  289. subq.l #1,d0
  290. bne @LMOVE3
  291. bra @LMOVE5
  292. {$ifdef CPUM68K_HAS_DBRA}
  293. @LMEMSET00: { use fast loop mode 68010+ }
  294. cmp.l a0,a1 { check copy direction }
  295. bls @LMOVE04
  296. add.l d0,a0 { move pointers to end }
  297. add.l d0,a1
  298. bra @LMOVE02
  299. @LMOVE01:
  300. move.b -(a0),-(a1) { (s < d) copy loop }
  301. @LMOVE02:
  302. dbra d0,@LMOVE01
  303. bra @LMOVE5
  304. @LMOVE03:
  305. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  306. @LMOVE04:
  307. dbra d0,@LMOVE03
  308. {$endif CPUM68K_HAS_DBRA}
  309. { end fast loop mode }
  310. @LMOVE5:
  311. end;
  312. {$ifdef CPUM68K_HAS_UNALIGNED}
  313. {$define FPC_SYSTEM_HAS_FILLWORD}
  314. procedure FillWord(var x; count : longint; value : word); assembler;
  315. asm
  316. move.l x, a0 { destination }
  317. move.w value, d1 { fill data }
  318. move.l count, d0 { number of bytes to fill }
  319. ble @LMEMSET3 { anything to fill at all? }
  320. bra @LMEMSET21
  321. @LMEMSET11:
  322. move.w d1,(a0)+
  323. @LMEMSET21:
  324. subq.l #1,d0
  325. bpl @LMEMSET11
  326. @LMEMSET3:
  327. end;
  328. {$endif}
  329. {$IFNDEF HASAMIGA}
  330. function InterLockedDecrement (var Target: longint) : longint;
  331. begin
  332. {$warning FIX ME}
  333. Dec(Target);
  334. Result := Target;
  335. end;
  336. function InterLockedIncrement (var Target: longint) : longint;
  337. begin
  338. {$warning FIX ME}
  339. Inc(Target);
  340. Result := Target;
  341. end;
  342. function InterLockedExchange (var Target: longint;Source : longint) : longint;
  343. begin
  344. {$warning FIX ME}
  345. Result := Target;
  346. Target := Source;
  347. end;
  348. function InterLockedExchangeAdd (var Target: longint;Source : longint) : longint;
  349. begin
  350. {$warning FIX ME}
  351. Result := Target;
  352. Target := Target + Source;
  353. end;
  354. function InterlockedCompareExchange(var Target: longint; NewValue: longint; Comperand: longint): longint;
  355. begin
  356. {$warning FIX ME}
  357. Result := Target;
  358. if Target = Comperand then
  359. Target := NewValue;
  360. end;
  361. {$ENDIF HASAMIGA}
  362. {$if defined(CPUM68K_HAS_BYTEREV) or defined(CPUM68K_HAS_ROLROR)}
  363. { Disabled for now, because not all cases below were tested. (KB) }
  364. {.$define FPC_SYSTEM_HAS_SWAPENDIAN}
  365. {$endif}
  366. {$if defined(FPC_SYSTEM_HAS_SWAPENDIAN)}
  367. function SwapEndian(const AValue: SmallInt): SmallInt; assembler; nostackframe;
  368. asm
  369. {$if defined(CPUM68K_HAS_ROLROR)}
  370. move.w avalue, d0
  371. ror.w #8, d0
  372. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  373. move.w avalue, d0
  374. byterev d0
  375. swap d0
  376. {$else}
  377. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  378. clr.l d0
  379. move.w avalue, d0
  380. move.w d0, d1
  381. lsr.l #8, d0
  382. lsl.l #8, d1
  383. or.l d1, d0
  384. {$endif}
  385. end;
  386. function SwapEndian(const AValue: Word): Word; assembler; nostackframe;
  387. asm
  388. {$if defined(CPUM68K_HAS_ROLROR)}
  389. move.w avalue, d0
  390. ror.w #8, d0
  391. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  392. move.w avalue, d0
  393. byterev d0
  394. swap d0
  395. {$else}
  396. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  397. clr.l d0
  398. move.w avalue, d0
  399. move.w d0, d1
  400. lsr.l #8, d0
  401. lsl.l #8, d1
  402. or.l d1, d0
  403. {$endif}
  404. end;
  405. function SwapEndian(const AValue: LongInt): LongInt; assembler; nostackframe;
  406. asm
  407. {$if defined(CPUM68K_HAS_ROLROR)}
  408. move.l avalue, d0
  409. ror.w #8, d0
  410. swap d0
  411. ror.w #8, d0
  412. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  413. move.l avalue, d0
  414. byterev d0
  415. {$else}
  416. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  417. move.l avalue, d0
  418. move.l d0, d1
  419. andi.l #$ff00ff00, d0
  420. andi.l #$00ff00ff, d1
  421. lsr.l #8, d0
  422. lsl.l #8, d1
  423. or.l d1, d0
  424. swap d0
  425. {$endif}
  426. end;
  427. function SwapEndian(const AValue: DWord): DWord; assembler; nostackframe;
  428. asm
  429. {$if defined(CPUM68K_HAS_ROLROR)}
  430. move.l avalue, d0
  431. ror.w #8, d0
  432. swap d0
  433. ror.w #8, d0
  434. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  435. move.l avalue, d0
  436. byterev d0
  437. {$else}
  438. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  439. move.l avalue, d0
  440. move.l d0, d1
  441. andi.l #$ff00ff00, d0
  442. andi.l #$00ff00ff, d1
  443. lsr.l #8, d0
  444. lsl.l #8, d1
  445. or.l d1, d0
  446. swap d0
  447. {$endif}
  448. end;
  449. function SwapEndian(const AValue: Int64): Int64; assembler; nostackframe;
  450. asm
  451. {$if defined(CPUM68K_HAS_ROLROR)}
  452. move.l avalue+4, d0
  453. ror.w #8, d0
  454. swap d0
  455. ror.w #8, d0
  456. move.l avalue, d1
  457. ror.w #8, d1
  458. swap d1
  459. ror.w #8, d1
  460. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  461. move.l avalue+4, d0
  462. move.l avalue, d1
  463. byterev d0
  464. byterev d1
  465. {$else}
  466. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  467. move.l d2, -(sp)
  468. move.l avalue+4, d0
  469. move.l d0, d1
  470. andi.l #$ff00ff00, d0
  471. andi.l #$00ff00ff, d1
  472. lsr.l #8, d0
  473. lsl.l #8, d1
  474. or.l d1, d0
  475. swap d0
  476. move.l avalue, d1
  477. move.l d1, d2
  478. andi.l #$ff00ff00, d1
  479. andi.l #$00ff00ff, d2
  480. lsr.l #8, d1
  481. lsl.l #8, d2
  482. or.l d2, d1
  483. swap d1
  484. move.l (sp)+, d2
  485. {$endif}
  486. end;
  487. function SwapEndian(const AValue: QWord): QWord; assembler; nostackframe;
  488. asm
  489. {$if defined(CPUM68K_HAS_ROLROR)}
  490. move.l avalue+4, d0
  491. ror.w #8, d0
  492. swap d0
  493. ror.w #8, d0
  494. move.l avalue, d1
  495. ror.w #8, d1
  496. swap d1
  497. ror.w #8, d1
  498. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  499. move.l avalue+4, d0
  500. move.l avalue, d1
  501. byterev d0
  502. byterev d1
  503. {$else}
  504. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  505. move.l d2, -(sp)
  506. move.l avalue+4, d0
  507. move.l d0, d1
  508. andi.l #$ff00ff00, d0
  509. andi.l #$00ff00ff, d1
  510. lsr.l #8, d0
  511. lsl.l #8, d1
  512. or.l d1, d0
  513. swap d0
  514. move.l avalue, d1
  515. move.l d1, d2
  516. andi.l #$ff00ff00, d1
  517. andi.l #$00ff00ff, d2
  518. lsr.l #8, d1
  519. lsl.l #8, d2
  520. or.l d2, d1
  521. swap d1
  522. move.l (sp)+, d2
  523. {$endif}
  524. end;
  525. {$endif FPC_SYSTEM_HAS_SWAPENDIAN}