popt386.pas 96 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2000 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. {$ifdef newOptimizations}
  20. {$define foropt}
  21. {$define replacereg}
  22. {$define arithopt}
  23. {$define foldarithops}
  24. {$endif newOptimizations}
  25. Interface
  26. Uses Aasm;
  27. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  28. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  29. Implementation
  30. Uses
  31. globtype,systems,
  32. globals,verbose,hcodegen,
  33. {$ifdef finaldestdebug}
  34. cobjects,
  35. {$endif finaldestdebug}
  36. cpubase,cpuasm,DAOpt386;
  37. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  38. Begin
  39. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  40. RegUsedAfterInstruction :=
  41. (Reg in UsedRegs) and
  42. (not(getNextInstruction(p,p)) or
  43. not(regLoadedWithNewValue(reg,false,p)));
  44. End;
  45. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  46. {First pass of peepholeoptimizations}
  47. Var
  48. l : longint;
  49. p,hp1,hp2 : pai;
  50. {$ifdef foropt}
  51. hp3,hp4: pai;
  52. {$endif foropt}
  53. TmpBool1, TmpBool2: Boolean;
  54. TmpRef: TReference;
  55. UsedRegs, TmpUsedRegs: TRegSet;
  56. Function SkipLabels(hp: Pai; var hp2: pai): boolean;
  57. {skips all labels and returns the next "real" instruction}
  58. Begin
  59. While assigned(hp^.next) and
  60. (pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
  61. hp := pai(hp^.next);
  62. If assigned(hp^.next) Then
  63. Begin
  64. SkipLabels := True;
  65. hp2 := pai(hp^.next)
  66. End
  67. Else
  68. Begin
  69. hp2 := hp;
  70. SkipLabels := False
  71. End;
  72. End;
  73. Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
  74. {traces sucessive jumps to their final destination and sets it, e.g.
  75. je l1 je l3
  76. <code> <code>
  77. l1: becomes l1:
  78. je l2 je l3
  79. <code> <code>
  80. l2: l2:
  81. jmp l3 jmp l3}
  82. Var p1, p2: pai;
  83. l: pasmlabel;
  84. Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
  85. Begin
  86. FindAnyLabel := false;
  87. While assigned(hp^.next) and
  88. (pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
  89. hp := pai(hp^.next);
  90. If assigned(hp^.next) and
  91. (pai(hp^.next)^.typ = ait_label) Then
  92. Begin
  93. FindAnyLabel := true;
  94. l := pai_label(hp^.next)^.l;
  95. End
  96. End;
  97. Begin
  98. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  99. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  100. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  101. Begin
  102. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  103. SkipLabels(p1,p1);
  104. If (pai(p1)^.typ = ait_instruction) and
  105. (paicpu(p1)^.is_jmp) Then
  106. If { the next instruction after the label where the jump hp arrives}
  107. { is unconditional or of the same type as hp, so continue }
  108. (paicpu(p1)^.condition in [C_None,hp^.condition]) or
  109. { the next instruction after the label where the jump hp arrives}
  110. { is the opposite of hp (so this one is never taken), but after }
  111. { that one there is a branch that will be taken, so perform a }
  112. { little hack: set p1 equal to this instruction (that's what the}
  113. { last SkipLabels is for, only works with short bool evaluation)}
  114. ((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
  115. SkipLabels(p1,p2) and
  116. (p2^.typ = ait_instruction) and
  117. (paicpu(p2)^.is_jmp) and
  118. (paicpu(p2)^.condition in [C_None,hp^.condition]) and
  119. SkipLabels(p1,p1)) Then
  120. Begin
  121. GetFinalDestination(asml, paicpu(p1));
  122. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  123. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  124. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  125. End
  126. Else
  127. If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
  128. if not FindAnyLabel(p1,l) then
  129. begin
  130. {$ifdef finaldestdebug}
  131. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  132. strpnew('previous label inserted'))));
  133. {$endif finaldestdebug}
  134. getlabel(l);
  135. insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
  136. dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
  137. hp^.oper[0].sym := l;
  138. inc(l^.refs);
  139. { this won't work, since the new label isn't in the labeltable }
  140. { so it will fail the rangecheck. Labeltable should become a }
  141. { hashtable to support this: }
  142. { GetFinalDestination(asml, hp); }
  143. end
  144. else
  145. begin
  146. {$ifdef finaldestdebug}
  147. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  148. strpnew('next label reused'))));
  149. {$endif finaldestdebug}
  150. inc(l^.refs);
  151. hp^.oper[0].sym := l;
  152. GetFinalDestination(asml, hp);
  153. end;
  154. End;
  155. End;
  156. Function DoSubAddOpt(var p: Pai): Boolean;
  157. Begin
  158. DoSubAddOpt := False;
  159. If GetLastInstruction(p, hp1) And
  160. (hp1^.typ = ait_instruction) And
  161. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  162. Case Paicpu(hp1)^.opcode Of
  163. A_DEC:
  164. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  165. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  166. Begin
  167. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  168. AsmL^.Remove(hp1);
  169. Dispose(hp1, Done)
  170. End;
  171. A_SUB:
  172. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  173. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  174. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  175. Begin
  176. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  177. AsmL^.Remove(hp1);
  178. Dispose(hp1, Done)
  179. End;
  180. A_ADD:
  181. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  182. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  183. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  184. Begin
  185. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  186. AsmL^.Remove(hp1);
  187. Dispose(hp1, Done);
  188. If (Paicpu(p)^.oper[0].val = 0) Then
  189. Begin
  190. hp1 := Pai(p^.next);
  191. AsmL^.Remove(p);
  192. Dispose(p, Done);
  193. If Not GetLastInstruction(hp1, p) Then
  194. p := hp1;
  195. DoSubAddOpt := True;
  196. End
  197. End;
  198. End;
  199. End;
  200. Begin
  201. P := BlockStart;
  202. UsedRegs := [];
  203. While (P <> BlockEnd) Do
  204. Begin
  205. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  206. Case P^.Typ Of
  207. ait_instruction:
  208. Begin
  209. { Handle Jmp Optimizations }
  210. if Paicpu(p)^.is_jmp then
  211. begin
  212. {the following if-block removes all code between a jmp and the next label,
  213. because it can never be executed}
  214. If (paicpu(p)^.opcode = A_JMP) Then
  215. Begin
  216. While GetNextInstruction(p, hp1) and
  217. ((hp1^.typ <> ait_label) or
  218. { skip unused labels, they're not referenced anywhere }
  219. Not(Pai_Label(hp1)^.l^.is_used)) Do
  220. If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
  221. Begin
  222. AsmL^.Remove(hp1);
  223. Dispose(hp1, done);
  224. End;
  225. End;
  226. If GetNextInstruction(p, hp1) then
  227. Begin
  228. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  229. Begin
  230. hp2:=pai(hp1^.next);
  231. asml^.remove(p);
  232. dispose(p,done);
  233. p:=hp2;
  234. continue;
  235. end
  236. Else
  237. Begin
  238. if hp1^.typ = ait_label then
  239. SkipLabels(hp1,hp1);
  240. If (pai(hp1)^.typ=ait_instruction) and
  241. (paicpu(hp1)^.opcode=A_JMP) and
  242. GetNextInstruction(hp1, hp2) And
  243. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  244. Then
  245. Begin
  246. if paicpu(p)^.opcode=A_Jcc then
  247. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  248. else
  249. begin
  250. If (LabDif <> 0) Then
  251. GetFinalDestination(asml, paicpu(p));
  252. p:=pai(p^.next);
  253. continue;
  254. end;
  255. Dec(pai_label(hp2)^.l^.refs);
  256. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  257. Inc(paicpu(p)^.oper[0].sym^.refs);
  258. asml^.remove(hp1);
  259. dispose(hp1,done);
  260. If (LabDif <> 0) Then
  261. GetFinalDestination(asml, paicpu(p));
  262. end
  263. else
  264. If (LabDif <> 0) Then
  265. GetFinalDestination(asml, paicpu(p));
  266. end;
  267. end;
  268. end
  269. else
  270. { All other optimizes }
  271. begin
  272. For l := 0 to 2 Do
  273. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  274. With Paicpu(p)^.oper[l].ref^ Do
  275. Begin
  276. If (base = R_NO) And
  277. (index <> R_NO) And
  278. (scalefactor in [0,1])
  279. Then
  280. Begin
  281. base := index;
  282. index := R_NO
  283. End
  284. End;
  285. Case Paicpu(p)^.opcode Of
  286. A_AND:
  287. Begin
  288. If (Paicpu(p)^.oper[0].typ = top_const) And
  289. (Paicpu(p)^.oper[1].typ = top_reg) And
  290. GetNextInstruction(p, hp1) And
  291. (Pai(hp1)^.typ = ait_instruction) And
  292. (Paicpu(hp1)^.opcode = A_AND) And
  293. (Paicpu(hp1)^.oper[0].typ = top_const) And
  294. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  295. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  296. Then
  297. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  298. Begin
  299. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  300. AsmL^.Remove(hp1);
  301. Dispose(hp1, Done)
  302. End
  303. Else
  304. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  305. jump, but only if it's a conditional jump (PFV) }
  306. If (Paicpu(p)^.oper[1].typ = top_reg) And
  307. GetNextInstruction(p, hp1) And
  308. (hp1^.typ = ait_instruction) And
  309. (Paicpu(hp1)^.is_jmp) and
  310. (Paicpu(hp1)^.opcode<>A_JMP) and
  311. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  312. Paicpu(p)^.opcode := A_TEST;
  313. End;
  314. A_CMP:
  315. Begin
  316. If (Paicpu(p)^.oper[0].typ = top_const) And
  317. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  318. (Paicpu(p)^.oper[0].val = 0) Then
  319. {$ifdef foropt}
  320. If GetNextInstruction(p, hp1) And
  321. (hp1^.typ = ait_instruction) And
  322. (Paicpu(hp1)^.is_jmp) and
  323. (paicpu(hp1)^.opcode=A_Jcc) and
  324. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  325. GetNextInstruction(hp1,hp2) and
  326. (hp2^.typ = ait_instruction) and
  327. (Paicpu(hp2)^.opcode = A_DEC) And
  328. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  329. GetNextInstruction(hp2, hp3) And
  330. (hp3^.typ = ait_instruction) and
  331. (Paicpu(hp3)^.is_jmp) and
  332. (Paicpu(hp3)^.opcode = A_JMP) And
  333. GetNextInstruction(hp3, hp4) And
  334. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  335. Then
  336. Begin
  337. Paicpu(hp2)^.Opcode := A_SUB;
  338. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  339. Paicpu(hp2)^.LoadConst(0,1);
  340. Paicpu(hp2)^.ops:=2;
  341. Paicpu(hp3)^.Opcode := A_Jcc;
  342. Case paicpu(hp1)^.condition of
  343. C_LE: Paicpu(hp3)^.condition := C_GE;
  344. C_BE: Paicpu(hp3)^.condition := C_AE;
  345. End;
  346. AsmL^.Remove(p);
  347. AsmL^.Remove(hp1);
  348. Dispose(p, Done);
  349. Dispose(hp1, Done);
  350. p := hp2;
  351. continue;
  352. End
  353. Else
  354. {$endif foropt}
  355. {change "cmp $0, %reg" to "test %reg, %reg"}
  356. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  357. Begin
  358. Paicpu(p)^.opcode := A_TEST;
  359. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  360. End;
  361. End;
  362. A_FLD:
  363. Begin
  364. If (Paicpu(p)^.oper[0].typ = top_reg) And
  365. GetNextInstruction(p, hp1) And
  366. (hp1^.typ = Ait_Instruction) And
  367. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  368. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  369. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  370. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  371. { change to
  372. fld reg fxxx reg,st
  373. fxxxp st, st1 (hp1)
  374. Remark: non commutative operations must be reversed!
  375. }
  376. begin
  377. Case Paicpu(hp1)^.opcode Of
  378. A_FMULP,A_FADDP,
  379. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  380. begin
  381. Case Paicpu(hp1)^.opcode Of
  382. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  383. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  384. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  385. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  386. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  387. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  388. End;
  389. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  390. Paicpu(hp1)^.oper[1].reg := R_ST;
  391. AsmL^.Remove(p);
  392. Dispose(p, Done);
  393. p := hp1;
  394. Continue;
  395. end;
  396. end;
  397. end
  398. else
  399. If (Paicpu(p)^.oper[0].typ = top_ref) And
  400. GetNextInstruction(p, hp2) And
  401. (hp2^.typ = Ait_Instruction) And
  402. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  403. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  404. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  405. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  406. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  407. If GetLastInstruction(p, hp1) And
  408. (hp1^.typ = Ait_Instruction) And
  409. ((Paicpu(hp1)^.opcode = A_FLD) Or
  410. (Paicpu(hp1)^.opcode = A_FST)) And
  411. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  412. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  413. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  414. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  415. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  416. { change to
  417. fld/fst mem1 (hp1) fld/fst mem1
  418. fld mem1 (p) fadd/
  419. faddp/ fmul st, st
  420. fmulp st, st1 (hp2) }
  421. Begin
  422. AsmL^.Remove(p);
  423. Dispose(p, Done);
  424. p := hp1;
  425. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  426. Paicpu(hp2)^.opcode := A_FADD
  427. Else
  428. Paicpu(hp2)^.opcode := A_FMUL;
  429. Paicpu(hp2)^.oper[1].reg := R_ST;
  430. End
  431. Else
  432. { change to
  433. fld/fst mem1 (hp1) fld/fst mem1
  434. fld mem1 (p) fld st}
  435. Begin
  436. Paicpu(p)^.changeopsize(S_FL);
  437. Paicpu(p)^.loadreg(0,R_ST);
  438. End
  439. Else
  440. Begin
  441. Case Paicpu(hp2)^.opcode Of
  442. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  443. { change to
  444. fld/fst mem1 (hp1) fld/fst mem1
  445. fld mem2 (p) fxxx mem2
  446. fxxxp st, st1 (hp2) }
  447. Begin
  448. Case Paicpu(hp2)^.opcode Of
  449. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  450. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  451. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  452. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  453. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  454. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  455. End;
  456. AsmL^.Remove(hp2);
  457. Dispose(hp2, Done)
  458. End
  459. End
  460. End
  461. End;
  462. A_FSTP,A_FISTP:
  463. Begin
  464. If (Paicpu(p)^.oper[0].typ = top_ref) And
  465. GetNextInstruction(p, hp1) And
  466. (Pai(hp1)^.typ = ait_instruction) And
  467. (((Paicpu(hp1)^.opcode = A_FLD) And
  468. (Paicpu(p)^.opcode = A_FSTP)) Or
  469. ((Paicpu(p)^.opcode = A_FISTP) And
  470. (Paicpu(hp1)^.opcode = A_FILD))) And
  471. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  472. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  473. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^)
  474. Then
  475. Begin
  476. If GetNextInstruction(hp1, hp2) And
  477. (hp2^.typ = ait_instruction) And
  478. ((Paicpu(hp2)^.opcode = A_LEAVE) Or
  479. (Paicpu(hp2)^.opcode = A_RET)) And
  480. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  481. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  482. (Paicpu(p)^.oper[0].ref^.Index = R_NO)
  483. Then
  484. Begin
  485. AsmL^.Remove(p);
  486. AsmL^.Remove(hp1);
  487. Dispose(p, Done);
  488. Dispose(hp1, Done);
  489. p := hp2;
  490. RemoveLastDeallocForFuncRes(asmL, p);
  491. Continue
  492. End
  493. Else
  494. {fst can't store an extended value!}
  495. If (Paicpu(p)^.opsize <> S_FX) And
  496. (Paicpu(p)^.opsize <> S_IQ) Then
  497. Begin
  498. If (Paicpu(p)^.opcode = A_FSTP) Then
  499. Paicpu(p)^.opcode := A_FST
  500. Else Paicpu(p)^.opcode := A_FIST;
  501. AsmL^.Remove(hp1);
  502. Dispose(hp1, done)
  503. End
  504. End;
  505. End;
  506. A_IMUL:
  507. {changes certain "imul const, %reg"'s to lea sequences}
  508. Begin
  509. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  510. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  511. (Paicpu(p)^.opsize = S_L) Then
  512. If (Paicpu(p)^.oper[0].val = 1) Then
  513. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  514. {remove "imul $1, reg"}
  515. Begin
  516. hp1 := Pai(p^.Next);
  517. AsmL^.Remove(p);
  518. Dispose(p, Done);
  519. p := hp1;
  520. Continue;
  521. End
  522. Else
  523. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  524. Begin
  525. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  526. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  527. Dispose(p, Done);
  528. p := hp1;
  529. End
  530. Else If
  531. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  532. (Paicpu(p)^.oper[2].typ = Top_None)) And
  533. (aktoptprocessor < ClassP6) And
  534. (Paicpu(p)^.oper[0].val <= 12) And
  535. Not(CS_LittleSize in aktglobalswitches) And
  536. (Not(GetNextInstruction(p, hp1)) Or
  537. {GetNextInstruction(p, hp1) And}
  538. Not((Pai(hp1)^.typ = ait_instruction) And
  539. ((paicpu(hp1)^.opcode=A_Jcc) and
  540. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  541. Then
  542. Begin
  543. Reset_reference(tmpref);
  544. Case Paicpu(p)^.oper[0].val Of
  545. 3: Begin
  546. {imul 3, reg1, reg2 to
  547. lea (reg1,reg1,2), reg2
  548. imul 3, reg1 to
  549. lea (reg1,reg1,2), reg1}
  550. TmpRef.base := Paicpu(p)^.oper[1].reg;
  551. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  552. TmpRef.ScaleFactor := 2;
  553. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  554. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  555. Else
  556. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  557. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  558. Dispose(p, Done);
  559. p := hp1;
  560. End;
  561. 5: Begin
  562. {imul 5, reg1, reg2 to
  563. lea (reg1,reg1,4), reg2
  564. imul 5, reg1 to
  565. lea (reg1,reg1,4), reg1}
  566. TmpRef.base := Paicpu(p)^.oper[1].reg;
  567. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  568. TmpRef.ScaleFactor := 4;
  569. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  570. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  571. Else
  572. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  573. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  574. Dispose(p, Done);
  575. p := hp1;
  576. End;
  577. 6: Begin
  578. {imul 6, reg1, reg2 to
  579. lea (,reg1,2), reg2
  580. lea (reg2,reg1,4), reg2
  581. imul 6, reg1 to
  582. lea (reg1,reg1,2), reg1
  583. add reg1, reg1}
  584. If (aktoptprocessor <= Class386)
  585. Then
  586. Begin
  587. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  588. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  589. Then
  590. Begin
  591. TmpRef.base := Paicpu(p)^.oper[2].reg;
  592. TmpRef.ScaleFactor := 4;
  593. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  594. End
  595. Else
  596. Begin
  597. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  598. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  599. End;
  600. InsertLLItem(AsmL,p, p^.next, hp1);
  601. Reset_reference(tmpref);
  602. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  603. TmpRef.ScaleFactor := 2;
  604. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  605. Then
  606. Begin
  607. TmpRef.base := R_NO;
  608. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  609. Paicpu(p)^.oper[2].reg));
  610. End
  611. Else
  612. Begin
  613. TmpRef.base := Paicpu(p)^.oper[1].reg;
  614. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  615. End;
  616. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  617. Dispose(p, Done);
  618. p := Pai(hp1^.next);
  619. End
  620. End;
  621. 9: Begin
  622. {imul 9, reg1, reg2 to
  623. lea (reg1,reg1,8), reg2
  624. imul 9, reg1 to
  625. lea (reg1,reg1,8), reg1}
  626. TmpRef.base := Paicpu(p)^.oper[1].reg;
  627. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  628. TmpRef.ScaleFactor := 8;
  629. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  630. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  631. Else
  632. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  633. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  634. Dispose(p, Done);
  635. p := hp1;
  636. End;
  637. 10: Begin
  638. {imul 10, reg1, reg2 to
  639. lea (reg1,reg1,4), reg2
  640. add reg2, reg2
  641. imul 10, reg1 to
  642. lea (reg1,reg1,4), reg1
  643. add reg1, reg1}
  644. If (aktoptprocessor <= Class386) Then
  645. Begin
  646. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  647. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  648. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  649. Else
  650. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  651. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  652. InsertLLItem(AsmL,p, p^.next, hp1);
  653. TmpRef.base := Paicpu(p)^.oper[1].reg;
  654. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  655. TmpRef.ScaleFactor := 4;
  656. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  657. Then
  658. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
  659. Else
  660. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  661. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  662. Dispose(p, Done);
  663. p := Pai(hp1^.next);
  664. End
  665. End;
  666. 12: Begin
  667. {imul 12, reg1, reg2 to
  668. lea (,reg1,4), reg2
  669. lea (,reg1,8) reg2
  670. imul 12, reg1 to
  671. lea (reg1,reg1,2), reg1
  672. lea (,reg1,4), reg1}
  673. If (aktoptprocessor <= Class386)
  674. Then
  675. Begin
  676. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  677. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  678. Begin
  679. TmpRef.base := Paicpu(p)^.oper[2].reg;
  680. TmpRef.ScaleFactor := 8;
  681. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  682. End
  683. Else
  684. Begin
  685. TmpRef.base := R_NO;
  686. TmpRef.ScaleFactor := 4;
  687. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  688. End;
  689. InsertLLItem(AsmL,p, p^.next, hp1);
  690. Reset_reference(tmpref);
  691. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  692. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  693. Begin
  694. TmpRef.base := R_NO;
  695. TmpRef.ScaleFactor := 4;
  696. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  697. End
  698. Else
  699. Begin
  700. TmpRef.base := Paicpu(p)^.oper[1].reg;
  701. TmpRef.ScaleFactor := 2;
  702. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  703. End;
  704. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  705. Dispose(p, Done);
  706. p := Pai(hp1^.next);
  707. End
  708. End
  709. End;
  710. End;
  711. End;
  712. A_LEA:
  713. Begin
  714. {removes seg register prefixes from LEA operations, as they
  715. don't do anything}
  716. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  717. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  718. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  719. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  720. {$ifndef newOptimizations}
  721. (Paicpu(p)^.oper[0].ref^.Offset = 0) And
  722. {$endif newOptimizations}
  723. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  724. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  725. {$ifdef newOptimizations}
  726. and (Paicpu(p)^.oper[0].ref^.Offset = 0)
  727. {$endif newOptimizations}
  728. Then
  729. Begin
  730. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  731. Paicpu(p)^.oper[1].reg));
  732. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  733. Dispose(p, Done);
  734. p := hp1;
  735. Continue;
  736. End
  737. Else
  738. {$ifdef newOptimizations}
  739. if (Paicpu(p)^.oper[0].ref^.Offset = 0) then
  740. {$endif newOptimizations}
  741. Begin
  742. hp1 := Pai(p^.Next);
  743. AsmL^.Remove(p);
  744. Dispose(p, Done);
  745. p := hp1;
  746. Continue;
  747. End
  748. {$ifdef newOptimizations}
  749. else
  750. with Paicpu(p)^.oper[0].ref^ do
  751. if (Base = Paicpu(p)^.oper[1].reg) then
  752. begin
  753. l := offset+offsetfixup;
  754. case l of
  755. 1,-1:
  756. begin
  757. if l = 1 then
  758. paicpu(p)^.opcode := A_INC
  759. else paicpu(p)^.opcode := A_DEC;
  760. paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  761. paicpu(p)^.ops := 1;
  762. end;
  763. else
  764. begin
  765. paicpu(p)^.opcode := A_ADD;
  766. paicpu(p)^.loadconst(0,offset+offsetfixup);
  767. end;
  768. end;
  769. end;
  770. {$endif newOptimizations}
  771. End;
  772. A_MOV:
  773. Begin
  774. TmpUsedRegs := UsedRegs;
  775. If (Paicpu(p)^.oper[1].typ = top_reg) And
  776. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  777. GetNextInstruction(p, hp1) And
  778. (Pai(hp1)^.typ = ait_instruction) And
  779. (Paicpu(hp1)^.opcode = A_MOV) And
  780. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  781. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  782. Then
  783. {we have "mov x, %treg; mov %treg, y}
  784. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  785. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  786. Case Paicpu(p)^.oper[0].typ Of
  787. top_reg:
  788. Begin
  789. { change "mov %reg, %treg; mov %treg, y"
  790. to "mov %reg, y" }
  791. Paicpu(hp1)^.LoadOper(0,Paicpu(p)^.oper[0]);
  792. AsmL^.Remove(p);
  793. Dispose(p, Done);
  794. p := hp1;
  795. continue;
  796. End;
  797. top_ref:
  798. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  799. Begin
  800. { change "mov mem, %treg; mov %treg, %reg"
  801. to "mov mem, %reg" }
  802. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  803. AsmL^.Remove(hp1);
  804. Dispose(hp1, Done);
  805. continue;
  806. End;
  807. End
  808. Else
  809. Else
  810. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  811. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  812. penalty}
  813. If (Paicpu(p)^.oper[0].typ = top_reg) And
  814. (Paicpu(p)^.oper[1].typ = top_reg) And
  815. GetNextInstruction(p,hp1) And
  816. (Pai(hp1)^.typ = ait_instruction) And
  817. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  818. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  819. Then
  820. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  821. Begin
  822. If ((Paicpu(hp1)^.opcode = A_OR) Or
  823. (Paicpu(hp1)^.opcode = A_TEST)) And
  824. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  825. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  826. Then
  827. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  828. Begin
  829. TmpUsedRegs := UsedRegs;
  830. If GetNextInstruction(hp1, hp2) And
  831. (hp2^.typ = ait_instruction) And
  832. paicpu(hp2)^.is_jmp and
  833. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  834. Then
  835. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  836. "test %reg1, %reg1; jxx"}
  837. Begin
  838. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  839. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  840. AsmL^.Remove(p);
  841. Dispose(p, done);
  842. p := hp1;
  843. continue
  844. End
  845. Else
  846. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  847. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  848. Begin
  849. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  850. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  851. End;
  852. End
  853. { Else
  854. If (Paicpu(p^.next)^.opcode
  855. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  856. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  857. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  858. End
  859. Else
  860. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  861. x >= RetOffset) as it doesn't do anything (it writes either to a
  862. parameter or to the temporary storage room for the function
  863. result)}
  864. If GetNextInstruction(p, hp1) And
  865. (Pai(hp1)^.typ = ait_instruction)
  866. Then
  867. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  868. (Paicpu(hp1)^.opcode = A_RET)) And
  869. (Paicpu(p)^.oper[1].typ = top_ref) And
  870. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  871. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
  872. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  873. (Paicpu(p)^.oper[0].typ = top_reg)
  874. Then
  875. Begin
  876. AsmL^.Remove(p);
  877. Dispose(p, done);
  878. p := hp1;
  879. RemoveLastDeallocForFuncRes(asmL,p);
  880. End
  881. Else
  882. If (Paicpu(p)^.oper[0].typ = top_reg) And
  883. (Paicpu(p)^.oper[1].typ = top_ref) And
  884. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  885. (Paicpu(hp1)^.opcode = A_CMP) And
  886. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  887. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^)
  888. Then
  889. {change "mov reg, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  890. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  891. { Next instruction is also a MOV ? }
  892. If GetNextInstruction(p, hp1) And
  893. (pai(hp1)^.typ = ait_instruction) and
  894. (Paicpu(hp1)^.opcode = A_MOV) and
  895. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  896. Then
  897. Begin
  898. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  899. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  900. Then
  901. {mov reg1, mem1 or mov mem1, reg1
  902. mov mem2, reg2 mov reg2, mem2}
  903. Begin
  904. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  905. {mov reg1, mem1 or mov mem1, reg1
  906. mov mem2, reg1 mov reg2, mem1}
  907. Begin
  908. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  909. { Removes the second statement from
  910. mov reg1, mem1
  911. mov mem1, reg1 }
  912. Begin
  913. AsmL^.remove(hp1);
  914. Dispose(hp1,done);
  915. End
  916. Else
  917. Begin
  918. TmpUsedRegs := UsedRegs;
  919. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  920. If (Paicpu(p)^.oper[0].typ = top_reg) And
  921. { mov reg1, mem1
  922. mov mem2, reg1 }
  923. GetNextInstruction(hp1, hp2) And
  924. (hp2^.typ = ait_instruction) And
  925. (Paicpu(hp2)^.opcode = A_CMP) And
  926. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  927. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  928. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  929. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  930. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  931. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  932. { change to
  933. mov reg1, mem1 mov reg1, mem1
  934. mov mem2, reg1 cmp reg1, mem2
  935. cmp mem1, reg1 }
  936. Begin
  937. AsmL^.Remove(hp2);
  938. Dispose(hp2, Done);
  939. Paicpu(hp1)^.opcode := A_CMP;
  940. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  941. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  942. End;
  943. End;
  944. End
  945. Else
  946. Begin
  947. tmpUsedRegs := UsedRegs;
  948. If GetNextInstruction(hp1, hp2) And
  949. (Paicpu(p)^.oper[0].typ = top_ref) And
  950. (Paicpu(p)^.oper[1].typ = top_reg) And
  951. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  952. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  953. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  954. (Pai(hp2)^.typ = ait_instruction) And
  955. (Paicpu(hp2)^.opcode = A_MOV) And
  956. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  957. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  958. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  959. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  960. If (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI]) and
  961. not(RegUsedAfterInstruction(R_EDI,hp1,tmpUsedRegs)) Then
  962. { mov mem1, %edi
  963. mov %edi, mem2
  964. mov mem2, reg2
  965. to:
  966. mov mem1, reg2
  967. mov reg2, mem2}
  968. Begin
  969. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  970. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  971. AsmL^.Remove(hp2);
  972. Dispose(hp2,Done);
  973. End
  974. Else
  975. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  976. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  977. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  978. Then
  979. { mov mem1, reg1 mov mem1, reg1
  980. mov reg1, mem2 mov reg1, mem2
  981. mov mem2, reg2 mov mem2, reg1
  982. to: to:
  983. mov mem1, reg1 mov mem1, reg1
  984. mov mem1, reg2 mov reg1, mem2
  985. mov reg1, mem2
  986. or (if mem1 depends on reg1
  987. and/or if mem2 depends on reg2)
  988. to:
  989. mov mem1, reg1
  990. mov reg1, mem2
  991. mov reg1, reg2
  992. }
  993. Begin
  994. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  995. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  996. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  997. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  998. End
  999. Else
  1000. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  1001. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg)
  1002. Else
  1003. Begin
  1004. AsmL^.Remove(hp2);
  1005. Dispose(hp2, Done);
  1006. End
  1007. End;
  1008. End
  1009. Else
  1010. (* {movl [mem1],reg1
  1011. movl [mem1],reg2
  1012. to:
  1013. movl [mem1],reg1
  1014. movl reg1,reg2 }
  1015. If (Paicpu(p)^.oper[0].typ = top_ref) and
  1016. (Paicpu(p)^.oper[1].typ = top_reg) and
  1017. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1018. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1019. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1020. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  1021. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  1022. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  1023. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  1024. Else*)
  1025. { movl const1,[mem1]
  1026. movl [mem1],reg1
  1027. to:
  1028. movl const1,reg1
  1029. movl reg1,[mem1] }
  1030. If (Paicpu(p)^.oper[0].typ = top_const) and
  1031. (Paicpu(p)^.oper[1].typ = top_ref) and
  1032. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1033. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1034. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1035. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  1036. Begin
  1037. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1038. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  1039. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  1040. End
  1041. End;
  1042. End;
  1043. A_MOVZX:
  1044. Begin
  1045. {removes superfluous And's after movzx's}
  1046. If (Paicpu(p)^.oper[1].typ = top_reg) And
  1047. GetNextInstruction(p, hp1) And
  1048. (Pai(hp1)^.typ = ait_instruction) And
  1049. (Paicpu(hp1)^.opcode = A_AND) And
  1050. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1051. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1052. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1053. Then
  1054. Case Paicpu(p)^.opsize Of
  1055. S_BL, S_BW:
  1056. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  1057. Begin
  1058. AsmL^.Remove(hp1);
  1059. Dispose(hp1, Done);
  1060. End;
  1061. S_WL:
  1062. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  1063. Begin
  1064. AsmL^.Remove(hp1);
  1065. Dispose(hp1, Done);
  1066. End;
  1067. End;
  1068. {changes some movzx constructs to faster synonims (all examples
  1069. are given with eax/ax, but are also valid for other registers)}
  1070. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1071. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1072. Case Paicpu(p)^.opsize of
  1073. S_BW:
  1074. Begin
  1075. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1076. Not(CS_LittleSize In aktglobalswitches)
  1077. Then
  1078. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1079. Begin
  1080. Paicpu(p)^.opcode := A_AND;
  1081. Paicpu(p)^.changeopsize(S_W);
  1082. Paicpu(p)^.LoadConst(0,$ff);
  1083. End
  1084. Else
  1085. If GetNextInstruction(p, hp1) And
  1086. (Pai(hp1)^.typ = ait_instruction) And
  1087. (Paicpu(hp1)^.opcode = A_AND) And
  1088. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1089. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1090. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1091. Then
  1092. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1093. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1094. Begin
  1095. Paicpu(p)^.opcode := A_MOV;
  1096. Paicpu(p)^.changeopsize(S_W);
  1097. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1098. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1099. End;
  1100. End;
  1101. S_BL:
  1102. Begin
  1103. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1104. Not(CS_LittleSize in aktglobalswitches)
  1105. Then
  1106. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1107. Begin
  1108. Paicpu(p)^.opcode := A_AND;
  1109. Paicpu(p)^.changeopsize(S_L);
  1110. Paicpu(p)^.loadconst(0,$ff)
  1111. End
  1112. Else
  1113. If GetNextInstruction(p, hp1) And
  1114. (Pai(hp1)^.typ = ait_instruction) And
  1115. (Paicpu(hp1)^.opcode = A_AND) And
  1116. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1117. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1118. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1119. Then
  1120. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1121. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1122. Begin
  1123. Paicpu(p)^.opcode := A_MOV;
  1124. Paicpu(p)^.changeopsize(S_L);
  1125. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1126. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1127. End
  1128. End;
  1129. S_WL:
  1130. Begin
  1131. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1132. Not(CS_LittleSize In aktglobalswitches)
  1133. Then
  1134. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1135. Begin
  1136. Paicpu(p)^.opcode := A_AND;
  1137. Paicpu(p)^.changeopsize(S_L);
  1138. Paicpu(p)^.LoadConst(0,$ffff);
  1139. End
  1140. Else
  1141. If GetNextInstruction(p, hp1) And
  1142. (Pai(hp1)^.typ = ait_instruction) And
  1143. (Paicpu(hp1)^.opcode = A_AND) And
  1144. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1145. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1146. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1147. Then
  1148. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1149. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1150. Begin
  1151. Paicpu(p)^.opcode := A_MOV;
  1152. Paicpu(p)^.changeopsize(S_L);
  1153. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1154. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1155. End;
  1156. End;
  1157. End
  1158. Else
  1159. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1160. Begin
  1161. If GetNextInstruction(p, hp1) And
  1162. (Pai(hp1)^.typ = ait_instruction) And
  1163. (Paicpu(hp1)^.opcode = A_AND) And
  1164. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1165. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1166. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1167. Begin
  1168. Paicpu(p)^.opcode := A_MOV;
  1169. Case Paicpu(p)^.opsize Of
  1170. S_BL:
  1171. Begin
  1172. Paicpu(p)^.changeopsize(S_L);
  1173. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1174. End;
  1175. S_WL:
  1176. Begin
  1177. Paicpu(p)^.changeopsize(S_L);
  1178. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1179. End;
  1180. S_BW:
  1181. Begin
  1182. Paicpu(p)^.changeopsize(S_W);
  1183. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1184. End;
  1185. End;
  1186. End;
  1187. End;
  1188. End;
  1189. A_POP:
  1190. Begin
  1191. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1192. GetNextInstruction(p, hp1) And
  1193. (pai(hp1)^.typ=ait_instruction) and
  1194. (Paicpu(hp1)^.opcode=A_PUSH) and
  1195. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1196. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1197. { This can't be done, because the register which is popped
  1198. can still be used after the push (PFV)
  1199. If (Not(cs_regalloc in aktglobalswitches)) Then
  1200. Begin
  1201. hp2:=pai(hp1^.next);
  1202. asml^.remove(p);
  1203. asml^.remove(hp1);
  1204. dispose(p,done);
  1205. dispose(hp1,done);
  1206. p:=hp2;
  1207. continue
  1208. End
  1209. Else }
  1210. Begin
  1211. { change it to a two op operation }
  1212. Paicpu(p)^.oper[1].typ:=top_none;
  1213. Paicpu(p)^.ops:=2;
  1214. Paicpu(p)^.opcode := A_MOV;
  1215. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1216. Reset_reference(tmpref);
  1217. TmpRef.base := R_ESP;
  1218. Paicpu(p)^.LoadRef(0,newReference(TmpRef));
  1219. AsmL^.Remove(hp1);
  1220. Dispose(hp1, Done)
  1221. End;
  1222. end;
  1223. A_PUSH:
  1224. Begin
  1225. If (Paicpu(p)^.opsize = S_W) And
  1226. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1227. GetNextInstruction(p, hp1) And
  1228. (Pai(hp1)^.typ = ait_instruction) And
  1229. (Paicpu(hp1)^.opcode = A_PUSH) And
  1230. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1231. (Paicpu(hp1)^.opsize = S_W) Then
  1232. Begin
  1233. Paicpu(p)^.changeopsize(S_L);
  1234. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + word(Paicpu(hp1)^.oper[0].val));
  1235. AsmL^.Remove(hp1);
  1236. Dispose(hp1, Done)
  1237. End;
  1238. End;
  1239. A_SHL, A_SAL:
  1240. Begin
  1241. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1242. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1243. (Paicpu(p)^.opsize = S_L) And
  1244. (Paicpu(p)^.oper[0].val <= 3)
  1245. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1246. Then
  1247. Begin
  1248. TmpBool1 := True; {should we check the next instruction?}
  1249. TmpBool2 := False; {have we found an add/sub which could be
  1250. integrated in the lea?}
  1251. Reset_reference(tmpref);
  1252. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1253. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1254. While TmpBool1 And
  1255. GetNextInstruction(p, hp1) And
  1256. (Pai(hp1)^.typ = ait_instruction) And
  1257. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1258. (Paicpu(hp1)^.opcode = A_SUB)) And
  1259. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1260. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1261. Begin
  1262. TmpBool1 := False;
  1263. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1264. Then
  1265. Begin
  1266. TmpBool1 := True;
  1267. TmpBool2 := True;
  1268. If Paicpu(hp1)^.opcode = A_ADD Then
  1269. Inc(TmpRef.offset, Paicpu(hp1)^.oper[0].val)
  1270. Else
  1271. Dec(TmpRef.offset, Paicpu(hp1)^.oper[0].val);
  1272. AsmL^.Remove(hp1);
  1273. Dispose(hp1, Done);
  1274. End
  1275. Else
  1276. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1277. (Paicpu(hp1)^.opcode = A_ADD) And
  1278. (TmpRef.base = R_NO) Then
  1279. Begin
  1280. TmpBool1 := True;
  1281. TmpBool2 := True;
  1282. TmpRef.base := Paicpu(hp1)^.oper[0].reg;
  1283. AsmL^.Remove(hp1);
  1284. Dispose(hp1, Done);
  1285. End;
  1286. End;
  1287. If TmpBool2 Or
  1288. ((aktoptprocessor < ClassP6) And
  1289. (Paicpu(p)^.oper[0].val <= 3) And
  1290. Not(CS_LittleSize in aktglobalswitches))
  1291. Then
  1292. Begin
  1293. If Not(TmpBool2) And
  1294. (Paicpu(p)^.oper[0].val = 1)
  1295. Then
  1296. Begin
  1297. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1298. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1299. End
  1300. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  1301. Paicpu(p)^.oper[1].reg));
  1302. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1303. Dispose(p, Done);
  1304. p := hp1;
  1305. End;
  1306. End
  1307. Else
  1308. If (aktoptprocessor < ClassP6) And
  1309. (Paicpu(p)^.oper[0].typ = top_const) And
  1310. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1311. If (Paicpu(p)^.oper[0].val = 1)
  1312. Then
  1313. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1314. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1315. (unlike shl, which is only pairable in the U pipe)}
  1316. Begin
  1317. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1318. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1319. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1320. Dispose(p, done);
  1321. p := hp1;
  1322. End
  1323. Else If (Paicpu(p)^.opsize = S_L) and
  1324. (Paicpu(p)^.oper[0].val<= 3) Then
  1325. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1326. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1327. Begin
  1328. Reset_reference(tmpref);
  1329. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1330. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1331. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  1332. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1333. Dispose(p, done);
  1334. p := hp1;
  1335. End
  1336. End;
  1337. A_SAR, A_SHR:
  1338. {changes the code sequence
  1339. shr/sar const1, x
  1340. shl const2, x
  1341. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1342. Begin
  1343. If GetNextInstruction(p, hp1) And
  1344. (pai(hp1)^.typ = ait_instruction) and
  1345. (Paicpu(hp1)^.opcode = A_SHL) and
  1346. (Paicpu(p)^.oper[0].typ = top_const) and
  1347. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1348. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1349. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1350. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1351. Then
  1352. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1353. Not(CS_LittleSize In aktglobalswitches)
  1354. Then
  1355. { shr/sar const1, %reg
  1356. shl const2, %reg
  1357. with const1 > const2 }
  1358. Begin
  1359. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1360. Paicpu(hp1)^.opcode := A_AND;
  1361. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1362. Case Paicpu(p)^.opsize Of
  1363. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1364. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1365. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1366. End;
  1367. End
  1368. Else
  1369. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1370. Not(CS_LittleSize In aktglobalswitches)
  1371. Then
  1372. { shr/sar const1, %reg
  1373. shl const2, %reg
  1374. with const1 < const2 }
  1375. Begin
  1376. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1377. Paicpu(p)^.opcode := A_AND;
  1378. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1379. Case Paicpu(p)^.opsize Of
  1380. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1381. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1382. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1383. End;
  1384. End
  1385. Else
  1386. { shr/sar const1, %reg
  1387. shl const2, %reg
  1388. with const1 = const2 }
  1389. Begin
  1390. Paicpu(p)^.opcode := A_AND;
  1391. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1392. Case Paicpu(p)^.opsize Of
  1393. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1394. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1395. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1396. End;
  1397. AsmL^.remove(hp1);
  1398. dispose(hp1, done);
  1399. End;
  1400. End;
  1401. A_SETcc :
  1402. { changes
  1403. setcc (funcres) setcc reg
  1404. movb (funcres), reg to leave/ret
  1405. leave/ret }
  1406. Begin
  1407. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1408. GetNextInstruction(p, hp1) And
  1409. GetNextInstruction(hp1, hp2) And
  1410. (hp2^.typ = ait_instruction) And
  1411. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1412. (Paicpu(hp2)^.opcode = A_RET)) And
  1413. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1414. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1415. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  1416. (hp1^.typ = ait_instruction) And
  1417. (Paicpu(hp1)^.opcode = A_MOV) And
  1418. (Paicpu(hp1)^.opsize = S_B) And
  1419. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1420. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1421. Begin
  1422. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1423. AsmL^.Remove(hp1);
  1424. Dispose(hp1, Done)
  1425. End
  1426. End;
  1427. A_SUB:
  1428. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1429. { * change "sub/add const1, reg" or "dec reg" followed by
  1430. "sub const2, reg" to one "sub ..., reg" }
  1431. Begin
  1432. If (Paicpu(p)^.oper[0].typ = top_const) And
  1433. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1434. If (Paicpu(p)^.oper[0].val = 2) And
  1435. (Paicpu(p)^.oper[1].reg = R_ESP) Then
  1436. Begin
  1437. hp1 := Pai(p^.next);
  1438. While Assigned(hp1) And
  1439. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1440. Not((Pai(hp1)^.typ = ait_instruction) And
  1441. ((Paicpu(hp1)^.opcode = A_CALL) or
  1442. (Paicpu(hp1)^.opcode = A_PUSH) or
  1443. ((Paicpu(hp1)^.opcode = A_MOV) And
  1444. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1445. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1446. hp1 := Pai(hp1^.next);
  1447. If Assigned(hp1) And
  1448. (Pai(hp1)^.typ = ait_instruction) And
  1449. (Paicpu(hp1)^.opcode = A_PUSH) And
  1450. (Paicpu(hp1)^.opsize = S_W)
  1451. Then
  1452. Begin
  1453. Paicpu(hp1)^.changeopsize(S_L);
  1454. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1455. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1456. hp1 := Pai(p^.next);
  1457. AsmL^.Remove(p);
  1458. Dispose(p, Done);
  1459. p := hp1;
  1460. Continue
  1461. End;
  1462. If DoSubAddOpt(p) Then continue;
  1463. End
  1464. Else If DoSubAddOpt(p) Then Continue
  1465. End;
  1466. A_TEST, A_OR:
  1467. {removes the line marked with (x) from the sequence
  1468. And/or/xor/add/sub/... $x, %y
  1469. test/or %y, %y (x)
  1470. j(n)z _Label
  1471. as the first instruction already adjusts the ZF}
  1472. Begin
  1473. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1474. If GetLastInstruction(p, hp1) And
  1475. (pai(hp1)^.typ = ait_instruction) Then
  1476. Case Paicpu(hp1)^.opcode Of
  1477. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1478. Begin
  1479. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1480. Begin
  1481. hp1 := pai(p^.next);
  1482. asml^.remove(p);
  1483. dispose(p, done);
  1484. p := pai(hp1);
  1485. continue
  1486. End;
  1487. End;
  1488. A_DEC, A_INC, A_NEG:
  1489. Begin
  1490. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1491. Begin
  1492. Case Paicpu(hp1)^.opcode Of
  1493. A_DEC, A_INC:
  1494. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1495. Begin
  1496. Case Paicpu(hp1)^.opcode Of
  1497. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1498. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1499. End;
  1500. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1501. Paicpu(hp1)^.LoadConst(0,1);
  1502. Paicpu(hp1)^.ops:=2;
  1503. End
  1504. End;
  1505. hp1 := pai(p^.next);
  1506. asml^.remove(p);
  1507. dispose(p, done);
  1508. p := pai(hp1);
  1509. continue
  1510. End;
  1511. End
  1512. End
  1513. Else
  1514. End;
  1515. A_XOR:
  1516. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1517. (Paicpu(p)^.oper[1].typ = top_reg) And
  1518. (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
  1519. { temporarily change this to 'mov reg,0' to make it easier }
  1520. { for the CSE. Will be changed back in pass 2 }
  1521. begin
  1522. paicpu(p)^.opcode := A_MOV;
  1523. paicpu(p)^.loadconst(0,0);
  1524. end;
  1525. End;
  1526. end; { if is_jmp }
  1527. End;
  1528. { ait_label:
  1529. Begin
  1530. If Not(Pai_Label(p)^.l^.is_used)
  1531. Then
  1532. Begin
  1533. hp1 := Pai(p^.next);
  1534. AsmL^.Remove(p);
  1535. Dispose(p, Done);
  1536. p := hp1;
  1537. Continue
  1538. End;
  1539. End;}
  1540. End;
  1541. p:=pai(p^.next);
  1542. end;
  1543. end;
  1544. {$ifdef foldArithOps}
  1545. Function IsArithOp(opcode: TAsmOp): Boolean;
  1546. Begin
  1547. IsArithOp := False;
  1548. Case opcode Of
  1549. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR: IsArithOp := True
  1550. End;
  1551. End;
  1552. {$endif foldArithOps}
  1553. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1554. function CanBeCMOV(p : pai) : boolean;
  1555. begin
  1556. CanBeCMOV:=assigned(p) and (p^.typ=ait_instruction) and
  1557. (paicpu(p)^.opcode=A_MOV) and
  1558. (paicpu(p)^.opsize in [S_L,S_W]) and
  1559. (paicpu(p)^.oper[0].typ in [top_reg,top_ref]) and
  1560. (paicpu(p)^.oper[1].typ in [top_reg,top_ref]);
  1561. end;
  1562. var
  1563. p,hp1,hp2: pai;
  1564. {$ifdef USECMOV}
  1565. l : longint;
  1566. condition : tasmcond;
  1567. hp3: pai;
  1568. {$endif USECMOV}
  1569. {$ifdef foldArithOps}
  1570. UsedRegs, TmpUsedRegs: TRegSet;
  1571. {$endif foldArithOps}
  1572. Begin
  1573. P := BlockStart;
  1574. {$ifdef foldArithOps}
  1575. UsedRegs := [];
  1576. {$endif foldArithOps}
  1577. While (P <> BlockEnd) Do
  1578. Begin
  1579. {$ifdef foldArithOps}
  1580. UpdateUsedRegs(UsedRegs, Pai(p^.next));
  1581. {$endif foldArithOps}
  1582. Case P^.Typ Of
  1583. Ait_Instruction:
  1584. Begin
  1585. Case Paicpu(p)^.opcode Of
  1586. A_CALL:
  1587. If (AktOptProcessor < ClassP6) And
  1588. GetNextInstruction(p, hp1) And
  1589. (hp1^.typ = ait_instruction) And
  1590. (paicpu(hp1)^.opcode = A_JMP) Then
  1591. Begin
  1592. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1593. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1594. InsertLLItem(AsmL, p^.previous, p, hp2);
  1595. Paicpu(p)^.opcode := A_JMP;
  1596. AsmL^.Remove(hp1);
  1597. Dispose(hp1, Done)
  1598. End;
  1599. {$ifdef USECMOV}
  1600. A_Jcc:
  1601. if (aktspecificoptprocessor=ClassP6) then
  1602. begin
  1603. { check for
  1604. jCC xxx
  1605. <several movs>
  1606. xxx:
  1607. }
  1608. l:=0;
  1609. GetNextInstruction(p, hp1);
  1610. while assigned(hp1) And
  1611. CanBeCMOV(hp1) do
  1612. begin
  1613. inc(l);
  1614. GetNextInstruction(hp1,hp1);
  1615. end;
  1616. if assigned(hp1) then
  1617. begin
  1618. if FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1619. begin
  1620. if (l<=4) and (l>0) then
  1621. begin
  1622. condition:=inverse_cond[paicpu(p)^.condition];
  1623. GetNextInstruction(p,hp1);
  1624. asml^.remove(p);
  1625. dispose(p,done);
  1626. p:=hp1;
  1627. repeat
  1628. paicpu(hp1)^.opcode:=A_CMOVcc;
  1629. paicpu(hp1)^.condition:=condition;
  1630. GetNextInstruction(hp1,hp1);
  1631. until not(assigned(hp1)) or
  1632. not(CanBeCMOV(hp1));
  1633. asml^.remove(hp1);
  1634. dispose(hp1,done);
  1635. continue;
  1636. end;
  1637. end
  1638. else
  1639. begin
  1640. { check further for
  1641. jCC xxx
  1642. <several movs>
  1643. jmp yyy
  1644. xxx:
  1645. <several movs>
  1646. yyy:
  1647. }
  1648. { hp2 points to jmp xxx }
  1649. hp2:=hp1;
  1650. { skip hp1 to xxx }
  1651. GetNextInstruction(hp1, hp1);
  1652. if assigned(hp2) and
  1653. assigned(hp1) and
  1654. (l<=3) and
  1655. (hp2^.typ=ait_instruction) and
  1656. (paicpu(hp2)^.is_jmp) and
  1657. (paicpu(hp2)^.condition=C_None) and
  1658. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1659. begin
  1660. l:=0;
  1661. while assigned(hp1) And
  1662. CanBeCMOV(hp1) do
  1663. begin
  1664. inc(l);
  1665. GetNextInstruction(hp1, hp1);
  1666. end;
  1667. end;
  1668. {
  1669. if assigned(hp1) and
  1670. FindLabel(PAsmLabel(paicpu(hp2)^.oper[0].sym),hp1) then
  1671. begin
  1672. condition:=inverse_cond[paicpu(p)^.condition];
  1673. GetNextInstruction(p,hp1);
  1674. asml^.remove(p);
  1675. dispose(p,done);
  1676. p:=hp1;
  1677. repeat
  1678. paicpu(hp1)^.opcode:=A_CMOVcc;
  1679. paicpu(hp1)^.condition:=condition;
  1680. GetNextInstruction(hp1,hp1);
  1681. until not(assigned(hp1)) or
  1682. not(CanBeCMOV(hp1));
  1683. hp2:=hp1^.next;
  1684. condition:=inverse_cond[condition];
  1685. asml^.remove(hp1^.next)
  1686. dispose(hp1^.next,done);
  1687. asml^.remove(hp1);
  1688. dispose(hp1,done);
  1689. continue;
  1690. end;
  1691. }
  1692. end;
  1693. end;
  1694. end;
  1695. {$endif USECMOV}
  1696. A_MOV:
  1697. Begin
  1698. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1699. (Paicpu(p)^.oper[1].typ = top_reg) And
  1700. GetNextInstruction(p, hp1) And
  1701. (hp1^.typ = ait_Instruction) And
  1702. ((Paicpu(hp1)^.opcode = A_MOV) or
  1703. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1704. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1705. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1706. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1707. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1708. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1709. (Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
  1710. {mov reg1, reg2
  1711. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1712. Begin
  1713. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1714. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1715. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1716. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1717. AsmL^.Remove(p);
  1718. Dispose(p, Done);
  1719. p := hp1;
  1720. Continue;
  1721. End
  1722. {$ifdef foldArithOps}
  1723. Else If (Paicpu(p)^.oper[0].typ = top_ref) And
  1724. GetNextInstruction(p,hp1) And
  1725. (hp1^.typ = ait_instruction) And
  1726. IsArithOp(Paicpu(hp1)^.opcode) And
  1727. (Paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) And
  1728. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1729. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) And
  1730. GetNextInstruction(hp1,hp2) And
  1731. (hp2^.typ = ait_instruction) And
  1732. (Paicpu(hp2)^.opcode = A_MOV) And
  1733. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  1734. (Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  1735. (Paicpu(hp2)^.oper[1].typ = top_ref) Then
  1736. Begin
  1737. TmpUsedRegs := UsedRegs;
  1738. UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
  1739. If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
  1740. Not(RegUsedAfterInstruction(Reg32(Paicpu(p)^.oper[1].reg),
  1741. hp2, TmpUsedRegs)))
  1742. Then
  1743. { change mov (ref), reg }
  1744. { add/sub/or/... reg2/$const, reg }
  1745. { mov (reg), ref }
  1746. { # release reg }
  1747. { to add/sub/or/... reg2/$const, (ref) }
  1748. Begin
  1749. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
  1750. AsmL^.Remove(p);
  1751. AsmL^.Remove(hp2);
  1752. Dispose(p,done);
  1753. Dispose(hp2,Done);
  1754. p := hp1
  1755. End;
  1756. End
  1757. {$endif foldArithOps}
  1758. else if (Paicpu(p)^.oper[0].typ = Top_Const) And
  1759. (Paicpu(p)^.oper[0].val = 0) And
  1760. (Paicpu(p)^.oper[1].typ = Top_Reg) Then
  1761. { change "mov $0, %reg" into "xor %reg, %reg" }
  1762. Begin
  1763. Paicpu(p)^.opcode := A_XOR;
  1764. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1765. End
  1766. End;
  1767. A_MOVZX:
  1768. Begin
  1769. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1770. If (Paicpu(p)^.oper[0].typ = top_reg)
  1771. Then
  1772. Case Paicpu(p)^.opsize of
  1773. S_BL:
  1774. Begin
  1775. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1776. Not(CS_LittleSize in aktglobalswitches) And
  1777. (aktoptprocessor = ClassP5)
  1778. Then
  1779. {Change "movzbl %reg1, %reg2" to
  1780. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1781. PentiumMMX}
  1782. Begin
  1783. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1784. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1785. InsertLLItem(AsmL,p^.previous, p, hp1);
  1786. Paicpu(p)^.opcode := A_MOV;
  1787. Paicpu(p)^.changeopsize(S_B);
  1788. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1789. End;
  1790. End;
  1791. End
  1792. Else
  1793. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1794. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1795. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1796. Not(CS_LittleSize in aktglobalswitches) And
  1797. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1798. (aktoptprocessor = ClassP5) And
  1799. (Paicpu(p)^.opsize = S_BL)
  1800. Then
  1801. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1802. Pentium and PentiumMMX}
  1803. Begin
  1804. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1805. Paicpu(p)^.oper[1].reg));
  1806. Paicpu(p)^.opcode := A_MOV;
  1807. Paicpu(p)^.changeopsize(S_B);
  1808. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1809. InsertLLItem(AsmL,p^.previous, p, hp1);
  1810. End;
  1811. End;
  1812. End;
  1813. End;
  1814. End;
  1815. p := Pai(p^.next)
  1816. End;
  1817. End;
  1818. End.
  1819. {
  1820. $Log$
  1821. Revision 1.82 2000-01-24 12:17:24 florian
  1822. * some improvemenst to cmov support
  1823. * disabled excpetion frame generation in cosntructors temporarily
  1824. Revision 1.81 2000/01/23 21:29:17 florian
  1825. * CMOV support in optimizer (in define USECMOV)
  1826. + start of support of exceptions in constructors
  1827. Revision 1.80 2000/01/22 16:05:15 jonas
  1828. + change "lea x(reg),reg" to "add x,reg" (-dnewoptimizations)
  1829. * detection whether edi is used after instructions (since regalloc
  1830. info for it is now available)
  1831. * better regUsedAfterInstruction function
  1832. Revision 1.79 2000/01/21 11:26:19 pierre
  1833. * bug fix for bug 802
  1834. Revision 1.78 2000/01/11 17:14:49 jonas
  1835. * fixed a serious memory leak
  1836. Revision 1.77 2000/01/09 12:35:02 jonas
  1837. * changed edi allocation to use getexplicitregister32/ungetregister
  1838. (adapted tgeni386 a bit for this) and enabled it by default
  1839. * fixed very big and stupid bug of mine in cg386mat that broke the
  1840. include() code (and make cycle :( ) if you compiled without
  1841. -dnewoptimizations
  1842. Revision 1.76 2000/01/07 01:14:30 peter
  1843. * updated copyright to 2000
  1844. Revision 1.75 1999/12/30 17:56:44 peter
  1845. * fixed and;jmp being translated into test;jmp
  1846. Revision 1.74 1999/12/05 16:48:43 jonas
  1847. * CSE of constant loading in regs works properly again
  1848. + if a constant is stored into memory using "mov const, ref" and
  1849. there is a reg that contains this const, it is changed into
  1850. "mov reg, ref"
  1851. Revision 1.73 1999/12/02 11:26:41 peter
  1852. * newoptimizations define added
  1853. Revision 1.72 1999/11/30 10:40:45 peter
  1854. + ttype, tsymlist
  1855. Revision 1.71 1999/11/27 23:47:55 jonas
  1856. + change "mov var,reg; add/shr/... x,reg; mov reg,var" to
  1857. "add/shr/... x,var" (if x is a const or reg, suggestion from Peter)
  1858. Enable with -dfoldArithOps
  1859. Revision 1.70 1999/11/21 13:09:41 jonas
  1860. * fixed some missed optimizations because 8bit regs were not always
  1861. taken into account
  1862. Revision 1.69 1999/11/13 19:03:56 jonas
  1863. * don't remove align objects between JMP's and labels
  1864. Revision 1.68 1999/11/06 16:24:00 jonas
  1865. * getfinaldestination works completely again (a lot of functionality
  1866. got lost in the conversion resulting from the removal of
  1867. ait_labeled_instruction)
  1868. Revision 1.67 1999/11/06 14:34:23 peter
  1869. * truncated log to 20 revs
  1870. Revision 1.66 1999/09/27 23:44:55 peter
  1871. * procinfo is now a pointer
  1872. * support for result setting in sub procedure
  1873. Revision 1.65 1999/09/05 14:27:19 florian
  1874. + fld reg;fxxx to fxxxr reg optimization
  1875. Revision 1.64 1999/08/25 12:00:02 jonas
  1876. * changed pai386, paippc and paiapha (same for tai*) to paicpu (taicpu)
  1877. Revision 1.63 1999/08/23 10:20:46 jonas
  1878. * fixed pop/push optmization
  1879. Revision 1.62 1999/08/10 12:30:00 pierre
  1880. * avoid unused locals
  1881. Revision 1.61 1999/08/05 15:02:48 jonas
  1882. * "add/sub const,%esp;sub $2,%esp" wasn't always optimized
  1883. Revision 1.60 1999/08/04 00:23:16 florian
  1884. * renamed i386asm and i386base to cpuasm and cpubase
  1885. Revision 1.59 1999/08/03 17:13:28 jonas
  1886. * fix for sar/shr-shl optimization
  1887. Revision 1.58 1999/07/30 18:17:55 jonas
  1888. * fix so (,reg) gets optimized to (reg)
  1889. Revision 1.57 1999/07/01 18:12:16 jonas
  1890. * enabled "mov reg1,reg2;mov (reg2,..), reg2" also if the second mov is
  1891. a movzx or movsx
  1892. Revision 1.56 1999/06/23 12:33:52 jonas
  1893. * merged
  1894. Revision 1.54.2.2 1999/06/23 11:55:08 jonas
  1895. * fixed bug in "mov mem1,reg1;mov reg1,mem2;mov mem2,reg2" optimization
  1896. Revision 1.55 1999/06/18 09:55:31 peter
  1897. * merged
  1898. Revision 1.54.2.1 1999/06/18 09:52:40 peter
  1899. * pop;push -> mov (esp),reg always instead of being removed
  1900. Revision 1.54 1999/05/27 19:44:49 peter
  1901. * removed oldasm
  1902. * plabel -> pasmlabel
  1903. * -a switches to source writing automaticly
  1904. * assembler readers OOPed
  1905. * asmsymbol automaticly external
  1906. * jumptables and other label fixes for asm readers
  1907. Revision 1.53 1999/05/12 00:19:52 peter
  1908. * removed R_DEFAULT_SEG
  1909. * uniform float names
  1910. Revision 1.52 1999/05/05 16:19:04 jonas
  1911. + remove the segment prefixes from LEA instructions
  1912. Revision 1.51 1999/05/05 10:05:54 florian
  1913. * a delphi compiled compiler recompiles ppc
  1914. Revision 1.50 1999/05/02 21:33:55 florian
  1915. * several bugs regarding -Or fixed
  1916. Revision 1.49 1999/05/02 14:26:31 peter
  1917. * fixed dec -> sub $1 opt which didn't set ops=2
  1918. }