| .. | 
		
		
			
				
					| aasmcpu.pas | 20dbda751a
					* fixed sparc compilation after addr_lo/hi changes | 18 年之前 | 
		
			
				
					| aoptcpu.pas | da910d654c
					+ SPARC: two more peephole optimizations | 11 年之前 | 
		
			
				
					| aoptcpub.pas | 2f5ce095ce
					* RefsHaveIndexReg -> cpurefshaveindexreg | 13 年之前 | 
		
			
				
					| aoptcpud.pas | 790a4fe2d3
					* log and id tags removed | 20 年之前 | 
		
			
				
					| cgcpu.pas | 534ecbda9f
					* SPARC: r26561 caused a_op_const_reg_reg used for zero-extending 8-bit values to be optimized away. Fixed by replacing it with an explicit instruction. | 11 年之前 | 
		
			
				
					| cpubase.pas | eaba90dda7
					* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches. | 12 年之前 | 
		
			
				
					| cpuelf.pas | 0aa7204707
					+ Added codes of dynamic relocations to TElfTarget; since most targets use similar dynamic relocation model differing only in code values, this will allow to do majority of handling in the base class. | 13 年之前 | 
		
			
				
					| cpugas.pas | 5e6669890a
					Handle asmextraopt in powerpc, mips and sparc assemblers | 11 年之前 | 
		
			
				
					| cpuinfo.pas | e190f76dd9
					* removed spaces from sparc cpu name strings so they can be much easier used | 13 年之前 | 
		
			
				
					| cpunode.pas | b270a1922b
					* reverts r18960, should solve sparc trouble | 14 年之前 | 
		
			
				
					| cpupara.pas | e9268a0a14
					* synchronised with trunk up till r26975 | 11 年之前 | 
		
			
				
					| cpupi.pas | 176d8434e4
					* SPARC: completely rewrote PIC-related code, got it twice shorter in source lines and much less instructions in generated code. | 12 年之前 | 
		
			
				
					| cputarg.pas | 7587145320
					Add possibility to test sparc elf generator with -dTEST_AGSPARC_ELF | 13 年之前 | 
		
			
				
					| hlcgcpu.pas | 72e9cfee24
					* create/destroy also the high level code generator for all architectures, | 14 年之前 | 
		
			
				
					| itcpugas.pas | 790a4fe2d3
					* log and id tags removed | 20 年之前 | 
		
			
				
					| ncpuadd.pas | 720b9bf560
					* SPARC: reworked 64-bit comparisons so their result is always in flags. Comparisons are emitted as subtractions, sides are optionally swapped to avoid using Z flag (since it is not set correctly in multi-word subtraction). This generates significantly shorter code: when both sides are in registers it is just 3 instructions for equal/unequal and 2 instructions otherwise. | 11 年之前 | 
		
			
				
					| ncpucall.pas | 51825b6f2e
					compiler: change ret_in_param to accept tabstractprocdef instead of tproccalloption to allow check more options (required for record constructor implementation) | 12 年之前 | 
		
			
				
					| ncpucnv.pas | 58cc531dd9
					* SPARC: convert from int64/qword to float using genmath helpers. Removes dependency on softfloat code. | 12 年之前 | 
		
			
				
					| ncpuinln.pas | 6b8aed593f
					* remove registers{int/mmx/fpu} from firstpass | 18 年之前 | 
		
			
				
					| ncpumat.pas | cda81e1d18
					* SPARC: emit "x shl 1" as "x+x", it yields shorter code. | 11 年之前 | 
		
			
				
					| ncpuset.pas | c673c32ad9
					+ SPARC: generate position-independent case jump tables, as specified by ABI. | 11 年之前 | 
		
			
				
					| opcode.inc | 9a486d73ba
					+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently. | 12 年之前 | 
		
			
				
					| racpu.pas | 18eb495d0f
					* give a regular error message instead of an internal error on x86 | 18 年之前 | 
		
			
				
					| racpugas.pas | eaba90dda7
					* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches. | 12 年之前 | 
		
			
				
					| rgcpu.pas | e9268a0a14
					* synchronised with trunk up till r26975 | 11 年之前 | 
		
			
				
					| rspcon.inc | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| rspdwrf.inc | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| rspnor.inc | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| rspnum.inc | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| rsprni.inc | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| rspsri.inc | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| rspstab.inc | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| rspstd.inc | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| rspsup.inc | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| spreg.dat | c3da1aa542
					Reenabled D0-D30 registers | 13 年之前 | 
		
			
				
					| strinst.inc | 9a486d73ba
					+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently. | 12 年之前 |