| .. |
|
aasmcpu.pas
|
bc0c94c204
fpcdefs.inc: Set fpc_compiler_has_fixup_jmps for powerpcXX and mips CPUs.
|
13 anni fa |
|
aoptcpu.pas
|
0c8546f94c
* more MIPS code of David Zhang integrated
|
15 anni fa |
|
aoptcpub.pas
|
93e0dd9c2f
* Patch from Fuxin Zhang: other mips and mipsel CPUs changes
|
13 anni fa |
|
aoptcpud.pas
|
0c8546f94c
* more MIPS code of David Zhang integrated
|
15 anni fa |
|
cgcpu.pas
|
db72b8d7fd
* TCGMips.a_loadfpu_reg_cgpara: temps of type Double need 8-byte alignment, according to description of sdcX/ldcX instructions. Using TCGSize2Size to specify alignment is somewhat weird, but it is being used in other CPU back-ends and looks working.
|
12 anni fa |
|
cpubase.pas
|
e327b4581c
Use TRegNameTable instead of array[tregisterindex] of string[10]
|
12 anni fa |
|
cpugas.pas
|
e6863aeb80
* typo fixed, patch by Mark Morgan Lloyd
|
12 anni fa |
|
cpuinfo.pas
|
305206354a
Add arch and abi values for mips cpu
|
13 anni fa |
|
cpunode.pas
|
a3ef2b42a8
Remove more TABs in sources
|
13 anni fa |
|
cpupara.pas
|
bf46526cc7
Set register_used boolean only for calleeside
|
13 anni fa |
|
cpupi.pas
|
7bd7cf275c
handle po_nostackframe for calc_stack_size
|
13 anni fa |
|
cputarg.pas
|
37a7c1fc25
Add Dwarf debug info generation by default for mips cpu
|
13 anni fa |
|
hlcgcpu.pas
|
a3ef2b42a8
Remove more TABs in sources
|
13 anni fa |
|
itcpugas.pas
|
3d2a27c66c
* fix fpu register type
|
13 anni fa |
|
mipsreg.dat
|
944d500d55
Change std reg names to allow use with GAS assembler
|
13 anni fa |
|
ncpuadd.pas
|
93e0dd9c2f
* Patch from Fuxin Zhang: other mips and mipsel CPUs changes
|
13 anni fa |
|
ncpucall.pas
|
a3ef2b42a8
Remove more TABs in sources
|
13 anni fa |
|
ncpucnv.pas
|
a3ef2b42a8
Remove more TABs in sources
|
13 anni fa |
|
ncpuinln.pas
|
f54365db94
* adapted more fpc-mips stuff to trunk
|
15 anni fa |
|
ncpuld.pas
|
c2cd8246cb
Override tloadnode.pass_1 to for use of got for shared library variables and genrate_picvaraccess
|
13 anni fa |
|
ncpumat.pas
|
d01ec10f45
Fix tw22326 for mips CPU
|
13 anni fa |
|
ncpuset.pas
|
b023627f6a
* converted tcgcasenode.pass_generate_code() to hlcgobj
|
14 anni fa |
|
opcode.inc
|
87b6bb5053
+ Add .cpXXX pseudo-instruction for PIC code
|
13 anni fa |
|
racpugas.pas
|
a3ef2b42a8
Remove more TABs in sources
|
13 anni fa |
|
rgcpu.pas
|
de4a96f96d
* fixes several register allocation related mips issues
|
13 anni fa |
|
rmipscon.inc
|
de4a96f96d
* fixes several register allocation related mips issues
|
13 anni fa |
|
rmipsdwf.inc
|
f58fcdf401
+ basic mips stuff
|
20 anni fa |
|
rmipsgas.inc
|
ae37b9f5b9
* fix floating point registers gas name
|
13 anni fa |
|
rmipsgri.inc
|
ae37b9f5b9
* fix floating point registers gas name
|
13 anni fa |
|
rmipsgss.inc
|
f58fcdf401
+ basic mips stuff
|
20 anni fa |
|
rmipsnor.inc
|
f58fcdf401
+ basic mips stuff
|
20 anni fa |
|
rmipsnum.inc
|
de4a96f96d
* fixes several register allocation related mips issues
|
13 anni fa |
|
rmipsrni.inc
|
f58fcdf401
+ basic mips stuff
|
20 anni fa |
|
rmipssri.inc
|
944d500d55
Change std reg names to allow use with GAS assembler
|
13 anni fa |
|
rmipssta.inc
|
f58fcdf401
+ basic mips stuff
|
20 anni fa |
|
rmipsstd.inc
|
944d500d55
Change std reg names to allow use with GAS assembler
|
13 anni fa |
|
rmipssup.inc
|
de4a96f96d
* fixes several register allocation related mips issues
|
13 anni fa |
|
strinst.inc
|
87b6bb5053
+ Add .cpXXX pseudo-instruction for PIC code
|
13 anni fa |
sergei
db72b8d7fd
* TCGMips.a_loadfpu_reg_cgpara: temps of type Double need 8-byte alignment, according to description of sdcX/ldcX instructions. Using TCGSize2Size to specify alignment is somewhat weird, but it is being used in other CPU back-ends and looks working.