cgcpu.pas 65 KB

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  1. {
  2. Copyright (c) 1998-2009 by Florian Klaempfl and David Zhang
  3. This unit implements the code generator for the MIPSEL
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit cgcpu;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. globtype, parabase,
  22. cgbase, cgutils, cgobj, cg64f32,
  23. aasmbase, aasmtai, aasmcpu, aasmdata,
  24. cpubase, cpuinfo,
  25. node, symconst, SymType, symdef,
  26. rgcpu;
  27. type
  28. TCgMPSel = class(tcg)
  29. public
  30. procedure init_register_allocators; override;
  31. procedure done_register_allocators; override;
  32. function getfpuregister(list: tasmlist; size: Tcgsize): Tregister; override;
  33. /// { needed by cg64 }
  34. procedure make_simple_ref(list: tasmlist; var ref: treference);
  35. procedure make_simple_ref_fpu(list: tasmlist; var ref: treference);
  36. procedure handle_load_store(list: tasmlist; isstore: boolean; op: tasmop; reg: tregister; ref: treference);
  37. procedure handle_load_store_fpu(list: tasmlist; isstore: boolean; op: tasmop; reg: tregister; ref: treference);
  38. procedure handle_reg_const_reg(list: tasmlist; op: Tasmop; src: tregister; a: aint; dst: tregister);
  39. { parameter }
  40. procedure a_param_const(list: tasmlist; size: tcgsize; a: aint; const paraloc: TCGPara); override;
  41. procedure a_param_ref(list: tasmlist; sz: tcgsize; const r: TReference; const paraloc: TCGPara); override;
  42. procedure a_paramaddr_ref(list: tasmlist; const r: TReference; const paraloc: TCGPara); override;
  43. procedure a_paramfpu_reg(list: tasmlist; size: tcgsize; const r: tregister; const paraloc: TCGPara); override;
  44. procedure a_paramfpu_ref(list: tasmlist; size: tcgsize; const ref: treference; const paraloc: TCGPara); override;
  45. procedure a_call_name(list: tasmlist; const s: string; weak : boolean); override;
  46. procedure a_call_reg(list: tasmlist; Reg: TRegister); override;
  47. { General purpose instructions }
  48. procedure a_op_const_reg(list: tasmlist; Op: TOpCG; size: tcgsize; a: aint; reg: TRegister); override;
  49. procedure a_op_reg_reg(list: tasmlist; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
  50. procedure a_op_const_reg_reg(list: tasmlist; op: TOpCg; size: tcgsize; a: aint; src, dst: tregister); override;
  51. procedure a_op_reg_reg_reg(list: tasmlist; op: TOpCg; size: tcgsize; src1, src2, dst: tregister); override;
  52. procedure a_op_const_reg_reg_checkoverflow(list: tasmlist; op: TOpCg; size: tcgsize; a: aint; src, dst: tregister; setflags: boolean; var ovloc: tlocation); override;
  53. procedure a_op_reg_reg_reg_checkoverflow(list: tasmlist; op: TOpCg; size: tcgsize; src1, src2, dst: tregister; setflags: boolean; var ovloc: tlocation); override;
  54. { move instructions }
  55. procedure a_load_const_reg(list: tasmlist; size: tcgsize; a: aint; reg: tregister); override;
  56. procedure a_load_const_ref(list: tasmlist; size: tcgsize; a: aint; const ref: TReference); override;
  57. procedure a_load_reg_ref(list: tasmlist; FromSize, ToSize: TCgSize; reg: TRegister; const ref: TReference); override;
  58. procedure a_load_ref_reg(list: tasmlist; FromSize, ToSize: TCgSize; const ref: TReference; reg: tregister); override;
  59. procedure a_load_reg_reg(list: tasmlist; FromSize, ToSize: TCgSize; reg1, reg2: tregister); override;
  60. procedure a_loadaddr_ref_reg(list: tasmlist; const ref: TReference; r: tregister); override;
  61. { fpu move instructions }
  62. procedure a_loadfpu_reg_reg(list: tasmlist; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  63. procedure a_loadfpu_ref_reg(list: tasmlist; fromsize, tosize: tcgsize; const ref: TReference; reg: tregister); override;
  64. procedure a_loadfpu_reg_ref(list: tasmlist; fromsize, tosize: tcgsize; reg: tregister; const ref: TReference); override;
  65. { comparison operations }
  66. procedure a_cmp_const_reg_label(list: tasmlist; size: tcgsize; cmp_op: topcmp; a: aint; reg: tregister; l: tasmlabel); override;
  67. procedure a_cmp_reg_reg_label(list: tasmlist; size: tcgsize; cmp_op: topcmp; reg1, reg2: tregister; l: tasmlabel); override;
  68. procedure a_jmp_always(List: tasmlist; l: TAsmLabel); override;
  69. procedure a_jmp_name(list: tasmlist; const s: string); override;
  70. procedure a_jmp_cond(list: tasmlist; cond: TOpCmp; l: tasmlabel); { override;}
  71. procedure g_overflowCheck(List: tasmlist; const Loc: TLocation; def: TDef); override;
  72. procedure g_overflowCheck_loc(List: tasmlist; const Loc: TLocation; def: TDef; ovloc: tlocation); override;
  73. procedure g_proc_entry(list: tasmlist; localsize: longint; nostackframe: boolean); override;
  74. procedure g_proc_exit(list: tasmlist; parasize: longint; nostackframe: boolean); override;
  75. procedure g_concatcopy(list: tasmlist; const Source, dest: treference; len: aint); override;
  76. procedure g_concatcopy_unaligned(list: tasmlist; const Source, dest: treference; len: aint); override;
  77. procedure g_concatcopy_move(list: tasmlist; const Source, dest: treference; len: aint);
  78. procedure g_intf_wrapper(list: tasmlist; procdef: tprocdef; const labelname: string; ioffset: longint); override;
  79. end;
  80. TCg64MPSel = class(tcg64f32)
  81. public
  82. procedure a_load64_reg_ref(list: tasmlist; reg: tregister64; const ref: treference); override;
  83. procedure a_load64_ref_reg(list: tasmlist; const ref: treference; reg: tregister64); override;
  84. procedure a_param64_ref(list: tasmlist; const r: treference; const paraloc: tcgpara); override;
  85. procedure a_op64_reg_reg(list: tasmlist; op: TOpCG; size: tcgsize; regsrc, regdst: TRegister64); override;
  86. procedure a_op64_const_reg(list: tasmlist; op: TOpCG; size: tcgsize; Value: int64; regdst: TRegister64); override;
  87. procedure a_op64_const_reg_reg(list: tasmlist; op: TOpCG; size: tcgsize; Value: int64; regsrc, regdst: tregister64); override;
  88. procedure a_op64_reg_reg_reg(list: tasmlist; op: TOpCG; size: tcgsize; regsrc1, regsrc2, regdst: tregister64); override;
  89. procedure a_op64_const_reg_reg_checkoverflow(list: tasmlist; op: TOpCG; size: tcgsize; Value: int64; regsrc, regdst: tregister64; setflags: boolean; var ovloc: tlocation); override;
  90. procedure a_op64_reg_reg_reg_checkoverflow(list: tasmlist; op: TOpCG; size: tcgsize; regsrc1, regsrc2, regdst: tregister64; setflags: boolean; var ovloc: tlocation); override;
  91. end;
  92. implementation
  93. uses
  94. globals, verbose, systems, cutils,
  95. paramgr, fmodule,
  96. tgobj,
  97. procinfo, cpupi;
  98. var
  99. cgcpu_calc_stackframe_size: aint;
  100. function f_TOpCG2AsmOp(op: TOpCG; size: tcgsize): TAsmOp;
  101. begin
  102. if size = OS_32 then
  103. case op of
  104. OP_ADD: { simple addition }
  105. f_TOpCG2AsmOp := A_ADDU;
  106. OP_AND: { simple logical and }
  107. f_TOpCG2AsmOp := A_AND;
  108. OP_DIV: { simple unsigned division }
  109. f_TOpCG2AsmOp := A_DIVU;
  110. OP_IDIV: { simple signed division }
  111. f_TOpCG2AsmOp := A_DIV;
  112. OP_IMUL: { simple signed multiply }
  113. f_TOpCG2AsmOp := A_MULT;
  114. OP_MUL: { simple unsigned multiply }
  115. f_TOpCG2AsmOp := A_MULTU;
  116. OP_NEG: { simple negate }
  117. f_TOpCG2AsmOp := A_NEGU;
  118. OP_NOT: { simple logical not }
  119. f_TOpCG2AsmOp := A_NOT;
  120. OP_OR: { simple logical or }
  121. f_TOpCG2AsmOp := A_OR;
  122. OP_SAR: { arithmetic shift-right }
  123. f_TOpCG2AsmOp := A_SRA;
  124. OP_SHL: { logical shift left }
  125. f_TOpCG2AsmOp := A_SLL;
  126. OP_SHR: { logical shift right }
  127. f_TOpCG2AsmOp := A_SRL;
  128. OP_SUB: { simple subtraction }
  129. f_TOpCG2AsmOp := A_SUBU;
  130. OP_XOR: { simple exclusive or }
  131. f_TOpCG2AsmOp := A_XOR;
  132. else
  133. InternalError(2007070401);
  134. end{ case }
  135. else
  136. case op of
  137. OP_ADD: { simple addition }
  138. f_TOpCG2AsmOp := A_ADDU;
  139. OP_AND: { simple logical and }
  140. f_TOpCG2AsmOp := A_AND;
  141. OP_DIV: { simple unsigned division }
  142. f_TOpCG2AsmOp := A_DIVU;
  143. OP_IDIV: { simple signed division }
  144. f_TOpCG2AsmOp := A_DIV;
  145. OP_IMUL: { simple signed multiply }
  146. f_TOpCG2AsmOp := A_MULT;
  147. OP_MUL: { simple unsigned multiply }
  148. f_TOpCG2AsmOp := A_MULTU;
  149. OP_NEG: { simple negate }
  150. f_TOpCG2AsmOp := A_NEGU;
  151. OP_NOT: { simple logical not }
  152. f_TOpCG2AsmOp := A_NOT;
  153. OP_OR: { simple logical or }
  154. f_TOpCG2AsmOp := A_OR;
  155. OP_SAR: { arithmetic shift-right }
  156. f_TOpCG2AsmOp := A_SRA;
  157. OP_SHL: { logical shift left }
  158. f_TOpCG2AsmOp := A_SLL;
  159. OP_SHR: { logical shift right }
  160. f_TOpCG2AsmOp := A_SRL;
  161. OP_SUB: { simple subtraction }
  162. f_TOpCG2AsmOp := A_SUBU;
  163. OP_XOR: { simple exclusive or }
  164. f_TOpCG2AsmOp := A_XOR;
  165. else
  166. InternalError(2007010701);
  167. end;{ case }
  168. end;
  169. function f_TOpCG2AsmOp_ovf(op: TOpCG; size: tcgsize): TAsmOp;
  170. begin
  171. if size = OS_32 then
  172. case op of
  173. OP_ADD: { simple addition }
  174. f_TOpCG2AsmOp_ovf := A_ADD;
  175. OP_AND: { simple logical and }
  176. f_TOpCG2AsmOp_ovf := A_AND;
  177. OP_DIV: { simple unsigned division }
  178. f_TOpCG2AsmOp_ovf := A_DIVU;
  179. OP_IDIV: { simple signed division }
  180. f_TOpCG2AsmOp_ovf := A_DIV;
  181. OP_IMUL: { simple signed multiply }
  182. f_TOpCG2AsmOp_ovf := A_MULO;
  183. OP_MUL: { simple unsigned multiply }
  184. f_TOpCG2AsmOp_ovf := A_MULOU;
  185. OP_NEG: { simple negate }
  186. f_TOpCG2AsmOp_ovf := A_NEG;
  187. OP_NOT: { simple logical not }
  188. f_TOpCG2AsmOp_ovf := A_NOT;
  189. OP_OR: { simple logical or }
  190. f_TOpCG2AsmOp_ovf := A_OR;
  191. OP_SAR: { arithmetic shift-right }
  192. f_TOpCG2AsmOp_ovf := A_SRA;
  193. OP_SHL: { logical shift left }
  194. f_TOpCG2AsmOp_ovf := A_SLL;
  195. OP_SHR: { logical shift right }
  196. f_TOpCG2AsmOp_ovf := A_SRL;
  197. OP_SUB: { simple subtraction }
  198. f_TOpCG2AsmOp_ovf := A_SUB;
  199. OP_XOR: { simple exclusive or }
  200. f_TOpCG2AsmOp_ovf := A_XOR;
  201. else
  202. InternalError(2007070403);
  203. end{ case }
  204. else
  205. case op of
  206. OP_ADD: { simple addition }
  207. f_TOpCG2AsmOp_ovf := A_ADD;
  208. OP_AND: { simple logical and }
  209. f_TOpCG2AsmOp_ovf := A_AND;
  210. OP_DIV: { simple unsigned division }
  211. f_TOpCG2AsmOp_ovf := A_DIVU;
  212. OP_IDIV: { simple signed division }
  213. f_TOpCG2AsmOp_ovf := A_DIV;
  214. OP_IMUL: { simple signed multiply }
  215. f_TOpCG2AsmOp_ovf := A_MULO;
  216. OP_MUL: { simple unsigned multiply }
  217. f_TOpCG2AsmOp_ovf := A_MULOU;
  218. OP_NEG: { simple negate }
  219. f_TOpCG2AsmOp_ovf := A_NEG;
  220. OP_NOT: { simple logical not }
  221. f_TOpCG2AsmOp_ovf := A_NOT;
  222. OP_OR: { simple logical or }
  223. f_TOpCG2AsmOp_ovf := A_OR;
  224. OP_SAR: { arithmetic shift-right }
  225. f_TOpCG2AsmOp_ovf := A_SRA;
  226. OP_SHL: { logical shift left }
  227. f_TOpCG2AsmOp_ovf := A_SLL;
  228. OP_SHR: { logical shift right }
  229. f_TOpCG2AsmOp_ovf := A_SRL;
  230. OP_SUB: { simple subtraction }
  231. f_TOpCG2AsmOp_ovf := A_SUB;
  232. OP_XOR: { simple exclusive or }
  233. f_TOpCG2AsmOp_ovf := A_XOR;
  234. else
  235. InternalError(2007010703);
  236. end;{ case }
  237. end;
  238. function f_TOp64CG2AsmOp(op: TOpCG): TAsmOp;
  239. begin
  240. case op of
  241. OP_ADD: { simple addition }
  242. f_TOp64CG2AsmOp := A_DADDU;
  243. OP_AND: { simple logical and }
  244. f_TOp64CG2AsmOp := A_AND;
  245. OP_DIV: { simple unsigned division }
  246. f_TOp64CG2AsmOp := A_DDIVU;
  247. OP_IDIV: { simple signed division }
  248. f_TOp64CG2AsmOp := A_DDIV;
  249. OP_IMUL: { simple signed multiply }
  250. f_TOp64CG2AsmOp := A_DMULO;
  251. OP_MUL: { simple unsigned multiply }
  252. f_TOp64CG2AsmOp := A_DMULOU;
  253. OP_NEG: { simple negate }
  254. f_TOp64CG2AsmOp := A_DNEGU;
  255. OP_NOT: { simple logical not }
  256. f_TOp64CG2AsmOp := A_NOT;
  257. OP_OR: { simple logical or }
  258. f_TOp64CG2AsmOp := A_OR;
  259. OP_SAR: { arithmetic shift-right }
  260. f_TOp64CG2AsmOp := A_DSRA;
  261. OP_SHL: { logical shift left }
  262. f_TOp64CG2AsmOp := A_DSLL;
  263. OP_SHR: { logical shift right }
  264. f_TOp64CG2AsmOp := A_DSRL;
  265. OP_SUB: { simple subtraction }
  266. f_TOp64CG2AsmOp := A_DSUBU;
  267. OP_XOR: { simple exclusive or }
  268. f_TOp64CG2AsmOp := A_XOR;
  269. else
  270. InternalError(2007010702);
  271. end;{ case }
  272. end;
  273. procedure TCgMPSel.make_simple_ref(list: tasmlist; var ref: treference);
  274. var
  275. tmpreg, tmpreg1: tregister;
  276. tmpref: treference;
  277. begin
  278. tmpreg := NR_NO;
  279. { Be sure to have a base register }
  280. if (ref.base = NR_NO) then
  281. begin
  282. ref.base := ref.index;
  283. ref.index := NR_NO;
  284. end;
  285. if (cs_create_pic in current_settings.moduleswitches) and
  286. assigned(ref.symbol) then
  287. begin
  288. tmpreg := GetIntRegister(list, OS_INT);
  289. reference_reset(tmpref,sizeof(aint));
  290. tmpref.symbol := ref.symbol;
  291. tmpref.refaddr := addr_pic;
  292. if not (pi_needs_got in current_procinfo.flags) then
  293. internalerror(200501161);
  294. tmpref.index := current_procinfo.got;
  295. list.concat(taicpu.op_reg_ref(A_LW, tmpreg, tmpref));
  296. ref.symbol := nil;
  297. if (ref.index <> NR_NO) then
  298. begin
  299. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg, ref.index, tmpreg));
  300. ref.index := tmpreg;
  301. end
  302. else
  303. begin
  304. if ref.base <> NR_NO then
  305. ref.index := tmpreg
  306. else
  307. ref.base := tmpreg;
  308. end;
  309. end;
  310. { When need to use LUI, do it first }
  311. if assigned(ref.symbol) or
  312. (ref.offset < simm16lo) or
  313. (ref.offset > simm16hi) then
  314. begin
  315. tmpreg := GetIntRegister(list, OS_INT);
  316. reference_reset(tmpref);
  317. tmpref.symbol := ref.symbol;
  318. tmpref.offset := ref.offset;
  319. tmpref.refaddr := addr_hi;
  320. list.concat(taicpu.op_reg_ref(A_LUI, tmpreg, tmpref));
  321. if (ref.offset = 0) and (ref.index = NR_NO) and
  322. (ref.base = NR_NO) then
  323. begin
  324. ref.refaddr := addr_lo;
  325. end
  326. else
  327. begin
  328. { Load the low part is left }
  329. tmpref.refaddr := addr_lo;
  330. list.concat(taicpu.op_reg_reg_ref(A_ADDIU, tmpreg, tmpreg, tmpref));
  331. ref.offset := 0;
  332. { symbol is loaded }
  333. ref.symbol := nil;
  334. end;
  335. if (ref.index <> NR_NO) then
  336. begin
  337. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg, ref.index, tmpreg));
  338. ref.index := tmpreg;
  339. end
  340. else
  341. begin
  342. if ref.base <> NR_NO then
  343. ref.index := tmpreg
  344. else
  345. ref.base := tmpreg;
  346. end;
  347. end;
  348. if (ref.base <> NR_NO) then
  349. begin
  350. if (ref.index <> NR_NO) and (ref.offset = 0) then
  351. begin
  352. tmpreg1 := GetIntRegister(list, OS_INT);
  353. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg1, ref.base, ref.index));
  354. ref.base := tmpreg1;
  355. ref.index := NR_NO;
  356. end
  357. else if (ref.index <> NR_NO) and
  358. ((ref.offset <> 0) or assigned(ref.symbol)) then
  359. begin
  360. if tmpreg = NR_NO then
  361. tmpreg := GetIntRegister(list, OS_INT);
  362. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg, ref.base, ref.index));
  363. ref.base := tmpreg;
  364. ref.index := NR_NO;
  365. end;
  366. end;
  367. end;
  368. procedure TCgMPSel.make_simple_ref_fpu(list: tasmlist; var ref: treference);
  369. var
  370. tmpreg, tmpreg1: tregister;
  371. tmpref: treference;
  372. begin
  373. tmpreg := NR_NO;
  374. { Be sure to have a base register }
  375. if (ref.base = NR_NO) then
  376. begin
  377. ref.base := ref.index;
  378. ref.index := NR_NO;
  379. end;
  380. if (cs_create_pic in current_settings.moduleswitches) and
  381. assigned(ref.symbol) then
  382. begin
  383. tmpreg := GetIntRegister(list, OS_INT);
  384. reference_reset(tmpref);
  385. tmpref.symbol := ref.symbol;
  386. tmpref.refaddr := addr_pic;
  387. if not (pi_needs_got in current_procinfo.flags) then
  388. internalerror(200501161);
  389. tmpref.index := current_procinfo.got;
  390. list.concat(taicpu.op_reg_ref(A_LW, tmpreg, tmpref));
  391. ref.symbol := nil;
  392. if (ref.index <> NR_NO) then
  393. begin
  394. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg, ref.index, tmpreg));
  395. ref.index := tmpreg;
  396. end
  397. else
  398. begin
  399. if ref.base <> NR_NO then
  400. ref.index := tmpreg
  401. else
  402. ref.base := tmpreg;
  403. end;
  404. end;
  405. { When need to use LUI, do it first }
  406. if (not assigned(ref.symbol)) and (ref.index = NR_NO) and
  407. (ref.offset > simm16lo + 1000) and (ref.offset < simm16hi - 1000)
  408. then
  409. exit;
  410. tmpreg1 := GetIntRegister(list, OS_INT);
  411. if assigned(ref.symbol) then
  412. begin
  413. reference_reset(tmpref);
  414. tmpref.symbol := ref.symbol;
  415. tmpref.offset := ref.offset;
  416. tmpref.refaddr := addr_hi;
  417. list.concat(taicpu.op_reg_ref(A_LUI, tmpreg1, tmpref));
  418. { Load the low part }
  419. tmpref.refaddr := addr_lo;
  420. list.concat(taicpu.op_reg_reg_ref(A_ADDIU, tmpreg1, tmpreg1, tmpref));
  421. { symbol is loaded }
  422. ref.symbol := nil;
  423. end
  424. else
  425. list.concat(taicpu.op_reg_const(A_LI, tmpreg1, ref.offset));
  426. if (ref.index <> NR_NO) then
  427. begin
  428. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg1, ref.index, tmpreg1));
  429. ref.index := NR_NO
  430. end;
  431. if ref.base <> NR_NO then
  432. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg1, ref.base, tmpreg1));
  433. ref.base := tmpreg1;
  434. ref.offset := 0;
  435. end;
  436. procedure TCgMPSel.handle_load_store(list: tasmlist; isstore: boolean; op: tasmop; reg: tregister; ref: treference);
  437. begin
  438. make_simple_ref(list, ref);
  439. list.concat(taicpu.op_reg_ref(op, reg, ref));
  440. end;
  441. procedure TCgMPSel.handle_load_store_fpu(list: tasmlist; isstore: boolean; op: tasmop; reg: tregister; ref: treference);
  442. begin
  443. make_simple_ref_fpu(list, ref);
  444. list.concat(taicpu.op_reg_ref(op, reg, ref));
  445. end;
  446. procedure TCgMPSel.handle_reg_const_reg(list: tasmlist; op: Tasmop; src: tregister; a: aint; dst: tregister);
  447. var
  448. tmpreg: tregister;
  449. begin
  450. if (a < simm16lo) or
  451. (a > simm16hi) then
  452. begin
  453. tmpreg := GetIntRegister(list, OS_INT);
  454. a_load_const_reg(list, OS_INT, a, tmpreg);
  455. list.concat(taicpu.op_reg_reg_reg(op, dst, src, tmpreg));
  456. end
  457. else
  458. list.concat(taicpu.op_reg_reg_const(op, dst, src, a));
  459. end;
  460. {****************************************************************************
  461. Assembler code
  462. ****************************************************************************}
  463. procedure TCgMPSel.init_register_allocators;
  464. begin
  465. inherited init_register_allocators;
  466. if (cs_create_pic in current_settings.moduleswitches) and
  467. (pi_needs_got in current_procinfo.flags) then
  468. begin
  469. current_procinfo.got := NR_GP;
  470. rg[R_INTREGISTER] := Trgcpu.Create(R_INTREGISTER, R_SUBD,
  471. [RS_R4, RS_R5, RS_R6, RS_R7, RS_R8, RS_R9, RS_R10, RS_R11,
  472. RS_R12, RS_R13, RS_R14 {, RS_R15 for tmp_const in ncpuadd.pas} {, RS_R24, RS_R25}],
  473. first_int_imreg, []);
  474. end
  475. else
  476. rg[R_INTREGISTER] := Trgcpu.Create(R_INTREGISTER, R_SUBD,
  477. [RS_R4, RS_R5, RS_R6, RS_R7, RS_R8, RS_R9, RS_R10, RS_R11,
  478. RS_R12, RS_R13, RS_R14 {, RS_R15 for tmp_const in ncpuadd.pas} {, RS_R24=VMT, RS_R25=PIC jump}],
  479. first_int_imreg, []);
  480. rg[R_FPUREGISTER] := trgcpu.Create(R_FPUREGISTER, R_SUBFS{R_SUBFD},
  481. [RS_F0, RS_F2, RS_F4, RS_F6,
  482. RS_F8, RS_F10, RS_F12, RS_F14,
  483. RS_F16, RS_F18, RS_F20, RS_F22,
  484. RS_F24, RS_F26, RS_F28, RS_F30],
  485. first_fpu_imreg, []);
  486. end;
  487. procedure TCgMPSel.done_register_allocators;
  488. begin
  489. rg[R_INTREGISTER].Free;
  490. rg[R_FPUREGISTER].Free;
  491. inherited done_register_allocators;
  492. end;
  493. function TCgMPSel.getfpuregister(list: tasmlist; size: Tcgsize): Tregister;
  494. begin
  495. if size = OS_F64 then
  496. Result := rg[R_FPUREGISTER].getregister(list, R_SUBFD)
  497. else
  498. Result := rg[R_FPUREGISTER].getregister(list, R_SUBFS);
  499. end;
  500. procedure TCgMPSel.a_param_const(list: tasmlist; size: tcgsize; a: aint; const paraloc: TCGPara);
  501. var
  502. Ref: TReference;
  503. begin
  504. paraloc.check_simple_location;
  505. case paraloc.location^.loc of
  506. LOC_REGISTER, LOC_CREGISTER:
  507. a_load_const_reg(list, size, a, paraloc.location^.Register);
  508. LOC_REFERENCE:
  509. begin
  510. with paraloc.location^.Reference do
  511. begin
  512. if (Index = NR_SP) and (Offset < Target_info.first_parm_offset) then
  513. InternalError(2002081104);
  514. reference_reset_base(ref, index, offset);
  515. end;
  516. a_load_const_ref(list, size, a, ref);
  517. end;
  518. else
  519. InternalError(2002122200);
  520. end;
  521. end;
  522. procedure TCgMPSel.a_param_ref(list: tasmlist; sz: TCgSize; const r: TReference; const paraloc: TCGPara);
  523. var
  524. ref: treference;
  525. tmpreg: TRegister;
  526. begin
  527. paraloc.check_simple_location;
  528. with paraloc.location^ do
  529. begin
  530. case loc of
  531. LOC_REGISTER, LOC_CREGISTER:
  532. a_load_ref_reg(list, sz, sz, r, Register);
  533. LOC_REFERENCE:
  534. begin
  535. with Reference do
  536. begin
  537. if (Index = NR_SP) and (Offset < Target_info.first_parm_offset) then
  538. InternalError(2002081104);
  539. reference_reset_base(ref, index, offset);
  540. end;
  541. tmpreg := GetIntRegister(list, OS_INT);
  542. a_load_ref_reg(list, sz, sz, r, tmpreg);
  543. a_load_reg_ref(list, sz, sz, tmpreg, ref);
  544. end;
  545. else
  546. internalerror(2002081103);
  547. end;
  548. end;
  549. end;
  550. procedure TCgMPSel.a_paramaddr_ref(list: tasmlist; const r: TReference; const paraloc: TCGPara);
  551. var
  552. Ref: TReference;
  553. TmpReg: TRegister;
  554. begin
  555. paraloc.check_simple_location;
  556. with paraloc.location^ do
  557. begin
  558. case loc of
  559. LOC_REGISTER, LOC_CREGISTER:
  560. a_loadaddr_ref_reg(list, r, Register);
  561. LOC_REFERENCE:
  562. begin
  563. reference_reset(ref);
  564. ref.base := reference.index;
  565. ref.offset := reference.offset;
  566. tmpreg := GetAddressRegister(list);
  567. a_loadaddr_ref_reg(list, r, tmpreg);
  568. a_load_reg_ref(list, OS_ADDR, OS_ADDR, tmpreg, ref);
  569. end;
  570. else
  571. internalerror(2002080701);
  572. end;
  573. end;
  574. end;
  575. procedure TCgMPSel.a_paramfpu_ref(list: tasmlist; size: tcgsize; const ref: treference; const paraloc: TCGPara);
  576. var
  577. href, href2: treference;
  578. hloc: pcgparalocation;
  579. begin
  580. href := ref;
  581. hloc := paraloc.location;
  582. while assigned(hloc) do
  583. begin
  584. case hloc^.loc of
  585. LOC_REGISTER:
  586. a_load_ref_reg(list, hloc^.size, hloc^.size, href, hloc^.Register);
  587. LOC_REFERENCE:
  588. begin
  589. reference_reset_base(href2, hloc^.reference.index, hloc^.reference.offset);
  590. a_load_ref_ref(list, hloc^.size, hloc^.size, href, href2);
  591. end;
  592. else
  593. internalerror(200408241);
  594. end;
  595. Inc(href.offset, tcgsize2size[hloc^.size]);
  596. hloc := hloc^.Next;
  597. end;
  598. end;
  599. procedure TCgMPSel.a_paramfpu_reg(list: tasmlist; size: tcgsize; const r: tregister; const paraloc: TCGPara);
  600. var
  601. href: treference;
  602. begin
  603. tg.GetTemp(list, TCGSize2Size[size], tt_normal, href);
  604. a_loadfpu_reg_ref(list, size, r, href);
  605. a_paramfpu_ref(list, size, href, paraloc);
  606. tg.Ungettemp(list, href);
  607. end;
  608. procedure TCgMPSel.a_call_name(list: tasmlist; const s: string);
  609. begin
  610. list.concat(taicpu.op_sym(A_JAL, objectlibrary.newasmsymbol(s, AB_EXTERNAL, AT_FUNCTION)));
  611. { Delay slot }
  612. list.concat(taicpu.op_none(A_NOP));
  613. end;
  614. procedure TCgMPSel.a_call_reg(list: tasmlist; Reg: TRegister);
  615. begin
  616. list.concat(taicpu.op_reg(A_JALR, reg));
  617. { Delay slot }
  618. list.concat(taicpu.op_none(A_NOP));
  619. end;
  620. {********************** load instructions ********************}
  621. procedure TCgMPSel.a_load_const_reg(list: tasmlist; size: TCGSize; a: aint; reg: TRegister);
  622. begin
  623. if (a = 0) then
  624. list.concat(taicpu.op_reg_reg(A_MOVE, reg, NR_R0))
  625. { LUI allows to set the upper 16 bits, so we'll take full advantage of it }
  626. else if (a and aint($ffff)) = 0 then
  627. list.concat(taicpu.op_reg_const(A_LUI, reg, a shr 16))
  628. else if (a >= simm16lo) and (a <= simm16hi) then
  629. list.concat(taicpu.op_reg_reg_const(A_ADDIU, reg, NR_R0, a))
  630. else if (a>=0) and (a <= 65535) then
  631. list.concat(taicpu.op_reg_reg_const(A_ORI, reg, NR_R0, a))
  632. else
  633. begin
  634. list.concat(taicpu.op_reg_const(A_LI, reg, a ));
  635. end;
  636. end;
  637. procedure TCgMPSel.a_load_const_ref(list: tasmlist; size: tcgsize; a: aint; const ref: TReference);
  638. begin
  639. if a = 0 then
  640. a_load_reg_ref(list, size, size, NR_R0, ref)
  641. else
  642. inherited a_load_const_ref(list, size, a, ref);
  643. end;
  644. procedure TCgMPSel.a_load_reg_ref(list: tasmlist; FromSize, ToSize: TCGSize; reg: tregister; const Ref: TReference);
  645. var
  646. op: tasmop;
  647. begin
  648. if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
  649. fromsize := tosize;
  650. case fromsize of
  651. { signed integer registers }
  652. OS_8,
  653. OS_S8:
  654. Op := A_SB;
  655. OS_16,
  656. OS_S16:
  657. Op := A_SH;
  658. OS_32,
  659. OS_S32:
  660. Op := A_SW;
  661. else
  662. InternalError(2002122100);
  663. end;
  664. handle_load_store(list, True, op, reg, ref);
  665. end;
  666. procedure TCgMPSel.a_load_ref_reg(list: tasmlist; FromSize, ToSize: TCgSize; const ref: TReference; reg: tregister);
  667. var
  668. op: tasmop;
  669. begin
  670. if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
  671. fromsize := tosize;
  672. case fromsize of
  673. OS_S8:
  674. Op := A_LB;{Load Signed Byte}
  675. OS_8:
  676. Op := A_LBU;{Load Unsigned Byte}
  677. OS_S16:
  678. Op := A_LH;{Load Signed Halfword}
  679. OS_16:
  680. Op := A_LHU;{Load Unsigned Halfword}
  681. OS_S32:
  682. Op := A_LW;{Load Word}
  683. OS_32:
  684. Op := A_LW;//A_LWU;{Load Unsigned Word}
  685. OS_S64,
  686. OS_64:
  687. Op := A_LD;{Load a Long Word}
  688. else
  689. InternalError(2002122101);
  690. end;
  691. handle_load_store(list, False, op, reg, ref);
  692. end;
  693. procedure TCgMPSel.a_load_reg_reg(list: tasmlist; fromsize, tosize: tcgsize; reg1, reg2: tregister);
  694. var
  695. instr: taicpu;
  696. begin
  697. if (tcgsize2size[tosize] < tcgsize2size[fromsize]) or
  698. (
  699. (tcgsize2size[tosize] = tcgsize2size[fromsize]) and
  700. (tosize <> fromsize) and not (fromsize in [OS_32, OS_S32])
  701. ) then
  702. begin
  703. case tosize of
  704. OS_8:
  705. a_op_const_reg_reg(list, OP_AND, tosize, $ff, reg1, reg2);
  706. OS_16:
  707. a_op_const_reg_reg(list, OP_AND, tosize, $ffff, reg1, reg2);
  708. OS_32,
  709. OS_S32:
  710. begin
  711. instr := taicpu.op_reg_reg(A_MOVE, reg2, reg1);
  712. list.Concat(instr);
  713. { Notify the register allocator that we have written a move instruction so
  714. it can try to eliminate it. }
  715. add_move_instruction(instr);
  716. end;
  717. OS_S8:
  718. begin
  719. list.concat(taicpu.op_reg_reg_const(A_SLL, reg2, reg1, 24));
  720. list.concat(taicpu.op_reg_reg_const(A_SRA, reg2, reg2, 24));
  721. end;
  722. OS_S16:
  723. begin
  724. list.concat(taicpu.op_reg_reg_const(A_SLL, reg2, reg1, 16));
  725. list.concat(taicpu.op_reg_reg_const(A_SRA, reg2, reg2, 16));
  726. end;
  727. else
  728. internalerror(2002090901);
  729. end;
  730. end
  731. else
  732. begin
  733. if reg1 <> reg2 then
  734. begin
  735. { same size, only a register mov required }
  736. instr := taicpu.op_reg_reg(A_MOVE, reg2, reg1);
  737. list.Concat(instr);
  738. // { Notify the register allocator that we have written a move instruction so
  739. // it can try to eliminate it. }
  740. add_move_instruction(instr);
  741. end;
  742. end;
  743. end;
  744. procedure TCgMPSel.a_loadaddr_ref_reg(list: tasmlist; const ref: TReference; r: tregister);
  745. var
  746. tmpref, href: treference;
  747. hreg, tmpreg: tregister;
  748. r_used: boolean;
  749. begin
  750. r_used := false;
  751. href := ref;
  752. if (href.base = NR_NO) and (href.index <> NR_NO) then
  753. internalerror(200306171);
  754. if (cs_create_pic in current_settings.moduleswitches) and
  755. assigned(href.symbol) then
  756. begin
  757. tmpreg := r; //GetIntRegister(list, OS_ADDR);
  758. r_used := true;
  759. reference_reset(tmpref);
  760. tmpref.symbol := href.symbol;
  761. tmpref.refaddr := addr_pic;
  762. if not (pi_needs_got in current_procinfo.flags) then
  763. internalerror(200501161);
  764. tmpref.base := current_procinfo.got;
  765. list.concat(taicpu.op_reg_ref(A_LW, tmpreg, tmpref));
  766. href.symbol := nil;
  767. if (href.index <> NR_NO) then
  768. begin
  769. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg, href.index, tmpreg));
  770. href.index := tmpreg;
  771. end
  772. else
  773. begin
  774. if href.base <> NR_NO then
  775. href.index := tmpreg
  776. else
  777. href.base := tmpreg;
  778. end;
  779. end;
  780. if assigned(href.symbol) or
  781. (href.offset < simm16lo) or
  782. (href.offset > simm16hi) then
  783. begin
  784. if (href.base = NR_NO) and (href.index = NR_NO) then
  785. hreg := r
  786. else
  787. hreg := GetAddressRegister(list);
  788. reference_reset(tmpref);
  789. tmpref.symbol := href.symbol;
  790. tmpref.offset := href.offset;
  791. tmpref.refaddr := addr_hi;
  792. list.concat(taicpu.op_reg_ref(A_LUI, hreg, tmpref));
  793. { Only the low part is left }
  794. tmpref.refaddr := addr_lo;
  795. list.concat(taicpu.op_reg_reg_ref(A_ADDIU, hreg, hreg, tmpref));
  796. if href.base <> NR_NO then
  797. begin
  798. if href.index <> NR_NO then
  799. begin
  800. list.concat(taicpu.op_reg_reg_reg(A_ADDU, hreg, href.base, hreg));
  801. list.concat(taicpu.op_reg_reg_reg(A_ADDU, r, hreg, href.index));
  802. end
  803. else
  804. list.concat(taicpu.op_reg_reg_reg(A_ADDU, r, hreg, href.base));
  805. end;
  806. end
  807. else
  808. { At least small offset, maybe base and maybe index }
  809. if (href.offset >= simm16lo) and
  810. (href.offset <= simm16hi)
  811. then
  812. begin
  813. if href.index <> NR_NO then { Both base and index }
  814. begin
  815. if href.offset = 0 then
  816. begin
  817. list.concat(taicpu.op_reg_reg_reg(A_ADDU, r, href.base, href.index));
  818. end
  819. else
  820. begin
  821. if r_used then
  822. hreg := GetAddressRegister(list)
  823. else
  824. hreg := r;
  825. list.concat(taicpu.op_reg_reg_const(A_ADDIU, hreg, href.base, href.offset));
  826. list.concat(taicpu.op_reg_reg_reg(A_ADDU, r, hreg, href.index));
  827. end
  828. end
  829. else if href.base <> NR_NO then { Only base }
  830. begin
  831. list.concat(taicpu.op_reg_reg_const(A_ADDIU, r, href.base, href.offset));
  832. end
  833. else { only offset, can be generated by absolute }
  834. a_load_const_reg(list, OS_ADDR, href.offset, r);
  835. end
  836. else
  837. internalerror(200703111);
  838. end;
  839. procedure TCgMPSel.a_loadfpu_reg_reg(list: tasmlist; fromsize, tosize: tcgsize; reg1, reg2: tregister);
  840. const
  841. FpuMovInstr: array[OS_F32..OS_F64] of TAsmOp =
  842. (A_MOV_S, A_MOV_D);
  843. var
  844. instr: taicpu;
  845. begin
  846. if reg1 <> reg2 then
  847. begin
  848. instr := taicpu.op_reg_reg(fpumovinstr[size], reg2, reg1);
  849. list.Concat(instr);
  850. { Notify the register allocator that we have written a move instruction so
  851. it can try to eliminate it. }
  852. add_move_instruction(instr);
  853. end;
  854. end;
  855. procedure TCgMPSel.a_loadfpu_ref_reg(list: tasmlist; fromsize, tosize: tcgsize; const ref: TReference; reg: tregister);
  856. var
  857. tmpref: treference;
  858. tmpreg: tregister;
  859. begin
  860. case size of
  861. OS_F32:
  862. begin
  863. handle_load_store_fpu(list, False, A_LWC1, reg, ref);
  864. end;
  865. OS_F64:
  866. begin
  867. handle_load_store_fpu(list, False, A_LDC1, reg, ref);
  868. end
  869. else
  870. InternalError(2007042701);
  871. end;
  872. end;
  873. procedure TCgMPSel.a_loadfpu_reg_ref(list: tasmlist; fromsize, tosize: tcgsize; reg: tregister; const ref: TReference);
  874. var
  875. tmpref: treference;
  876. tmpreg: tregister;
  877. begin
  878. case size of
  879. OS_F32:
  880. begin
  881. handle_load_store_fpu(list, True, A_SWC1, reg, ref);
  882. end;
  883. OS_F64:
  884. begin
  885. handle_load_store_fpu(list, True, A_SDC1, reg, ref);
  886. end
  887. else
  888. InternalError(2007042702);
  889. end;
  890. end;
  891. procedure TCgMPSel.a_op_const_reg(list: tasmlist; Op: TOpCG; size: tcgsize; a: aint; reg: TRegister);
  892. var
  893. power: longint;
  894. tmpreg1: tregister;
  895. begin
  896. if ((op = OP_MUL) or (op = OP_IMUL)) then
  897. begin
  898. if ispowerof2(a, power) then
  899. begin
  900. { can be done with a shift }
  901. if power < 32 then
  902. begin
  903. list.concat(taicpu.op_reg_reg_const(A_SLL, reg, reg, power));
  904. exit;
  905. end;
  906. end;
  907. end;
  908. if ((op = OP_SUB) or (op = OP_ADD)) then
  909. begin
  910. if (a = 0) then
  911. exit;
  912. end;
  913. if Op in [OP_NEG, OP_NOT] then
  914. internalerror(200306011);
  915. if (a = 0) then
  916. begin
  917. if (Op = OP_IMUL) or (Op = OP_MUL) then
  918. list.concat(taicpu.op_reg_reg(A_MOVE, reg, NR_R0))
  919. else
  920. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp(op, size), reg, reg, NR_R0))
  921. end
  922. else
  923. begin
  924. if op = OP_IMUL then
  925. begin
  926. tmpreg1 := GetIntRegister(list, OS_INT);
  927. a_load_const_reg(list, OS_INT, a, tmpreg1);
  928. list.concat(taicpu.op_reg_reg(A_MULT, reg, tmpreg1));
  929. list.concat(taicpu.op_reg(A_MFLO, reg));
  930. end
  931. else if op = OP_MUL then
  932. begin
  933. tmpreg1 := GetIntRegister(list, OS_INT);
  934. a_load_const_reg(list, OS_INT, a, tmpreg1);
  935. list.concat(taicpu.op_reg_reg(A_MULTU, reg, tmpreg1));
  936. list.concat(taicpu.op_reg(A_MFLO, reg));
  937. end
  938. else
  939. handle_reg_const_reg(list, f_TOpCG2AsmOp(op, size), reg, a, reg);
  940. end;
  941. end;
  942. procedure TCgMPSel.a_op_reg_reg(list: tasmlist; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  943. var
  944. a: aint;
  945. begin
  946. case Op of
  947. OP_NEG:
  948. list.concat(taicpu.op_reg_reg(A_NEG, dst, src));
  949. OP_NOT:
  950. begin
  951. list.concat(taicpu.op_reg_reg(A_NOT, dst, src));
  952. end;
  953. else
  954. begin
  955. if op = OP_IMUL then
  956. begin
  957. list.concat(taicpu.op_reg_reg(A_MULT, dst, src));
  958. list.concat(taicpu.op_reg(A_MFLO, dst));
  959. end
  960. else if op = OP_MUL then
  961. begin
  962. list.concat(taicpu.op_reg_reg(A_MULTU, dst, src));
  963. list.concat(taicpu.op_reg(A_MFLO, dst));
  964. end
  965. else
  966. begin
  967. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp(op, size), dst, dst, src));
  968. end;
  969. end;
  970. end;
  971. end;
  972. procedure TCgMPSel.a_op_const_reg_reg(list: tasmlist; op: TOpCg; size: tcgsize; a: aint; src, dst: tregister);
  973. var
  974. power: longint;
  975. tmpreg1: tregister;
  976. begin
  977. case op of
  978. OP_MUL,
  979. OP_IMUL:
  980. begin
  981. if ispowerof2(a, power) then
  982. begin
  983. { can be done with a shift }
  984. if power < 32 then
  985. list.concat(taicpu.op_reg_reg_const(A_SLL, dst, src, power))
  986. else
  987. inherited a_op_const_reg_reg(list, op, size, a, src, dst);
  988. exit;
  989. end;
  990. end;
  991. OP_SUB,
  992. OP_ADD:
  993. begin
  994. if (a = 0) then
  995. begin
  996. a_load_reg_reg(list, size, size, src, dst);
  997. exit;
  998. end;
  999. end;
  1000. end;
  1001. if op = OP_IMUL then
  1002. begin
  1003. tmpreg1 := GetIntRegister(list, OS_INT);
  1004. a_load_const_reg(list, OS_INT, a, tmpreg1);
  1005. list.concat(taicpu.op_reg_reg(A_MULT, src, tmpreg1));
  1006. list.concat(taicpu.op_reg(A_MFLO, dst));
  1007. end
  1008. else if op = OP_MUL then
  1009. begin
  1010. tmpreg1 := GetIntRegister(list, OS_INT);
  1011. a_load_const_reg(list, OS_INT, a, tmpreg1);
  1012. list.concat(taicpu.op_reg_reg(A_MULTU, src, tmpreg1));
  1013. list.concat(taicpu.op_reg(A_MFLO, dst));
  1014. end
  1015. else
  1016. handle_reg_const_reg(list, f_TOpCG2AsmOp(op, size), src, a, dst);
  1017. end;
  1018. procedure TCgMPSel.a_op_reg_reg_reg(list: tasmlist; op: TOpCg; size: tcgsize; src1, src2, dst: tregister);
  1019. begin
  1020. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp(op, size), dst, src2, src1));
  1021. end;
  1022. procedure TCgMPSel.a_op_const_reg_reg_checkoverflow(list: tasmlist; op: TOpCg; size: tcgsize; a: aint; src, dst: tregister; setflags: boolean; var ovloc: tlocation);
  1023. var
  1024. tmpreg1: tregister;
  1025. begin
  1026. ovloc.loc := LOC_VOID;
  1027. case op of
  1028. OP_SUB,
  1029. OP_ADD:
  1030. begin
  1031. if (a = 0) then
  1032. begin
  1033. a_load_reg_reg(list, size, size, src, dst);
  1034. exit;
  1035. end;
  1036. end;
  1037. end;{case}
  1038. case op of
  1039. OP_ADD:
  1040. begin
  1041. if setflags then
  1042. handle_reg_const_reg(list, f_TOpCG2AsmOp_ovf(op, size), src, a, dst)
  1043. else
  1044. handle_reg_const_reg(list, f_TOpCG2AsmOp(op, size), src, a, dst);
  1045. end;
  1046. OP_SUB:
  1047. begin
  1048. if setflags then
  1049. handle_reg_const_reg(list, f_TOpCG2AsmOp_ovf(op, size), src, a, dst)
  1050. else
  1051. handle_reg_const_reg(list, f_TOpCG2AsmOp(op, size), src, a, dst);
  1052. end;
  1053. OP_MUL:
  1054. begin
  1055. if setflags then
  1056. handle_reg_const_reg(list, f_TOpCG2AsmOp_ovf(op, size), src, a, dst)
  1057. else
  1058. begin
  1059. tmpreg1 := GetIntRegister(list, OS_INT);
  1060. a_load_const_reg(list, OS_INT, a, tmpreg1);
  1061. list.concat(taicpu.op_reg_reg(f_TOpCG2AsmOp(op, size),src, tmpreg1));
  1062. list.concat(taicpu.op_reg(A_MFLO, dst));
  1063. end;
  1064. end;
  1065. OP_IMUL:
  1066. begin
  1067. if setflags then
  1068. handle_reg_const_reg(list, f_TOpCG2AsmOp_ovf(op, size), src, a, dst)
  1069. else
  1070. begin
  1071. tmpreg1 := GetIntRegister(list, OS_INT);
  1072. a_load_const_reg(list, OS_INT, a, tmpreg1);
  1073. list.concat(taicpu.op_reg_reg(f_TOpCG2AsmOp(op, size),src, tmpreg1));
  1074. list.concat(taicpu.op_reg(A_MFLO, dst));
  1075. end;
  1076. end;
  1077. OP_XOR, OP_OR, OP_AND:
  1078. begin
  1079. handle_reg_const_reg(list, f_TOpCG2AsmOp_ovf(op, size), src, a, dst);
  1080. end;
  1081. else
  1082. internalerror(2007012601);
  1083. end;
  1084. end;
  1085. procedure TCgMPSel.a_op_reg_reg_reg_checkoverflow(list: tasmlist; op: TOpCg; size: tcgsize; src1, src2, dst: tregister; setflags: boolean; var ovloc: tlocation);
  1086. begin
  1087. ovloc.loc := LOC_VOID;
  1088. case op of
  1089. OP_ADD:
  1090. begin
  1091. if setflags then
  1092. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp_ovf(op, size), dst, src2, src1))
  1093. else
  1094. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp(op, size), dst, src2, src1));
  1095. end;
  1096. OP_SUB:
  1097. begin
  1098. if setflags then
  1099. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp_ovf(op, size), dst, src2, src1))
  1100. else
  1101. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp(op, size), dst, src2, src1));
  1102. end;
  1103. OP_MUL:
  1104. begin
  1105. if setflags then
  1106. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp_ovf(op, size), dst, src2, src1))
  1107. else
  1108. begin
  1109. list.concat(taicpu.op_reg_reg(f_TOpCG2AsmOp(op, size), src2, src1));
  1110. list.concat(taicpu.op_reg(A_MFLO, dst));
  1111. end;
  1112. end;
  1113. OP_IMUL:
  1114. begin
  1115. if setflags then
  1116. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp_ovf(op, size), dst, src2, src1))
  1117. else
  1118. begin
  1119. list.concat(taicpu.op_reg_reg(f_TOpCG2AsmOp(op, size), src2, src1));
  1120. list.concat(taicpu.op_reg(A_MFLO, dst));
  1121. end;
  1122. end;
  1123. OP_XOR, OP_OR, OP_AND:
  1124. begin
  1125. list.concat(taicpu.op_reg_reg_reg(f_TOpCG2AsmOp_ovf(op, size), dst, src2, src1));
  1126. end;
  1127. else
  1128. internalerror(2007012602);
  1129. end;
  1130. end;
  1131. {*************** compare instructructions ****************}
  1132. procedure TCgMPSel.a_cmp_const_reg_label(list: tasmlist; size: tcgsize; cmp_op: topcmp; a: aint; reg: tregister; l: tasmlabel);
  1133. var
  1134. tmpreg: tregister;
  1135. begin
  1136. if a = 0 then
  1137. tmpreg := NR_R0
  1138. else
  1139. begin
  1140. tmpreg := GetIntRegister(list, OS_INT);
  1141. list.concat(taicpu.op_reg_const(A_LI, tmpreg, a));
  1142. end;
  1143. case cmp_op of
  1144. OC_EQ: { equality comparison }
  1145. list.concat(taicpu.op_reg_reg_sym(A_BEQ, reg, tmpreg, l));
  1146. OC_GT: { greater than (signed) }
  1147. list.concat(taicpu.op_reg_reg_sym(A_BGT, reg, tmpreg, l));
  1148. OC_LT: { less than (signed) }
  1149. list.concat(taicpu.op_reg_reg_sym(A_BLT, reg, tmpreg, l));
  1150. OC_GTE: { greater or equal than (signed) }
  1151. list.concat(taicpu.op_reg_reg_sym(A_BGE, reg, tmpreg, l));
  1152. OC_LTE: { less or equal than (signed) }
  1153. list.concat(taicpu.op_reg_reg_sym(A_BLE, reg, tmpreg, l));
  1154. OC_NE: { not equal }
  1155. list.concat(taicpu.op_reg_reg_sym(A_BNE, reg, tmpreg, l));
  1156. OC_BE: { less or equal than (unsigned) }
  1157. list.concat(taicpu.op_reg_reg_sym(A_BLEU, reg, tmpreg, l));
  1158. OC_B: { less than (unsigned) }
  1159. list.concat(taicpu.op_reg_reg_sym(A_BLTU, reg, tmpreg, l));
  1160. OC_AE: { greater or equal than (unsigned) }
  1161. list.concat(taicpu.op_reg_reg_sym(A_BGEU, reg, tmpreg, l));
  1162. OC_A: { greater than (unsigned) }
  1163. list.concat(taicpu.op_reg_reg_sym(A_BGTU, reg, tmpreg, l));
  1164. else
  1165. internalerror(200701071);
  1166. end;{ case }
  1167. list.Concat(TAiCpu.Op_none(A_NOP));
  1168. end;
  1169. procedure TCgMPSel.a_cmp_reg_reg_label(list: tasmlist; size: tcgsize; cmp_op: topcmp; reg1, reg2: tregister; l: tasmlabel);
  1170. begin
  1171. case cmp_op of
  1172. OC_EQ: { equality comparison }
  1173. list.concat(taicpu.op_reg_reg_sym(A_BEQ, reg2, reg1, l));
  1174. OC_GT: { greater than (signed) }
  1175. list.concat(taicpu.op_reg_reg_sym(A_BGT, reg2, reg1, l));
  1176. OC_LT: { less than (signed) }
  1177. list.concat(taicpu.op_reg_reg_sym(A_BLT, reg2, reg1, l));
  1178. OC_GTE: { greater or equal than (signed) }
  1179. list.concat(taicpu.op_reg_reg_sym(A_BGE, reg2, reg1, l));
  1180. OC_LTE: { less or equal than (signed) }
  1181. list.concat(taicpu.op_reg_reg_sym(A_BLE, reg2, reg1, l));
  1182. OC_NE: { not equal }
  1183. list.concat(taicpu.op_reg_reg_sym(A_BNE, reg2, reg1, l));
  1184. OC_BE: { less or equal than (unsigned) }
  1185. list.concat(taicpu.op_reg_reg_sym(A_BLEU, reg2, reg1, l));
  1186. OC_B: { less than (unsigned) }
  1187. list.concat(taicpu.op_reg_reg_sym(A_BLTU, reg2, reg1, l));
  1188. OC_AE: { greater or equal than (unsigned) }
  1189. list.concat(taicpu.op_reg_reg_sym(A_BGEU, reg2, reg1, l));
  1190. OC_A: { greater than (unsigned) }
  1191. list.concat(taicpu.op_reg_reg_sym(A_BGTU, reg2, reg1, l));
  1192. else
  1193. internalerror(200701072);
  1194. end;{ case }
  1195. list.Concat(TAiCpu.Op_none(A_NOP));
  1196. end;
  1197. procedure TCgMPSel.a_jmp_always(List: tasmlist; l: TAsmLabel);
  1198. begin
  1199. List.Concat(TAiCpu.op_sym(A_J, objectlibrary.newasmsymbol(l.Name, AB_EXTERNAL, AT_FUNCTION)));
  1200. { Delay slot }
  1201. list.Concat(TAiCpu.Op_none(A_NOP));
  1202. end;
  1203. procedure TCgMPSel.a_jmp_name(list: tasmlist; const s: string);
  1204. begin
  1205. List.Concat(TAiCpu.op_sym(A_J, objectlibrary.newasmsymbol(s, AB_EXTERNAL, AT_FUNCTION)));
  1206. { Delay slot }
  1207. list.Concat(TAiCpu.Op_none(A_NOP));
  1208. end;
  1209. procedure TCgMPSel.a_jmp_cond(list: tasmlist; cond: TOpCmp; l: TAsmLabel);
  1210. begin
  1211. internalerror(200701181);
  1212. end;
  1213. procedure TCgMPSel.g_overflowCheck(List: tasmlist; const Loc: TLocation; def: TDef);
  1214. begin
  1215. // this is an empty procedure
  1216. end;
  1217. procedure TCgMPSel.g_overflowCheck_loc(List: tasmlist; const Loc: TLocation; def: TDef; ovloc: tlocation);
  1218. begin
  1219. // this is an empty procedure
  1220. end;
  1221. { *********** entry/exit code and address loading ************ }
  1222. procedure TCgMPSel.g_proc_entry(list: tasmlist; localsize: longint; nostackframe: boolean);
  1223. var
  1224. regcounter, firstregfpu, firstreggpr: TSuperRegister;
  1225. href: treference;
  1226. usesfpr, usesgpr, gotgot: boolean;
  1227. regcounter2, firstfpureg: Tsuperregister;
  1228. cond: tasmcond;
  1229. instr: taicpu;
  1230. begin
  1231. if STK2_dummy <> 0 then
  1232. begin
  1233. list.concat(Taicpu.Op_reg_reg_const(A_P_STK2, STK2_PTR, STK2_PTR, -STK2_dummy));
  1234. end;
  1235. if nostackframe then
  1236. exit;
  1237. usesfpr := False;
  1238. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1239. case target_info.abi of
  1240. abi_powerpc_aix:
  1241. firstfpureg := RS_F14;
  1242. abi_powerpc_sysv:
  1243. firstfpureg := RS_F14;
  1244. abi_default:
  1245. firstfpureg := RS_F14;
  1246. else
  1247. internalerror(2003122903);
  1248. end;
  1249. for regcounter := firstfpureg to RS_F31 do
  1250. begin
  1251. if regcounter in rg[R_FPUREGISTER].used_in_proc then
  1252. begin
  1253. usesfpr := True;
  1254. firstregfpu := regcounter;
  1255. break;
  1256. end;
  1257. end;
  1258. usesgpr := False;
  1259. if not (po_assembler in current_procinfo.procdef.procoptions) then
  1260. for regcounter2 := RS_R13 to RS_R31 do
  1261. begin
  1262. if regcounter2 in rg[R_INTREGISTER].used_in_proc then
  1263. begin
  1264. usesgpr := True;
  1265. firstreggpr := regcounter2;
  1266. break;
  1267. end;
  1268. end;
  1269. LocalSize := align(LocalSize, 8);
  1270. cgcpu_calc_stackframe_size := LocalSize;
  1271. list.concat(Taicpu.Op_reg_reg_const(A_P_FRAME, NR_FRAME_POINTER_REG, NR_R31, LocalSize));
  1272. list.concat(Taicpu.op_none(A_P_SET_NOREORDER));
  1273. list.concat(Taicpu.op_none(A_P_SET_NOMACRO));
  1274. list.concat(Taicpu.Op_reg_reg_const(A_P_SW, NR_FRAME_POINTER_REG, NR_STACK_POINTER_REG, -LocalSize));
  1275. list.concat(Taicpu.Op_reg_reg_const(A_P_SW, NR_R31, NR_STACK_POINTER_REG, -LocalSize + 4));
  1276. list.concat(Taicpu.op_reg_reg(A_MOVE, NR_FRAME_POINTER_REG, NR_STACK_POINTER_REG));
  1277. list.concat(Taicpu.Op_reg_reg_const(A_ADDIU, NR_STACK_POINTER_REG, NR_STACK_POINTER_REG, -LocalSize));
  1278. if (cs_create_pic in current_settings.moduleswitches) and
  1279. (pi_needs_got in current_procinfo.flags) then
  1280. begin
  1281. current_procinfo.got := NR_GP;
  1282. end;
  1283. end;
  1284. procedure TCgMPSel.g_proc_exit(list: tasmlist; parasize: longint; nostackframe: boolean);
  1285. var
  1286. hr: treference;
  1287. localsize: aint;
  1288. begin
  1289. localsize := cgcpu_calc_stackframe_size;
  1290. if paramanager.ret_in_param(current_procinfo.procdef.rettype.def, current_procinfo.procdef.proccalloption) then
  1291. begin
  1292. reference_reset(hr);
  1293. hr.offset := 12;
  1294. hr.refaddr := addr_full;
  1295. if nostackframe then
  1296. begin
  1297. if STK2_dummy <> 0 then
  1298. list.concat(Taicpu.Op_reg_reg_const(A_P_STK2, STK2_PTR, STK2_PTR, STK2_dummy));
  1299. list.concat(taicpu.op_reg(A_J, NR_R31));
  1300. list.concat(Taicpu.op_none(A_NOP));
  1301. end
  1302. else
  1303. begin
  1304. list.concat(Taicpu.Op_reg_reg_const(A_P_LW, NR_FRAME_POINTER_REG, NR_STACK_POINTER_REG, 0));
  1305. list.concat(Taicpu.Op_reg_reg_const(A_P_LW, NR_R31, NR_STACK_POINTER_REG, 4));
  1306. list.concat(Taicpu.Op_reg_reg_const(A_ADDIU, NR_STACK_POINTER_REG, NR_STACK_POINTER_REG, localsize));
  1307. if STK2_dummy <> 0 then
  1308. list.concat(Taicpu.Op_reg_reg_const(A_P_STK2, STK2_PTR, STK2_PTR, STK2_dummy));
  1309. list.concat(taicpu.op_reg(A_J, NR_R31));
  1310. list.concat(Taicpu.op_none(A_NOP));
  1311. list.concat(Taicpu.op_none(A_P_SET_MACRO));
  1312. list.concat(Taicpu.op_none(A_P_SET_REORDER));
  1313. end;
  1314. end
  1315. else
  1316. begin
  1317. if nostackframe then
  1318. begin
  1319. if STK2_dummy <> 0 then
  1320. list.concat(Taicpu.Op_reg_reg_const(A_P_STK2, STK2_PTR, STK2_PTR, STK2_dummy));
  1321. list.concat(taicpu.op_reg(A_J, NR_R31));
  1322. list.concat(Taicpu.op_none(A_NOP));
  1323. list.concat(Taicpu.op_none(A_P_SET_MACRO));
  1324. list.concat(Taicpu.op_none(A_P_SET_REORDER));
  1325. end
  1326. else
  1327. begin
  1328. list.concat(Taicpu.Op_reg_reg_const(A_P_LW, NR_FRAME_POINTER_REG, NR_STACK_POINTER_REG, 0));
  1329. list.concat(Taicpu.Op_reg_reg_const(A_P_LW, NR_R31, NR_STACK_POINTER_REG, 4));
  1330. list.concat(Taicpu.Op_reg_reg_const(A_ADDIU, NR_STACK_POINTER_REG, NR_STACK_POINTER_REG, localsize));
  1331. if STK2_dummy <> 0 then
  1332. list.concat(Taicpu.Op_reg_reg_const(A_P_STK2, STK2_PTR, STK2_PTR, STK2_dummy));
  1333. list.concat(taicpu.op_reg(A_J, NR_R31));
  1334. list.concat(Taicpu.op_none(A_NOP));
  1335. list.concat(Taicpu.op_none(A_P_SET_MACRO));
  1336. list.concat(Taicpu.op_none(A_P_SET_REORDER));
  1337. end;
  1338. end;
  1339. end;
  1340. { ************* concatcopy ************ }
  1341. procedure TCgMPSel.g_concatcopy_move(list: tasmlist; const Source, dest: treference; len: aint);
  1342. var
  1343. paraloc1, paraloc2, paraloc3: TCGPara;
  1344. begin
  1345. paraloc1.init;
  1346. paraloc2.init;
  1347. paraloc3.init;
  1348. paramanager.getintparaloc(pocall_default, 1, paraloc1);
  1349. paramanager.getintparaloc(pocall_default, 2, paraloc2);
  1350. paramanager.getintparaloc(pocall_default, 3, paraloc3);
  1351. paramanager.allocparaloc(list, paraloc3);
  1352. a_param_const(list, OS_INT, len, paraloc3);
  1353. paramanager.allocparaloc(list, paraloc2);
  1354. a_paramaddr_ref(list, dest, paraloc2);
  1355. paramanager.allocparaloc(list, paraloc2);
  1356. a_paramaddr_ref(list, Source, paraloc1);
  1357. paramanager.freeparaloc(list, paraloc3);
  1358. paramanager.freeparaloc(list, paraloc2);
  1359. paramanager.freeparaloc(list, paraloc1);
  1360. alloccpuregisters(list, R_INTREGISTER, paramanager.get_volatile_registers_int(pocall_default));
  1361. alloccpuregisters(list, R_FPUREGISTER, paramanager.get_volatile_registers_fpu(pocall_default));
  1362. a_call_name(list, 'FPC_MOVE');
  1363. dealloccpuregisters(list, R_FPUREGISTER, paramanager.get_volatile_registers_fpu(pocall_default));
  1364. dealloccpuregisters(list, R_INTREGISTER, paramanager.get_volatile_registers_int(pocall_default));
  1365. paraloc3.done;
  1366. paraloc2.done;
  1367. paraloc1.done;
  1368. end;
  1369. procedure TCgMPSel.g_concatcopy(list: tasmlist; const Source, dest: treference; len: aint);
  1370. var
  1371. tmpreg1, hreg, countreg: TRegister;
  1372. src, dst: TReference;
  1373. lab: tasmlabel;
  1374. Count, count2: aint;
  1375. begin
  1376. if len > high(longint) then
  1377. internalerror(2002072704);
  1378. { anybody wants to determine a good value here :)? }
  1379. if len > 100 then
  1380. g_concatcopy_move(list, Source, dest, len)
  1381. else
  1382. begin
  1383. reference_reset(src);
  1384. reference_reset(dst);
  1385. { load the address of source into src.base }
  1386. src.base := GetAddressRegister(list);
  1387. a_loadaddr_ref_reg(list, Source, src.base);
  1388. { load the address of dest into dst.base }
  1389. dst.base := GetAddressRegister(list);
  1390. a_loadaddr_ref_reg(list, dest, dst.base);
  1391. { generate a loop }
  1392. Count := len div 4;
  1393. if Count > 4 then
  1394. begin
  1395. { the offsets are zero after the a_loadaddress_ref_reg and just }
  1396. { have to be set to 8. I put an Inc there so debugging may be }
  1397. { easier (should offset be different from zero here, it will be }
  1398. { easy to notice in the generated assembler }
  1399. countreg := GetIntRegister(list, OS_INT);
  1400. tmpreg1 := GetIntRegister(list, OS_INT);
  1401. a_load_const_reg(list, OS_INT, Count, countreg);
  1402. { explicitely allocate R_O0 since it can be used safely here }
  1403. { (for holding date that's being copied) }
  1404. objectlibrary.getlabel(lab);
  1405. a_label(list, lab);
  1406. list.concat(taicpu.op_reg_ref(A_LW, tmpreg1, src));
  1407. list.concat(taicpu.op_reg_ref(A_SW, tmpreg1, dst));
  1408. list.concat(taicpu.op_reg_reg_const(A_ADDIU, src.base, src.base, 4));
  1409. list.concat(taicpu.op_reg_reg_const(A_ADDIU, dst.base, dst.base, 4));
  1410. list.concat(taicpu.op_reg_reg_const(A_ADDIU, countreg, countreg, -1));
  1411. list.concat(taicpu.op_reg_sym(A_BGTZ, countreg, lab));
  1412. list.concat(taicpu.op_none(A_NOP));
  1413. len := len mod 4;
  1414. end;
  1415. { unrolled loop }
  1416. Count := len div 4;
  1417. if Count > 0 then
  1418. begin
  1419. tmpreg1 := GetIntRegister(list, OS_INT);
  1420. for count2 := 1 to Count do
  1421. begin
  1422. list.concat(taicpu.op_reg_ref(A_LW, tmpreg1, src));
  1423. list.concat(taicpu.op_reg_ref(A_SW, tmpreg1, dst));
  1424. Inc(src.offset, 4);
  1425. Inc(dst.offset, 4);
  1426. end;
  1427. len := len mod 4;
  1428. end;
  1429. if (len and 4) <> 0 then
  1430. begin
  1431. hreg := GetIntRegister(list, OS_INT);
  1432. a_load_ref_reg(list, OS_32, OS_32, src, hreg);
  1433. a_load_reg_ref(list, OS_32, OS_32, hreg, dst);
  1434. Inc(src.offset, 4);
  1435. Inc(dst.offset, 4);
  1436. end;
  1437. { copy the leftovers }
  1438. if (len and 2) <> 0 then
  1439. begin
  1440. hreg := GetIntRegister(list, OS_INT);
  1441. a_load_ref_reg(list, OS_16, OS_16, src, hreg);
  1442. a_load_reg_ref(list, OS_16, OS_16, hreg, dst);
  1443. Inc(src.offset, 2);
  1444. Inc(dst.offset, 2);
  1445. end;
  1446. if (len and 1) <> 0 then
  1447. begin
  1448. hreg := GetIntRegister(list, OS_INT);
  1449. a_load_ref_reg(list, OS_8, OS_8, src, hreg);
  1450. a_load_reg_ref(list, OS_8, OS_8, hreg, dst);
  1451. end;
  1452. end;
  1453. end;
  1454. procedure TCgMPSel.g_concatcopy_unaligned(list: tasmlist; const Source, dest: treference; len: aint);
  1455. var
  1456. src, dst: TReference;
  1457. tmpreg1, countreg: TRegister;
  1458. i: aint;
  1459. lab: tasmlabel;
  1460. begin
  1461. if len > 31 then
  1462. g_concatcopy_move(list, Source, dest, len)
  1463. else
  1464. begin
  1465. reference_reset(src);
  1466. reference_reset(dst);
  1467. { load the address of source into src.base }
  1468. src.base := GetAddressRegister(list);
  1469. a_loadaddr_ref_reg(list, Source, src.base);
  1470. { load the address of dest into dst.base }
  1471. dst.base := GetAddressRegister(list);
  1472. a_loadaddr_ref_reg(list, dest, dst.base);
  1473. { generate a loop }
  1474. if len > 4 then
  1475. begin
  1476. { the offsets are zero after the a_loadaddress_ref_reg and just }
  1477. { have to be set to 8. I put an Inc there so debugging may be }
  1478. { easier (should offset be different from zero here, it will be }
  1479. { easy to notice in the generated assembler }
  1480. countreg := GetIntRegister(list, OS_INT);
  1481. tmpreg1 := GetIntRegister(list, OS_INT);
  1482. a_load_const_reg(list, OS_INT, len, countreg);
  1483. { explicitely allocate R_O0 since it can be used safely here }
  1484. { (for holding date that's being copied) }
  1485. objectlibrary.getlabel(lab);
  1486. a_label(list, lab);
  1487. list.concat(taicpu.op_reg_ref(A_LBU, tmpreg1, src));
  1488. list.concat(taicpu.op_reg_ref(A_SB, tmpreg1, dst));
  1489. list.concat(taicpu.op_reg_reg_const(A_ADDIU, src.base, src.base, 1));
  1490. list.concat(taicpu.op_reg_reg_const(A_ADDIU, dst.base, dst.base, 1));
  1491. list.concat(taicpu.op_reg_reg_const(A_ADDIU, countreg, countreg, -1));
  1492. list.concat(taicpu.op_reg_sym(A_BGTZ, countreg, lab));
  1493. list.concat(taicpu.op_none(A_NOP));
  1494. end
  1495. else
  1496. begin
  1497. { unrolled loop }
  1498. tmpreg1 := GetIntRegister(list, OS_INT);
  1499. for i := 1 to len do
  1500. begin
  1501. list.concat(taicpu.op_reg_ref(A_LBU, tmpreg1, src));
  1502. list.concat(taicpu.op_reg_ref(A_SB, tmpreg1, dst));
  1503. Inc(src.offset);
  1504. Inc(dst.offset);
  1505. end;
  1506. end;
  1507. end;
  1508. end;
  1509. procedure TCgMPSel.g_intf_wrapper(list: tasmlist; procdef: tprocdef; const labelname: string; ioffset: longint);
  1510. procedure loadvmttor24;
  1511. var
  1512. href: treference;
  1513. begin
  1514. reference_reset_base(href, NR_R2, 0); { return value }
  1515. cg.a_load_ref_reg(list, OS_ADDR, OS_ADDR, href, NR_R24);
  1516. end;
  1517. procedure op_onr24methodaddr;
  1518. var
  1519. href : treference;
  1520. begin
  1521. if (procdef.extnumber=$ffff) then
  1522. Internalerror(200006139);
  1523. { call/jmp vmtoffs(%eax) ; method offs }
  1524. reference_reset_base(href, NR_R24, procdef._class.vmtmethodoffset(procdef.extnumber));
  1525. cg.a_load_ref_reg(list, OS_ADDR, OS_ADDR, href, NR_R24);
  1526. list.concat(taicpu.op_reg(A_JR, NR_R24));
  1527. end;
  1528. var
  1529. make_global: boolean;
  1530. href: treference;
  1531. begin
  1532. if procdef.proctypeoption <> potype_none then
  1533. Internalerror(200006137);
  1534. if not assigned(procdef._class) or
  1535. (procdef.procoptions * [po_classmethod, po_staticmethod,
  1536. po_methodpointer, po_interrupt, po_iocheck] <> []) then
  1537. Internalerror(200006138);
  1538. if procdef.owner.symtabletype <> objectsymtable then
  1539. Internalerror(200109191);
  1540. make_global := False;
  1541. if (not current_module.is_unit) or
  1542. (procdef.owner.defowner.owner.symtabletype = globalsymtable) then
  1543. make_global := True;
  1544. if make_global then
  1545. List.concat(Tai_symbol.Createname_global(labelname, AT_FUNCTION, 0))
  1546. else
  1547. List.concat(Tai_symbol.Createname(labelname, AT_FUNCTION, 0));
  1548. { set param1 interface to self }
  1549. g_adjust_self_value(list, procdef, ioffset);
  1550. if po_virtualmethod in procdef.procoptions then
  1551. begin
  1552. loadvmttor24;
  1553. op_onr24methodaddr;
  1554. end
  1555. else
  1556. list.concat(taicpu.op_sym(A_B, objectlibrary.newasmsymbol(procdef.mangledname, AB_EXTERNAL, AT_FUNCTION)));
  1557. { Delay slot }
  1558. list.Concat(TAiCpu.Op_none(A_NOP));
  1559. List.concat(Tai_symbol_end.Createname(labelname));
  1560. end;
  1561. {****************************************************************************
  1562. TCG64_MIPSel
  1563. ****************************************************************************}
  1564. procedure TCg64MPSel.a_load64_reg_ref(list: tasmlist; reg: tregister64; const ref: treference);
  1565. var
  1566. tmpref: treference;
  1567. begin
  1568. { Override this function to prevent loading the reference twice }
  1569. tmpref := ref;
  1570. cg.a_load_reg_ref(list, OS_S32, OS_S32, reg.reglo, tmpref);
  1571. Inc(tmpref.offset, 4);
  1572. cg.a_load_reg_ref(list, OS_S32, OS_S32, reg.reghi, tmpref);
  1573. end;
  1574. procedure TCg64MPSel.a_load64_ref_reg(list: tasmlist; const ref: treference; reg: tregister64);
  1575. var
  1576. tmpref: treference;
  1577. begin
  1578. { Override this function to prevent loading the reference twice }
  1579. tmpref := ref;
  1580. cg.a_load_ref_reg(list, OS_S32, OS_S32, tmpref, reg.reglo);
  1581. Inc(tmpref.offset, 4);
  1582. cg.a_load_ref_reg(list, OS_S32, OS_S32, tmpref, reg.reghi);
  1583. end;
  1584. procedure TCg64MPSel.a_param64_ref(list: tasmlist; const r: treference; const paraloc: tcgpara);
  1585. var
  1586. hreg64: tregister64;
  1587. begin
  1588. { Override this function to prevent loading the reference twice.
  1589. Use here some extra registers, but those are optimized away by the RA }
  1590. hreg64.reglo := cg.GetIntRegister(list, OS_S32);
  1591. hreg64.reghi := cg.GetIntRegister(list, OS_S32);
  1592. a_load64_ref_reg(list, r, hreg64);
  1593. a_param64_reg(list, hreg64, paraloc);
  1594. end;
  1595. procedure TCg64MPSel.a_op64_reg_reg(list: tasmlist; op: TOpCG; size: tcgsize; regsrc, regdst: TRegister64);
  1596. var
  1597. op1, op2, op_call64: TAsmOp;
  1598. tmpreg1, tmpreg2: TRegister;
  1599. begin
  1600. tmpreg1 := NR_TCR12; //GetIntRegister(list, OS_INT);
  1601. tmpreg2 := NR_TCR13; //GetIntRegister(list, OS_INT);
  1602. case op of
  1603. OP_ADD:
  1604. begin
  1605. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg1, regsrc.reglo, regdst.reglo));
  1606. list.concat(taicpu.op_reg_reg_reg(A_SLTU, NR_TCR10, tmpreg1, regsrc.reglo));
  1607. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg2, regsrc.reghi, regdst.reghi));
  1608. list.concat(taicpu.op_reg_reg_reg(A_ADDU, NR_TCR10, NR_TCR10, tmpreg2));
  1609. list.concat(Taicpu.Op_reg_reg(A_MOVE, regdst.reglo, tmpreg1));
  1610. list.concat(Taicpu.Op_reg_reg(A_MOVE, regdst.reghi, NR_TCR10));
  1611. exit;
  1612. end;
  1613. OP_AND:
  1614. begin
  1615. list.concat(taicpu.op_reg_reg_reg(A_AND, regdst.reglo, regsrc.reglo, regdst.reglo));
  1616. list.concat(taicpu.op_reg_reg_reg(A_AND, regdst.reghi, regsrc.reghi, regdst.reghi));
  1617. exit;
  1618. end;
  1619. OP_NEG:
  1620. begin
  1621. list.concat(taicpu.op_reg_reg_reg(A_SUBU, regdst.reglo, NR_R0, regsrc.reglo));
  1622. list.concat(taicpu.op_reg_reg_reg(A_SLTU, NR_TCR10, NR_R0, regdst.reglo));
  1623. list.concat(taicpu.op_reg_reg_reg(A_SUBU, regdst.reghi, NR_R0, regsrc.reghi));
  1624. list.concat(taicpu.op_reg_reg_reg(A_SUBU, NR_TCR10, regdst.reghi, NR_TCR10));
  1625. list.concat(Taicpu.Op_reg_reg(A_MOVE, regdst.reghi, NR_TCR10));
  1626. exit;
  1627. end;
  1628. OP_NOT:
  1629. begin
  1630. list.concat(taicpu.op_reg_reg_reg(A_NOR, regdst.reglo, NR_R0, regsrc.reglo));
  1631. list.concat(taicpu.op_reg_reg_reg(A_NOR, regdst.reghi, NR_R0, regsrc.reghi));
  1632. exit;
  1633. end;
  1634. OP_OR:
  1635. begin
  1636. list.concat(taicpu.op_reg_reg_reg(A_OR, regdst.reglo, regsrc.reglo, regdst.reglo));
  1637. list.concat(taicpu.op_reg_reg_reg(A_OR, regdst.reghi, regsrc.reghi, regdst.reghi));
  1638. exit;
  1639. end;
  1640. OP_SUB:
  1641. begin
  1642. list.concat(taicpu.op_reg_reg_reg(A_SUBU, tmpreg1, regdst.reglo, regsrc.reglo));
  1643. list.concat(taicpu.op_reg_reg_reg(A_SLTU, NR_TCR10, regdst.reglo, tmpreg1));
  1644. list.concat(taicpu.op_reg_reg_reg(A_SUBU, tmpreg2, regdst.reghi, regsrc.reghi));
  1645. list.concat(taicpu.op_reg_reg_reg(A_SUBU, tmpreg2, tmpreg2, NR_TCR10));
  1646. list.concat(Taicpu.Op_reg_reg(A_MOVE, regdst.reglo, tmpreg1));
  1647. list.concat(Taicpu.Op_reg_reg(A_MOVE, regdst.reghi, tmpreg2));
  1648. exit;
  1649. end;
  1650. OP_XOR:
  1651. begin
  1652. list.concat(taicpu.op_reg_reg_reg(A_XOR, regdst.reglo, regdst.reglo, regsrc.reglo));
  1653. list.concat(taicpu.op_reg_reg_reg(A_XOR, regdst.reghi, regsrc.reghi, regdst.reghi));
  1654. exit;
  1655. end;
  1656. else
  1657. internalerror(200306017);
  1658. end; {case}
  1659. end;
  1660. procedure TCg64MPSel.a_op64_const_reg(list: tasmlist; op: TOpCG; size: tcgsize; Value: int64; regdst: TRegister64);
  1661. var
  1662. op1, op2: TAsmOp;
  1663. begin
  1664. case op of
  1665. OP_NEG,
  1666. OP_NOT:
  1667. internalerror(200306017);
  1668. end;
  1669. a_op64_const_reg_reg(list, op, size, value, regdst, regdst);
  1670. end;
  1671. procedure TCg64MPSel.a_op64_const_reg_reg(list: tasmlist; op: TOpCG; size: tcgsize; Value: int64; regsrc, regdst: tregister64);
  1672. var
  1673. l: tlocation;
  1674. begin
  1675. a_op64_const_reg_reg_checkoverflow(list, op, size, Value, regsrc, regdst, False, l);
  1676. end;
  1677. procedure TCg64MPSel.a_op64_reg_reg_reg(list: tasmlist; op: TOpCG; size: tcgsize; regsrc1, regsrc2, regdst: tregister64);
  1678. var
  1679. l: tlocation;
  1680. begin
  1681. a_op64_reg_reg_reg_checkoverflow(list, op, size, regsrc1, regsrc2, regdst, False, l);
  1682. end;
  1683. procedure TCg64MPSel.a_op64_const_reg_reg_checkoverflow(list: tasmlist; op: TOpCG; size: tcgsize; Value: int64; regsrc, regdst: tregister64; setflags: boolean; var ovloc: tlocation);
  1684. var
  1685. op1, op2: TAsmOp;
  1686. tmpreg1: TRegister;
  1687. begin
  1688. tmpreg1 := NR_TCR12;
  1689. case op of
  1690. OP_NEG,
  1691. OP_NOT:
  1692. internalerror(200306017);
  1693. end;
  1694. list.concat(taicpu.op_reg_const(A_LI, NR_TCR10, aint(hi(Value))));
  1695. list.concat(taicpu.op_reg_const(A_LI, NR_TCR11, aint(lo(Value))));
  1696. case op of
  1697. OP_ADD:
  1698. begin
  1699. list.concat(taicpu.op_reg_reg_reg(A_ADDU, regdst.reglo, regsrc.reglo, NR_TCR10));
  1700. list.concat(taicpu.op_reg_reg_reg(A_SLTU, tmpreg1, regdst.reglo, regsrc.reglo));
  1701. list.concat(taicpu.op_reg_reg_reg(A_ADDU, regdst.reghi, regsrc.reghi, NR_TCR11));
  1702. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg1, tmpreg1, regdst.reghi));
  1703. list.concat(Taicpu.Op_reg_reg(A_MOVE, regdst.reghi, tmpreg1));
  1704. exit;
  1705. end;
  1706. OP_AND:
  1707. begin
  1708. list.concat(taicpu.op_reg_reg_reg(A_AND, regdst.reglo, regsrc.reglo, NR_TCR10));
  1709. list.concat(taicpu.op_reg_reg_reg(A_AND, regdst.reghi, regsrc.reghi, NR_TCR11));
  1710. exit;
  1711. end;
  1712. OP_OR:
  1713. begin
  1714. list.concat(taicpu.op_reg_reg_reg(A_OR, regdst.reglo, regsrc.reglo, NR_TCR10));
  1715. list.concat(taicpu.op_reg_reg_reg(A_OR, regdst.reghi, regsrc.reghi, NR_TCR11));
  1716. exit;
  1717. end;
  1718. OP_SUB:
  1719. begin
  1720. list.concat(taicpu.op_reg_reg_reg(A_SUBU, regdst.reglo, regsrc.reglo, NR_TCR10));
  1721. list.concat(taicpu.op_reg_reg_reg(A_SLTU, tmpreg1, regsrc.reglo, regdst.reglo));
  1722. list.concat(taicpu.op_reg_reg_reg(A_SUBU, regdst.reghi, regsrc.reghi, NR_TCR11));
  1723. list.concat(taicpu.op_reg_reg_reg(A_SUBU, tmpreg1, regdst.reghi, tmpreg1));
  1724. list.concat(Taicpu.Op_reg_reg(A_MOVE, regdst.reghi, tmpreg1));
  1725. exit;
  1726. end;
  1727. OP_XOR:
  1728. begin
  1729. list.concat(taicpu.op_reg_reg_reg(A_XOR, regdst.reglo, regsrc.reglo, NR_TCR10));
  1730. list.concat(taicpu.op_reg_reg_reg(A_XOR, regdst.reghi, regsrc.reghi, NR_TCR11));
  1731. exit;
  1732. end;
  1733. else
  1734. internalerror(200306017);
  1735. end;
  1736. end;
  1737. procedure TCg64MPSel.a_op64_reg_reg_reg_checkoverflow(list: tasmlist; op: TOpCG; size: tcgsize; regsrc1, regsrc2, regdst: tregister64; setflags: boolean; var ovloc: tlocation);
  1738. var
  1739. op1, op2: TAsmOp;
  1740. tmpreg1, tmpreg2: TRegister;
  1741. begin
  1742. tmpreg1 := NR_TCR12;
  1743. tmpreg2 := NR_TCR13;
  1744. case op of
  1745. OP_NEG,
  1746. OP_NOT:
  1747. internalerror(200306017);
  1748. end;
  1749. case op of
  1750. OP_ADD:
  1751. begin
  1752. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg1, regsrc2.reglo, regsrc1.reglo));
  1753. list.concat(taicpu.op_reg_reg_reg(A_SLTU, NR_TCR10, tmpreg1, regsrc2.reglo));
  1754. list.concat(taicpu.op_reg_reg_reg(A_ADDU, tmpreg2, regsrc2.reghi, regsrc1.reghi));
  1755. list.concat(taicpu.op_reg_reg_reg(A_ADDU, regdst.reghi, NR_TCR10, tmpreg2));
  1756. list.concat(Taicpu.Op_reg_reg(A_MOVE, regdst.reglo, tmpreg1));
  1757. exit;
  1758. end;
  1759. OP_AND:
  1760. begin
  1761. list.concat(taicpu.op_reg_reg_reg(A_AND, regdst.reglo, regsrc2.reglo, regsrc1.reglo));
  1762. list.concat(taicpu.op_reg_reg_reg(A_AND, regdst.reghi, regsrc2.reghi, regsrc1.reghi));
  1763. exit;
  1764. end;
  1765. OP_OR:
  1766. begin
  1767. list.concat(taicpu.op_reg_reg_reg(A_OR, regdst.reglo, regsrc2.reglo, regsrc1.reglo));
  1768. list.concat(taicpu.op_reg_reg_reg(A_OR, regdst.reghi, regsrc2.reghi, regsrc1.reghi));
  1769. exit;
  1770. end;
  1771. OP_SUB:
  1772. begin
  1773. list.concat(taicpu.op_reg_reg_reg(A_SUBU, tmpreg1, regsrc2.reglo, regsrc1.reglo));
  1774. list.concat(taicpu.op_reg_reg_reg(A_SLTU, NR_TCR10, regsrc2.reglo, tmpreg1));
  1775. list.concat(taicpu.op_reg_reg_reg(A_SUBU, tmpreg2, regsrc2.reghi, regsrc1.reghi));
  1776. list.concat(taicpu.op_reg_reg_reg(A_SUBU, regdst.reghi, tmpreg2, NR_TCR10));
  1777. list.concat(Taicpu.Op_reg_reg(A_MOVE, regdst.reglo, tmpreg1));
  1778. exit;
  1779. end;
  1780. OP_XOR:
  1781. begin
  1782. list.concat(taicpu.op_reg_reg_reg(A_XOR, regdst.reglo, regsrc2.reglo, regsrc1.reglo));
  1783. list.concat(taicpu.op_reg_reg_reg(A_XOR, regdst.reghi, regsrc2.reghi, regsrc1.reghi));
  1784. exit;
  1785. end;
  1786. else
  1787. internalerror(200306017);
  1788. end; {case}
  1789. end;
  1790. begin
  1791. cg := TCgMPSel.Create;
  1792. cg64 := TCg64MPSel.Create;
  1793. end.