ncginl.pas 34 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Carl Eric Codere
  3. Generate generic inline nodes
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit ncginl;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. node,ninl;
  22. type
  23. tcginlinenode = class(tinlinenode)
  24. procedure pass_generate_code;override;
  25. procedure second_sizeoftypeof;virtual;
  26. procedure second_length;virtual;
  27. procedure second_predsucc;virtual;
  28. procedure second_incdec;virtual;
  29. procedure second_AndOrXorShiftRot_assign;virtual;
  30. procedure second_NegNot_assign;virtual;
  31. procedure second_typeinfo;virtual;
  32. procedure second_includeexclude;virtual;
  33. procedure second_pi; virtual;
  34. procedure second_arctan_real; virtual;
  35. procedure second_abs_real; virtual;
  36. procedure second_sqr_real; virtual;
  37. procedure second_sqrt_real; virtual;
  38. procedure second_ln_real; virtual;
  39. procedure second_cos_real; virtual;
  40. procedure second_sin_real; virtual;
  41. procedure second_assigned; virtual;
  42. procedure second_get_frame;virtual;
  43. procedure second_get_caller_frame;virtual;
  44. procedure second_get_caller_addr;virtual;
  45. procedure second_prefetch; virtual;
  46. procedure second_round_real; virtual;
  47. procedure second_trunc_real; virtual;
  48. procedure second_int_real; virtual;
  49. procedure second_abs_long; virtual;
  50. procedure second_rox_sar; virtual;
  51. procedure second_bsfbsr; virtual;
  52. procedure second_new; virtual;
  53. procedure second_setlength; virtual; abstract;
  54. procedure second_box; virtual; abstract;
  55. procedure second_popcnt; virtual;
  56. procedure second_seg; virtual; abstract;
  57. procedure second_fma; virtual;
  58. end;
  59. implementation
  60. uses
  61. globtype,constexp,
  62. verbose,globals,compinnr,
  63. symconst,symtype,symdef,defutil,
  64. aasmbase,aasmdata,
  65. cgbase,pass_2,
  66. cpubase,procinfo,
  67. ncon,ncal,
  68. tgobj,ncgutil,
  69. cgutils,cgobj,hlcgobj
  70. {$ifndef cpu64bitalu}
  71. ,cg64f32
  72. {$endif not cpu64bitalu}
  73. ;
  74. {*****************************************************************************
  75. TCGINLINENODE
  76. *****************************************************************************}
  77. procedure tcginlinenode.pass_generate_code;
  78. begin
  79. location_reset(location,LOC_VOID,OS_NO);
  80. case inlinenumber of
  81. in_sizeof_x,
  82. in_typeof_x :
  83. second_SizeofTypeOf;
  84. in_length_x :
  85. second_Length;
  86. in_pred_x,
  87. in_succ_x:
  88. second_PredSucc;
  89. in_dec_x,
  90. in_inc_x :
  91. second_IncDec;
  92. in_typeinfo_x:
  93. second_TypeInfo;
  94. in_include_x_y,
  95. in_exclude_x_y:
  96. second_IncludeExclude;
  97. in_pi_real:
  98. second_pi;
  99. in_sin_real:
  100. second_sin_real;
  101. in_arctan_real:
  102. second_arctan_real;
  103. in_abs_real:
  104. second_abs_real;
  105. in_abs_long:
  106. second_abs_long;
  107. in_round_real:
  108. second_round_real;
  109. in_trunc_real:
  110. second_trunc_real;
  111. in_int_real:
  112. second_int_real;
  113. in_sqr_real:
  114. second_sqr_real;
  115. in_sqrt_real:
  116. second_sqrt_real;
  117. in_ln_real:
  118. second_ln_real;
  119. in_cos_real:
  120. second_cos_real;
  121. in_prefetch_var:
  122. second_prefetch;
  123. in_assigned_x:
  124. second_assigned;
  125. in_get_frame:
  126. second_get_frame;
  127. in_get_caller_frame:
  128. second_get_caller_frame;
  129. in_get_caller_addr:
  130. second_get_caller_addr;
  131. in_unaligned_x:
  132. begin
  133. secondpass(tcallparanode(left).left);
  134. location:=tcallparanode(left).left.location;
  135. if location.loc in [LOC_CREFERENCE,LOC_REFERENCE] then
  136. location.reference.alignment:=1;
  137. end;
  138. in_aligned_x:
  139. begin
  140. secondpass(tcallparanode(left).left);
  141. location:=tcallparanode(left).left.location;
  142. if location.loc in [LOC_CREFERENCE,LOC_REFERENCE] then
  143. location.reference.alignment:=resultdef.alignment;
  144. end;
  145. {$ifdef SUPPORT_MMX}
  146. in_mmx_pcmpeqb..in_mmx_pcmpgtw:
  147. begin
  148. location_reset(location,LOC_MMXREGISTER,OS_NO);
  149. if left.location.loc=LOC_REGISTER then
  150. begin
  151. {!!!!!!!}
  152. end
  153. else if tcallparanode(left).left.location.loc=LOC_REGISTER then
  154. begin
  155. {!!!!!!!}
  156. end
  157. else
  158. begin
  159. {!!!!!!!}
  160. end;
  161. end;
  162. {$endif SUPPORT_MMX}
  163. in_rol_x,
  164. in_rol_x_y,
  165. in_ror_x,
  166. in_ror_x_y,
  167. in_sar_x,
  168. in_sar_x_y:
  169. second_rox_sar;
  170. in_bsf_x,
  171. in_bsr_x:
  172. second_BsfBsr;
  173. in_new_x:
  174. second_new;
  175. in_setlength_x:
  176. second_setlength;
  177. in_box_x:
  178. second_box;
  179. in_popcnt_x:
  180. second_popcnt;
  181. in_seg_x:
  182. second_seg;
  183. in_fma_single,
  184. in_fma_double,
  185. in_fma_extended,
  186. in_fma_float128:
  187. second_fma;
  188. in_and_assign_x_y,
  189. in_or_assign_x_y,
  190. in_xor_assign_x_y,
  191. in_sar_assign_x_y,
  192. in_shl_assign_x_y,
  193. in_shr_assign_x_y,
  194. in_rol_assign_x_y,
  195. in_ror_assign_x_y:
  196. second_AndOrXorShiftRot_assign;
  197. in_neg_assign_x,
  198. in_not_assign_x:
  199. second_NegNot_assign;
  200. else internalerror(9);
  201. end;
  202. end;
  203. {*****************************************************************************
  204. SIZEOF / TYPEOF GENERIC HANDLING
  205. *****************************************************************************}
  206. { second_handle_ the sizeof and typeof routines }
  207. procedure tcginlinenode.second_SizeOfTypeOf;
  208. begin
  209. { handled in pass 1 }
  210. internalerror(2015122701);
  211. end;
  212. {*****************************************************************************
  213. LENGTH GENERIC HANDLING
  214. *****************************************************************************}
  215. procedure tcginlinenode.second_Length;
  216. var
  217. lengthlab : tasmlabel;
  218. hregister : tregister;
  219. lendef : tdef;
  220. href : treference;
  221. begin
  222. secondpass(left);
  223. if is_shortstring(left.resultdef) then
  224. begin
  225. location_copy(location,left.location);
  226. location.size:=OS_8;
  227. end
  228. else
  229. begin
  230. { length in ansi/wide strings and high in dynamic arrays is at offset -sizeof(pint) }
  231. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
  232. current_asmdata.getjumplabel(lengthlab);
  233. hlcg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,left.resultdef,OC_EQ,0,left.location.register,lengthlab);
  234. { the length of a widestring is a 32 bit unsigned int. Since every
  235. character occupies 2 bytes, on a 32 bit platform you can express
  236. the maximum length using 31 bits. On a 64 bit platform, it may be
  237. 32 bits. This means that regardless of the platform, a location
  238. with size OS_SINT/ossinttype can hold the length without
  239. overflowing (this code returns an ossinttype value) }
  240. if is_widestring(left.resultdef) then
  241. lendef:=u32inttype
  242. else
  243. lendef:=ossinttype;
  244. { volatility of the ansistring/widestring refers to the volatility of the
  245. string pointer, not of the string data }
  246. hlcg.reference_reset_base(href,left.resultdef,left.location.register,-lendef.size,lendef.alignment,[]);
  247. { if the string pointer is nil, the length is 0 -> reuse the register
  248. that originally held the string pointer for the length, so that we
  249. can keep the original nil/0 as length in that case }
  250. hregister:=cg.makeregsize(current_asmdata.CurrAsmList,left.location.register,def_cgsize(resultdef));
  251. hlcg.a_load_ref_reg(current_asmdata.CurrAsmList,lendef,resultdef,href,hregister);
  252. if is_widestring(left.resultdef) then
  253. hlcg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,resultdef,1,hregister);
  254. { Dynamic arrays do not have their length attached but their maximum index }
  255. if is_dynamic_array(left.resultdef) then
  256. hlcg.a_op_const_reg(current_asmdata.CurrAsmList,OP_ADD,resultdef,1,hregister);
  257. cg.a_label(current_asmdata.CurrAsmList,lengthlab);
  258. location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
  259. location.register:=hregister;
  260. end;
  261. end;
  262. {*****************************************************************************
  263. PRED/SUCC GENERIC HANDLING
  264. *****************************************************************************}
  265. procedure tcginlinenode.second_PredSucc;
  266. var
  267. cgop : topcg;
  268. begin
  269. secondpass(left);
  270. if inlinenumber=in_pred_x then
  271. cgop:=OP_SUB
  272. else
  273. cgop:=OP_ADD;
  274. location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
  275. if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
  276. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
  277. {$ifndef cpu64bitalu}
  278. if def_cgsize(resultdef) in [OS_64,OS_S64] then
  279. begin
  280. location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
  281. location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
  282. cg64.a_op64_const_reg_reg(current_asmdata.CurrAsmList,cgop,def_cgsize(resultdef),1,left.location.register64,location.register64);
  283. end
  284. else
  285. {$endif not cpu64bitalu}
  286. begin
  287. location.register:=hlcg.getregisterfordef(current_asmdata.CurrAsmList,resultdef);
  288. hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,cgop,resultdef,1,left.location.register,location.register);
  289. end;
  290. end;
  291. {*****************************************************************************
  292. INC/DEC GENERIC HANDLING
  293. *****************************************************************************}
  294. procedure tcginlinenode.second_IncDec;
  295. const
  296. addsubop:array[in_inc_x..in_dec_x] of TOpCG=(OP_ADD,OP_SUB);
  297. var
  298. addvalue : TConstExprInt;
  299. addconstant : boolean;
  300. {$ifndef cpu64bitalu}
  301. hregisterhi,
  302. {$endif not cpu64bitalu}
  303. hregister : tregister;
  304. begin
  305. { set defaults }
  306. addconstant:=true;
  307. hregister:=NR_NO;
  308. {$ifndef cpu64bitalu}
  309. hregisterhi:=NR_NO;
  310. {$endif not cpu64bitalu}
  311. { first secondpass second argument, because if the first arg }
  312. { is used in that expression then SSL may move it to another }
  313. { register }
  314. if assigned(tcallparanode(left).right) then
  315. secondpass(tcallparanode(tcallparanode(left).right).left);
  316. { load first parameter, must be a reference }
  317. secondpass(tcallparanode(left).left);
  318. { get addvalue }
  319. case tcallparanode(left).left.resultdef.typ of
  320. orddef,
  321. enumdef :
  322. addvalue:=1;
  323. pointerdef :
  324. begin
  325. if is_void(tpointerdef(tcallparanode(left).left.resultdef).pointeddef) then
  326. addvalue:=1
  327. else
  328. addvalue:=tpointerdef(tcallparanode(left).left.resultdef).pointeddef.size;
  329. end;
  330. else
  331. internalerror(10081);
  332. end;
  333. { second_ argument specified?, must be a s32bit in register }
  334. if assigned(tcallparanode(left).right) then
  335. begin
  336. { when constant, just multiply the addvalue }
  337. if is_constintnode(tcallparanode(tcallparanode(left).right).left) then
  338. addvalue:=addvalue*get_ordinal_value(tcallparanode(tcallparanode(left).right).left)
  339. else if is_constpointernode(tcallparanode(tcallparanode(left).right).left) then
  340. addvalue:=addvalue*tpointerconstnode(tcallparanode(tcallparanode(left).right).left).value
  341. else
  342. begin
  343. hlcg.location_force_reg(current_asmdata.CurrAsmList,tcallparanode(tcallparanode(left).right).left.location,tcallparanode(tcallparanode(left).right).left.resultdef,left.resultdef,addvalue<=1);
  344. hregister:=tcallparanode(tcallparanode(left).right).left.location.register;
  345. {$ifndef cpu64bitalu}
  346. hregisterhi:=tcallparanode(tcallparanode(left).right).left.location.register64.reghi;
  347. {$endif not cpu64bitalu}
  348. { insert multiply with addvalue if its >1 }
  349. if addvalue>1 then
  350. hlcg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,left.resultdef,addvalue.svalue,hregister);
  351. addconstant:=false;
  352. end;
  353. end;
  354. { write the add instruction }
  355. if addconstant then
  356. begin
  357. {$ifndef cpu64bitalu}
  358. if def_cgsize(left.resultdef) in [OS_64,OS_S64] then
  359. cg64.a_op64_const_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],def_cgsize(left.resultdef),addvalue,tcallparanode(left).left.location)
  360. else
  361. {$endif not cpu64bitalu}
  362. hlcg.a_op_const_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],left.resultdef,
  363. {$ifdef cpu64bitalu}
  364. aint(addvalue.svalue),
  365. {$else cpu64bitalu}
  366. longint(addvalue.svalue), // can't use aint, because it breaks 16-bit and 8-bit CPUs
  367. {$endif cpu64bitalu}
  368. tcallparanode(left).left.location);
  369. end
  370. else
  371. begin
  372. {$ifndef cpu64bitalu}
  373. if def_cgsize(left.resultdef) in [OS_64,OS_S64] then
  374. cg64.a_op64_reg_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],def_cgsize(left.resultdef),
  375. joinreg64(hregister,hregisterhi),tcallparanode(left).left.location)
  376. else
  377. {$endif not cpu64bitalu}
  378. hlcg.a_op_reg_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],left.resultdef,
  379. hregister,tcallparanode(left).left.location);
  380. end;
  381. { no overflow checking for pointers (see ninl), and range checking }
  382. { is not applicable for them }
  383. if (tcallparanode(left).left.resultdef.typ <> pointerdef) then
  384. begin
  385. { things which can overflow must NOT pass via here, but have to be }
  386. { handled via a regular add node (conversion in tinlinenode.pass_1) }
  387. { Or someone has to rewrite the above to use a_op_const_reg_reg_ov }
  388. { and friends in case of overflow checking, and ask everyone to }
  389. { implement these methods since they don't exist for all cpus (JM) }
  390. { Similarly, range checking also has to be handled separately, }
  391. { see mantis #14841 (JM) }
  392. if ([cs_check_overflow,cs_check_range] * current_settings.localswitches <> []) then
  393. internalerror(2006111010);
  394. // cg.g_overflowcheck(current_asmdata.CurrAsmList,tcallparanode(left).left.location,tcallparanode(left).resultdef);
  395. // cg.g_rangecheck(current_asmdata.CurrAsmList,tcallparanode(left).left.location,tcallparanode(left).left.resultdef,
  396. // tcallparanode(left).left.resultdef);
  397. end;
  398. end;
  399. {*****************************************************************************
  400. AND/OR/XOR/SHIFT/ROTATE ASSIGN GENERIC HANDLING
  401. *****************************************************************************}
  402. procedure tcginlinenode.second_AndOrXorShiftRot_assign;
  403. const
  404. andorxorop:array[in_and_assign_x_y..in_ror_assign_x_y] of TOpCG=
  405. (OP_AND,OP_OR,OP_XOR,OP_SAR,OP_SHL,OP_SHR,OP_ROL,OP_ROR);
  406. var
  407. maskvalue : TConstExprInt;
  408. maskconstant : boolean;
  409. {$ifndef cpu64bitalu}
  410. hregisterhi,
  411. {$endif not cpu64bitalu}
  412. hregister : tregister;
  413. begin
  414. { set defaults }
  415. maskconstant:=true;
  416. hregister:=NR_NO;
  417. maskvalue:=0;
  418. {$ifndef cpu64bitalu}
  419. hregisterhi:=NR_NO;
  420. {$endif not cpu64bitalu}
  421. { first secondpass first argument, because if the second arg }
  422. { is used in that expression then SSL may move it to another }
  423. { register }
  424. secondpass(tcallparanode(left).left);
  425. { load second parameter, must be a reference }
  426. secondpass(tcallparanode(tcallparanode(left).right).left);
  427. { when constant, just get the maskvalue }
  428. if is_constintnode(tcallparanode(left).left) then
  429. maskvalue:=get_ordinal_value(tcallparanode(left).left)
  430. else
  431. begin
  432. { for shift/rotate the shift count can be of different size than the shifted variable }
  433. if inlinenumber in [in_sar_assign_x_y,in_shl_assign_x_y,in_shr_assign_x_y,in_rol_assign_x_y,in_ror_assign_x_y] then
  434. hlcg.location_force_reg(current_asmdata.CurrAsmList,tcallparanode(left).left.location,tcallparanode(left).left.resultdef,tcallparanode(left).left.resultdef,true)
  435. else
  436. hlcg.location_force_reg(current_asmdata.CurrAsmList,tcallparanode(left).left.location,tcallparanode(left).left.resultdef,tcallparanode(left).right.resultdef,true);
  437. hregister:=tcallparanode(left).left.location.register;
  438. {$ifndef cpu64bitalu}
  439. hregisterhi:=tcallparanode(left).left.location.register64.reghi;
  440. {$endif not cpu64bitalu}
  441. maskconstant:=false;
  442. end;
  443. { write the and/or/xor/sar/shl/shr/rol/ror instruction }
  444. if maskconstant then
  445. begin
  446. if inlinenumber in [in_sar_assign_x_y,in_shl_assign_x_y,in_shr_assign_x_y,in_rol_assign_x_y,in_ror_assign_x_y] then
  447. if def_cgsize(tcallparanode(left).right.resultdef) in [OS_64,OS_S64] then
  448. maskvalue:=maskvalue and 63
  449. else
  450. maskvalue:=maskvalue and 31;
  451. {$ifndef cpu64bitalu}
  452. if def_cgsize(tcallparanode(left).right.resultdef) in [OS_64,OS_S64] then
  453. cg64.a_op64_const_loc(current_asmdata.CurrAsmList,andorxorop[inlinenumber],def_cgsize(tcallparanode(left).right.resultdef),maskvalue.svalue,tcallparanode(tcallparanode(left).right).left.location)
  454. else
  455. {$endif not cpu64bitalu}
  456. hlcg.a_op_const_loc(current_asmdata.CurrAsmList,andorxorop[inlinenumber],tcallparanode(left).right.resultdef,
  457. {$ifdef cpu64bitalu}
  458. aint(maskvalue.svalue),
  459. {$else cpu64bitalu}
  460. longint(maskvalue.svalue), // can't use aint, because it breaks 16-bit and 8-bit CPUs
  461. {$endif cpu64bitalu}
  462. tcallparanode(tcallparanode(left).right).left.location);
  463. end
  464. else
  465. begin
  466. {$ifndef cpu64bitalu}
  467. if def_cgsize(tcallparanode(left).right.resultdef) in [OS_64,OS_S64] then
  468. cg64.a_op64_reg_loc(current_asmdata.CurrAsmList,andorxorop[inlinenumber],def_cgsize(tcallparanode(left).right.resultdef),
  469. joinreg64(hregister,hregisterhi),tcallparanode(tcallparanode(left).right).left.location)
  470. else
  471. {$endif not cpu64bitalu}
  472. hlcg.a_op_reg_loc(current_asmdata.CurrAsmList,andorxorop[inlinenumber],tcallparanode(left).right.resultdef,
  473. hregister,tcallparanode(tcallparanode(left).right).left.location);
  474. end;
  475. end;
  476. {*****************************************************************************
  477. NEG/NOT ASSIGN GENERIC HANDLING
  478. *****************************************************************************}
  479. procedure tcginlinenode.second_NegNot_assign;
  480. const
  481. negnotop:array[in_neg_assign_x..in_not_assign_x] of TOpCG=(OP_NEG,OP_NOT);
  482. {$ifndef cpu64bitalu}
  483. var
  484. NR_NO64: tregister64=(reglo:NR_NO;reghi:NR_NO);
  485. {$endif not cpu64bitalu}
  486. begin
  487. { load parameter, must be a reference }
  488. secondpass(left);
  489. location_reset(location,LOC_VOID,OS_NO);
  490. if left.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
  491. begin
  492. {$ifndef cpu64bitalu}
  493. if def_cgsize(left.resultdef) in [OS_64,OS_S64] then
  494. cg64.a_op64_reg_loc(current_asmdata.CurrAsmList,negnotop[inlinenumber],def_cgsize(left.resultdef),left.location.register64,left.location)
  495. else
  496. {$endif not cpu64bitalu}
  497. hlcg.a_op_reg_loc(current_asmdata.CurrAsmList,negnotop[inlinenumber],left.resultdef,left.location.register,left.location);
  498. end
  499. else if left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
  500. begin
  501. {$ifndef cpu64bitalu}
  502. if def_cgsize(left.resultdef) in [OS_64,OS_S64] then
  503. cg64.a_op64_reg_loc(current_asmdata.CurrAsmList,negnotop[inlinenumber],def_cgsize(left.resultdef),NR_NO64,left.location)
  504. else
  505. {$endif not cpu64bitalu}
  506. hlcg.a_op_reg_loc(current_asmdata.CurrAsmList,negnotop[inlinenumber],left.resultdef,NR_NO,left.location);
  507. end
  508. else
  509. internalerror(2017040701);
  510. end;
  511. {*****************************************************************************
  512. TYPEINFO GENERIC HANDLING
  513. *****************************************************************************}
  514. procedure tcginlinenode.second_typeinfo;
  515. begin
  516. internalerror(2013060301);
  517. end;
  518. {*****************************************************************************
  519. INCLUDE/EXCLUDE GENERIC HANDLING
  520. *****************************************************************************}
  521. procedure tcginlinenode.second_IncludeExclude;
  522. var
  523. setpara, elepara: tnode;
  524. begin
  525. { the set }
  526. secondpass(tcallparanode(left).left);
  527. { the element to set }
  528. secondpass(tcallparanode(tcallparanode(left).right).left);
  529. setpara:=tcallparanode(left).left;
  530. elepara:=tcallparanode(tcallparanode(left).right).left;
  531. if elepara.location.loc=LOC_CONSTANT then
  532. begin
  533. hlcg.a_bit_set_const_loc(current_asmdata.CurrAsmList,(inlinenumber=in_include_x_y),
  534. setpara.resultdef,elepara.location.value-tsetdef(setpara.resultdef).setbase,setpara.location);
  535. end
  536. else
  537. begin
  538. hlcg.location_force_reg(current_asmdata.CurrAsmList,elepara.location,elepara.resultdef,u32inttype,true);
  539. register_maybe_adjust_setbase(current_asmdata.CurrAsmList,u32inttype,elepara.location,tsetdef(setpara.resultdef).setbase);
  540. hlcg.a_bit_set_reg_loc(current_asmdata.CurrAsmList,(inlinenumber=in_include_x_y),
  541. u32inttype,setpara.resultdef,elepara.location.register,setpara.location);
  542. end;
  543. end;
  544. {*****************************************************************************
  545. FLOAT GENERIC HANDLING
  546. *****************************************************************************}
  547. {
  548. These routines all call internal RTL routines, so if they are
  549. called here, they give an internal error
  550. }
  551. procedure tcginlinenode.second_pi;
  552. begin
  553. internalerror(20020718);
  554. end;
  555. procedure tcginlinenode.second_arctan_real;
  556. begin
  557. internalerror(20020718);
  558. end;
  559. procedure tcginlinenode.second_abs_real;
  560. begin
  561. internalerror(20020718);
  562. end;
  563. procedure tcginlinenode.second_round_real;
  564. begin
  565. internalerror(20020718);
  566. end;
  567. procedure tcginlinenode.second_trunc_real;
  568. begin
  569. internalerror(20020718);
  570. end;
  571. procedure tcginlinenode.second_int_real;
  572. begin
  573. internalerror(2016112702);
  574. end;
  575. procedure tcginlinenode.second_sqr_real;
  576. begin
  577. internalerror(20020718);
  578. end;
  579. procedure tcginlinenode.second_sqrt_real;
  580. begin
  581. internalerror(20020718);
  582. end;
  583. procedure tcginlinenode.second_ln_real;
  584. begin
  585. internalerror(20020718);
  586. end;
  587. procedure tcginlinenode.second_cos_real;
  588. begin
  589. internalerror(20020718);
  590. end;
  591. procedure tcginlinenode.second_sin_real;
  592. begin
  593. internalerror(20020718);
  594. end;
  595. procedure tcginlinenode.second_prefetch;
  596. begin
  597. end;
  598. procedure tcginlinenode.second_abs_long;
  599. var
  600. tempreg1, tempreg2: tregister;
  601. begin
  602. secondpass(left);
  603. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
  604. location:=left.location;
  605. location.register:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
  606. tempreg1:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
  607. tempreg2:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
  608. hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,left.resultdef,left.resultdef.size*8-1,left.location.register,tempreg1);
  609. hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.resultdef,left.location.register,tempreg1,tempreg2);
  610. hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmlist,OP_SUB,left.resultdef,tempreg1,tempreg2,location.register);
  611. end;
  612. {*****************************************************************************
  613. ASSIGNED GENERIC HANDLING
  614. *****************************************************************************}
  615. procedure tcginlinenode.second_assigned;
  616. begin
  617. internalerror(2013091602);
  618. end;
  619. procedure Tcginlinenode.second_get_frame;
  620. begin
  621. {$if defined(x86) or defined(arm)}
  622. if current_procinfo.framepointer=NR_STACK_POINTER_REG then
  623. begin
  624. location_reset(location,LOC_CONSTANT,OS_ADDR);
  625. location.value:=0;
  626. end
  627. else
  628. {$endif defined(x86) or defined(arm)}
  629. begin
  630. location_reset(location,LOC_CREGISTER,OS_ADDR);
  631. location.register:=current_procinfo.framepointer;
  632. end;
  633. end;
  634. procedure Tcginlinenode.second_get_caller_frame;
  635. var
  636. frame_reg:Tregister;
  637. use_frame_pointer:boolean;
  638. begin
  639. frame_reg:=NR_NO;
  640. if left<>nil then
  641. begin
  642. secondpass(left);
  643. if left.location.loc=LOC_CONSTANT then
  644. use_frame_pointer:=true
  645. else
  646. begin
  647. hlcg.location_force_reg(current_asmdata.currasmlist,left.location,left.resultdef,voidpointertype,false);
  648. frame_reg:=left.location.register;
  649. use_frame_pointer:=false;
  650. end
  651. end
  652. else
  653. begin
  654. use_frame_pointer:=current_procinfo.framepointer=NR_STACK_POINTER_REG;
  655. frame_reg:=current_procinfo.framepointer;
  656. end;
  657. if use_frame_pointer then
  658. begin
  659. location_reset(location,LOC_CREGISTER,OS_ADDR);
  660. location.register:=NR_FRAME_POINTER_REG;
  661. end
  662. else
  663. begin
  664. location_reset_ref(location,LOC_REFERENCE,OS_ADDR,sizeof(pint),[]);
  665. location.reference.base:=frame_reg;
  666. end;
  667. end;
  668. procedure Tcginlinenode.second_get_caller_addr;
  669. var
  670. frame_ref:Treference;
  671. begin
  672. if current_procinfo.framepointer=NR_STACK_POINTER_REG then
  673. begin
  674. location_reset(location,LOC_REGISTER,OS_ADDR);
  675. location.register:=cg.getaddressregister(current_asmdata.currasmlist);
  676. reference_reset_base(frame_ref,NR_STACK_POINTER_REG,{current_procinfo.calc_stackframe_size}tg.lasttemp,sizeof(pint),[]);
  677. cg.a_load_ref_reg(current_asmdata.currasmlist,OS_ADDR,OS_ADDR,frame_ref,location.register);
  678. end
  679. else
  680. begin
  681. location_reset(location,LOC_REGISTER,OS_ADDR);
  682. location.register:=cg.getaddressregister(current_asmdata.currasmlist);
  683. reference_reset_base(frame_ref,current_procinfo.framepointer,sizeof(pint),sizeof(pint),[]);
  684. cg.a_load_ref_reg(current_asmdata.currasmlist,OS_ADDR,OS_ADDR,frame_ref,location.register);
  685. end;
  686. end;
  687. procedure tcginlinenode.second_rox_sar;
  688. var
  689. op : topcg;
  690. op1,op2 : tnode;
  691. begin
  692. { one or two parameters? }
  693. if (left.nodetype=callparan) and
  694. assigned(tcallparanode(left).right) then
  695. begin
  696. op1:=tcallparanode(tcallparanode(left).right).left;
  697. op2:=tcallparanode(left).left;
  698. secondpass(op2);
  699. end
  700. else
  701. begin
  702. op1:=left;
  703. op2:=nil;
  704. end;
  705. secondpass(op1);
  706. case inlinenumber of
  707. in_ror_x,
  708. in_ror_x_y:
  709. op:=OP_ROR;
  710. in_rol_x,
  711. in_rol_x_y:
  712. op:=OP_ROL;
  713. in_sar_x,
  714. in_sar_x_y:
  715. op:=OP_SAR;
  716. else
  717. internalerror(2013120110);
  718. end;
  719. hlcg.location_force_reg(current_asmdata.CurrAsmList,op1.location,op1.resultdef,resultdef,true);
  720. location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
  721. {$ifndef cpu64bitalu}
  722. if def_cgsize(resultdef) in [OS_64,OS_S64] then
  723. begin
  724. location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
  725. location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
  726. end
  727. else
  728. {$endif not cpu64bitalu}
  729. location.register:=hlcg.getintregister(current_asmdata.CurrAsmList,resultdef);
  730. if assigned(op2) then
  731. begin
  732. { rotating by a constant directly coded: }
  733. if op2.nodetype=ordconstn then
  734. {$ifndef cpu64bitalu}
  735. if def_cgsize(resultdef) in [OS_64,OS_S64] then
  736. cg64.a_op64_const_reg_reg(current_asmdata.CurrAsmList,op,def_cgsize(resultdef),
  737. tordconstnode(op2).value.uvalue and (resultdef.size*8-1),
  738. op1.location.register64, location.register64)
  739. else
  740. {$endif not cpu64bitalu}
  741. hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,resultdef,
  742. tordconstnode(op2).value.uvalue and (resultdef.size*8-1),
  743. op1.location.register, location.register)
  744. else
  745. begin
  746. {$ifndef cpu64bitalu}
  747. if def_cgsize(resultdef) in [OS_64,OS_S64] then
  748. begin
  749. hlcg.location_force_reg(current_asmdata.CurrAsmList,op2.location,
  750. op2.resultdef,alusinttype,true);
  751. cg64.a_op64_reg_reg_reg(current_asmdata.CurrAsmList,op,def_cgsize(resultdef),
  752. joinreg64(op2.location.register,NR_NO),op1.location.register64,
  753. location.register64);
  754. end
  755. else
  756. {$endif not cpu64bitalu}
  757. begin
  758. hlcg.location_force_reg(current_asmdata.CurrAsmList,op2.location,
  759. op2.resultdef,resultdef,true);
  760. hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,resultdef,
  761. op2.location.register,op1.location.register,
  762. location.register);
  763. end;
  764. end;
  765. end
  766. else
  767. {$ifndef cpu64bitalu}
  768. if def_cgsize(resultdef) in [OS_64,OS_S64] then
  769. cg64.a_op64_const_reg_reg(current_asmdata.CurrAsmList,op,def_cgsize(resultdef),1,
  770. op1.location.register64,location.register64)
  771. else
  772. {$endif not cpu64bitalu}
  773. hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,resultdef,1,
  774. op1.location.register,location.register);
  775. end;
  776. procedure tcginlinenode.second_BsfBsr;
  777. var
  778. reverse: boolean;
  779. opsize: tcgsize;
  780. begin
  781. reverse:=(inlinenumber = in_bsr_x);
  782. secondpass(left);
  783. opsize:=tcgsize2unsigned[left.location.size];
  784. if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
  785. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,cgsize_orddef(opsize),true);
  786. location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
  787. location.register:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
  788. cg.a_bit_scan_reg_reg(current_asmdata.CurrAsmList,reverse,opsize,location.size,left.location.register,location.register);
  789. end;
  790. procedure tcginlinenode.second_new;
  791. begin
  792. internalerror(2011012202);
  793. end;
  794. procedure tcginlinenode.second_popcnt;
  795. begin
  796. internalerror(2012082601);
  797. end;
  798. procedure tcginlinenode.second_fma;
  799. begin
  800. internalerror(2014032701);
  801. end;
  802. begin
  803. cinlinenode:=tcginlinenode;
  804. end. s