popt386.pas 90 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1993-98 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. {$ifdef newOptimizations}
  20. {$define foropt}
  21. {$define replacereg}
  22. {$define arithopt}
  23. {$define foldarithops}
  24. {$endif newOptimizations}
  25. Interface
  26. Uses Aasm;
  27. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  28. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  29. Implementation
  30. Uses
  31. globtype,systems,
  32. globals,verbose,hcodegen,
  33. {$ifdef finaldestdebug}
  34. cobjects,
  35. {$endif finaldestdebug}
  36. cpubase,cpuasm,DAOpt386;
  37. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  38. Begin
  39. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  40. RegUsedAfterInstruction := Reg in UsedRegs
  41. End;
  42. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  43. {First pass of peepholeoptimizations}
  44. Var
  45. l : longint;
  46. p ,hp1, hp2 : pai;
  47. {$ifdef foropt}
  48. hp3, hp4: pai;
  49. {$endif foropt}
  50. TmpBool1, TmpBool2: Boolean;
  51. TmpRef: PReference;
  52. UsedRegs, TmpUsedRegs: TRegSet;
  53. Function SkipLabels(hp: Pai; var hp2: pai): boolean;
  54. {skips all labels and returns the next "real" instruction}
  55. Begin
  56. While assigned(hp^.next) and
  57. (pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
  58. hp := pai(hp^.next);
  59. If assigned(hp^.next) Then
  60. Begin
  61. SkipLabels := True;
  62. hp2 := pai(hp^.next)
  63. End
  64. Else
  65. Begin
  66. hp2 := hp;
  67. SkipLabels := False
  68. End;
  69. End;
  70. Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
  71. {traces sucessive jumps to their final destination and sets it, e.g.
  72. je l1 je l3
  73. <code> <code>
  74. l1: becomes l1:
  75. je l2 je l3
  76. <code> <code>
  77. l2: l2:
  78. jmp l3 jmp l3}
  79. Var p1, p2: pai;
  80. l: pasmlabel;
  81. Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
  82. Begin
  83. FindAnyLabel := false;
  84. While assigned(hp^.next) and
  85. (pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
  86. hp := pai(hp^.next);
  87. If assigned(hp^.next) and
  88. (pai(hp^.next)^.typ = ait_label) Then
  89. Begin
  90. FindAnyLabel := true;
  91. l := pai_label(hp^.next)^.l;
  92. End
  93. End;
  94. Begin
  95. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  96. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  97. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  98. Begin
  99. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  100. SkipLabels(p1,p1);
  101. If (pai(p1)^.typ = ait_instruction) and
  102. (paicpu(p1)^.is_jmp) Then
  103. If { the next instruction after the label where the jump hp arrives}
  104. { is unconditional or of the same type as hp, so continue }
  105. (paicpu(p1)^.condition in [C_None,hp^.condition]) or
  106. { the next instruction after the label where the jump hp arrives}
  107. { is the opposite of hp (so this one is never taken), but after }
  108. { that one there is a branch that will be taken, so perform a }
  109. { little hack: set p1 equal to this instruction (that's what the}
  110. { last SkipLabels is for, only works with short bool evaluation)}
  111. ((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
  112. SkipLabels(p1,p2) and
  113. (p2^.typ = ait_instruction) and
  114. (paicpu(p2)^.is_jmp) and
  115. (paicpu(p2)^.condition in [C_None,hp^.condition]) and
  116. SkipLabels(p1,p1)) Then
  117. Begin
  118. GetFinalDestination(asml, paicpu(p1));
  119. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  120. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  121. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  122. End
  123. Else
  124. If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
  125. if not FindAnyLabel(p1,l) then
  126. begin
  127. {$ifdef finaldestdebug}
  128. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  129. strpnew('previous label inserted'))));
  130. {$endif finaldestdebug}
  131. getlabel(l);
  132. insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
  133. dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
  134. hp^.oper[0].sym := l;
  135. inc(l^.refs);
  136. { this won't work, since the new label isn't in the labeltable }
  137. { so it will fail the rangecheck. Labeltable should become a }
  138. { hashtable to support this: }
  139. { GetFinalDestination(asml, hp); }
  140. end
  141. else
  142. begin
  143. {$ifdef finaldestdebug}
  144. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  145. strpnew('next label reused'))));
  146. {$endif finaldestdebug}
  147. inc(l^.refs);
  148. hp^.oper[0].sym := l;
  149. GetFinalDestination(asml, hp);
  150. end;
  151. End;
  152. End;
  153. Function DoSubAddOpt(var p: Pai): Boolean;
  154. Begin
  155. DoSubAddOpt := False;
  156. If GetLastInstruction(p, hp1) And
  157. (hp1^.typ = ait_instruction) And
  158. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  159. Case Paicpu(hp1)^.opcode Of
  160. A_DEC:
  161. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  162. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  163. Begin
  164. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  165. AsmL^.Remove(hp1);
  166. Dispose(hp1, Done)
  167. End;
  168. A_SUB:
  169. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  170. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  171. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  172. Begin
  173. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  174. AsmL^.Remove(hp1);
  175. Dispose(hp1, Done)
  176. End;
  177. A_ADD:
  178. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  179. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  180. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  181. Begin
  182. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  183. AsmL^.Remove(hp1);
  184. Dispose(hp1, Done);
  185. If (Paicpu(p)^.oper[0].val = 0) Then
  186. Begin
  187. hp1 := Pai(p^.next);
  188. AsmL^.Remove(p);
  189. Dispose(p, Done);
  190. If Not GetLastInstruction(hp1, p) Then
  191. p := hp1;
  192. DoSubAddOpt := True;
  193. End
  194. End;
  195. End;
  196. End;
  197. Begin
  198. P := BlockStart;
  199. UsedRegs := [];
  200. While (P <> BlockEnd) Do
  201. Begin
  202. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  203. Case P^.Typ Of
  204. ait_instruction:
  205. Begin
  206. { Handle Jmp Optimizations }
  207. if Paicpu(p)^.is_jmp then
  208. begin
  209. {the following if-block removes all code between a jmp and the next label,
  210. because it can never be executed}
  211. If (paicpu(p)^.opcode = A_JMP) Then
  212. Begin
  213. While GetNextInstruction(p, hp1) and
  214. ((hp1^.typ <> ait_label) or
  215. { skip unused labels, they're not referenced anywhere }
  216. Not(Pai_Label(hp1)^.l^.is_used)) Do
  217. If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
  218. Begin
  219. AsmL^.Remove(hp1);
  220. Dispose(hp1, done);
  221. End;
  222. End;
  223. If GetNextInstruction(p, hp1) then
  224. Begin
  225. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  226. Begin
  227. hp2:=pai(hp1^.next);
  228. asml^.remove(p);
  229. dispose(p,done);
  230. p:=hp2;
  231. continue;
  232. end
  233. Else
  234. Begin
  235. if hp1^.typ = ait_label then
  236. SkipLabels(hp1,hp1);
  237. If (pai(hp1)^.typ=ait_instruction) and
  238. (paicpu(hp1)^.opcode=A_JMP) and
  239. GetNextInstruction(hp1, hp2) And
  240. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  241. Then
  242. Begin
  243. if paicpu(p)^.opcode=A_Jcc then
  244. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  245. else
  246. begin
  247. If (LabDif <> 0) Then
  248. GetFinalDestination(asml, paicpu(p));
  249. p:=pai(p^.next);
  250. continue;
  251. end;
  252. Dec(pai_label(hp2)^.l^.refs);
  253. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  254. Inc(paicpu(p)^.oper[0].sym^.refs);
  255. asml^.remove(hp1);
  256. dispose(hp1,done);
  257. If (LabDif <> 0) Then
  258. GetFinalDestination(asml, paicpu(p));
  259. end
  260. else
  261. If (LabDif <> 0) Then
  262. GetFinalDestination(asml, paicpu(p));
  263. end;
  264. end
  265. end
  266. else
  267. { All other optimizes }
  268. begin
  269. For l := 0 to 2 Do
  270. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  271. With Paicpu(p)^.oper[l].ref^ Do
  272. Begin
  273. If (base = R_NO) And
  274. (index <> R_NO) And
  275. (scalefactor in [0,1])
  276. Then
  277. Begin
  278. base := index;
  279. index := R_NO
  280. End
  281. End;
  282. Case Paicpu(p)^.opcode Of
  283. A_AND:
  284. Begin
  285. If (Paicpu(p)^.oper[0].typ = top_const) And
  286. (Paicpu(p)^.oper[1].typ = top_reg) And
  287. GetNextInstruction(p, hp1) And
  288. (Pai(hp1)^.typ = ait_instruction) And
  289. (Paicpu(hp1)^.opcode = A_AND) And
  290. (Paicpu(hp1)^.oper[0].typ = top_const) And
  291. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  292. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  293. Then
  294. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  295. Begin
  296. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  297. AsmL^.Remove(hp1);
  298. Dispose(hp1, Done)
  299. End
  300. Else
  301. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  302. jump}
  303. If (Paicpu(p)^.oper[1].typ = top_reg) And
  304. GetNextInstruction(p, hp1) And
  305. (hp1^.typ = ait_instruction) And
  306. (Paicpu(hp1)^.is_jmp) and
  307. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  308. Paicpu(p)^.opcode := A_TEST;
  309. End;
  310. A_CMP:
  311. Begin
  312. If (Paicpu(p)^.oper[0].typ = top_const) And
  313. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  314. (Paicpu(p)^.oper[0].val = 0) Then
  315. {$ifdef foropt}
  316. If GetNextInstruction(p, hp1) And
  317. (hp1^.typ = ait_instruction) And
  318. (Paicpu(hp1)^.is_jmp) and
  319. (paicpu(hp1)^.opcode=A_Jcc) and
  320. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  321. GetNextInstruction(hp1,hp2) and
  322. (hp2^.typ = ait_instruction) and
  323. (Paicpu(hp2)^.opcode = A_DEC) And
  324. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  325. GetNextInstruction(hp2, hp3) And
  326. (hp3^.typ = ait_instruction) and
  327. (Paicpu(hp3)^.is_jmp) and
  328. (Paicpu(hp3)^.opcode = A_JMP) And
  329. GetNextInstruction(hp3, hp4) And
  330. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  331. Then
  332. Begin
  333. Paicpu(hp2)^.Opcode := A_SUB;
  334. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  335. Paicpu(hp2)^.LoadConst(0,1);
  336. Paicpu(hp2)^.ops:=2;
  337. Paicpu(hp3)^.Opcode := A_Jcc;
  338. Case paicpu(hp1)^.condition of
  339. C_LE: Paicpu(hp3)^.condition := C_GE;
  340. C_BE: Paicpu(hp3)^.condition := C_AE;
  341. End;
  342. AsmL^.Remove(p);
  343. AsmL^.Remove(hp1);
  344. Dispose(p, Done);
  345. Dispose(hp1, Done);
  346. p := hp2;
  347. continue;
  348. End
  349. Else
  350. {$endif foropt}
  351. {change "cmp $0, %reg" to "test %reg, %reg"}
  352. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  353. Begin
  354. Paicpu(p)^.opcode := A_TEST;
  355. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  356. End;
  357. End;
  358. A_FLD:
  359. Begin
  360. If (Paicpu(p)^.oper[0].typ = top_reg) And
  361. GetNextInstruction(p, hp1) And
  362. (hp1^.typ = Ait_Instruction) And
  363. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  364. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  365. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  366. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  367. { change to
  368. fld reg fxxx reg,st
  369. fxxxp st, st1 (hp1)
  370. Remark: non commutative operations must be reversed!
  371. }
  372. begin
  373. Case Paicpu(hp1)^.opcode Of
  374. A_FMULP,A_FADDP,
  375. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  376. begin
  377. Case Paicpu(hp1)^.opcode Of
  378. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  379. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  380. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  381. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  382. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  383. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  384. End;
  385. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  386. Paicpu(hp1)^.oper[1].reg := R_ST;
  387. AsmL^.Remove(p);
  388. Dispose(p, Done);
  389. p := hp1;
  390. Continue;
  391. end;
  392. end;
  393. end
  394. else
  395. If (Paicpu(p)^.oper[0].typ = top_ref) And
  396. GetNextInstruction(p, hp2) And
  397. (hp2^.typ = Ait_Instruction) And
  398. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  399. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  400. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  401. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  402. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  403. If GetLastInstruction(p, hp1) And
  404. (hp1^.typ = Ait_Instruction) And
  405. ((Paicpu(hp1)^.opcode = A_FLD) Or
  406. (Paicpu(hp1)^.opcode = A_FST)) And
  407. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  408. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  409. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  410. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  411. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  412. { change to
  413. fld/fst mem1 (hp1) fld/fst mem1
  414. fld mem1 (p) fadd/
  415. faddp/ fmul st, st
  416. fmulp st, st1 (hp2) }
  417. Begin
  418. AsmL^.Remove(p);
  419. Dispose(p, Done);
  420. p := hp1;
  421. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  422. Paicpu(hp2)^.opcode := A_FADD
  423. Else
  424. Paicpu(hp2)^.opcode := A_FMUL;
  425. Paicpu(hp2)^.oper[1].reg := R_ST;
  426. End
  427. Else
  428. { change to
  429. fld/fst mem1 (hp1) fld/fst mem1
  430. fld mem1 (p) fld st}
  431. Begin
  432. Paicpu(p)^.changeopsize(S_FL);
  433. Paicpu(p)^.loadreg(0,R_ST);
  434. End
  435. Else
  436. Begin
  437. Case Paicpu(hp2)^.opcode Of
  438. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  439. { change to
  440. fld/fst mem1 (hp1) fld/fst mem1
  441. fld mem2 (p) fxxx mem2
  442. fxxxp st, st1 (hp2) }
  443. Begin
  444. Case Paicpu(hp2)^.opcode Of
  445. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  446. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  447. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  448. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  449. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  450. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  451. End;
  452. AsmL^.Remove(hp2);
  453. Dispose(hp2, Done)
  454. End
  455. End
  456. End
  457. End;
  458. A_FSTP,A_FISTP:
  459. Begin
  460. If (Paicpu(p)^.oper[0].typ = top_ref) And
  461. GetNextInstruction(p, hp1) And
  462. (Pai(hp1)^.typ = ait_instruction) And
  463. (((Paicpu(hp1)^.opcode = A_FLD) And
  464. (Paicpu(p)^.opcode = A_FSTP)) Or
  465. ((Paicpu(p)^.opcode = A_FISTP) And
  466. (Paicpu(hp1)^.opcode = A_FILD))) And
  467. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  468. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  469. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^)
  470. Then
  471. Begin
  472. If GetNextInstruction(hp1, hp2) And
  473. (hp2^.typ = ait_instruction) And
  474. ((Paicpu(hp2)^.opcode = A_LEAVE) Or
  475. (Paicpu(hp2)^.opcode = A_RET)) And
  476. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  477. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  478. (Paicpu(p)^.oper[0].ref^.Index = R_NO)
  479. Then
  480. Begin
  481. AsmL^.Remove(p);
  482. AsmL^.Remove(hp1);
  483. Dispose(p, Done);
  484. Dispose(hp1, Done);
  485. p := hp2;
  486. Continue
  487. End
  488. Else
  489. {fst can't store an extended value!}
  490. If (Paicpu(p)^.opsize <> S_FX) And
  491. (Paicpu(p)^.opsize <> S_IQ) Then
  492. Begin
  493. If (Paicpu(p)^.opcode = A_FSTP) Then
  494. Paicpu(p)^.opcode := A_FST
  495. Else Paicpu(p)^.opcode := A_FIST;
  496. AsmL^.Remove(hp1);
  497. Dispose(hp1, done)
  498. End
  499. End;
  500. End;
  501. A_IMUL:
  502. {changes certain "imul const, %reg"'s to lea sequences}
  503. Begin
  504. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  505. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  506. (Paicpu(p)^.opsize = S_L) Then
  507. If (Paicpu(p)^.oper[0].val = 1) Then
  508. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  509. {remove "imul $1, reg"}
  510. Begin
  511. hp1 := Pai(p^.Next);
  512. AsmL^.Remove(p);
  513. Dispose(p, Done);
  514. p := hp1;
  515. Continue;
  516. End
  517. Else
  518. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  519. Begin
  520. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  521. hp1^.fileinfo := p^.fileinfo;
  522. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  523. Dispose(p, Done);
  524. p := hp1;
  525. End
  526. Else If
  527. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  528. (Paicpu(p)^.oper[2].typ = Top_None)) And
  529. (aktoptprocessor < ClassP6) And
  530. (Paicpu(p)^.oper[0].val <= 12) And
  531. Not(CS_LittleSize in aktglobalswitches) And
  532. (Not(GetNextInstruction(p, hp1)) Or
  533. {GetNextInstruction(p, hp1) And}
  534. Not((Pai(hp1)^.typ = ait_instruction) And
  535. ((paicpu(hp1)^.opcode=A_Jcc) and
  536. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  537. Then
  538. Begin
  539. New(TmpRef);
  540. Reset_reference(tmpref^);
  541. Case Paicpu(p)^.oper[0].val Of
  542. 3: Begin
  543. {imul 3, reg1, reg2 to
  544. lea (reg1,reg1,2), reg2
  545. imul 3, reg1 to
  546. lea (reg1,reg1,2), reg1}
  547. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  548. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  549. TmpRef^.ScaleFactor := 2;
  550. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  551. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  552. Else
  553. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  554. hp1^.fileinfo := p^.fileinfo;
  555. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  556. Dispose(p, Done);
  557. p := hp1;
  558. End;
  559. 5: Begin
  560. {imul 5, reg1, reg2 to
  561. lea (reg1,reg1,4), reg2
  562. imul 5, reg1 to
  563. lea (reg1,reg1,4), reg1}
  564. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  565. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  566. TmpRef^.ScaleFactor := 4;
  567. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  568. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  569. Else
  570. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  571. hp1^.fileinfo:= p^.fileinfo;
  572. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  573. Dispose(p, Done);
  574. p := hp1;
  575. End;
  576. 6: Begin
  577. {imul 6, reg1, reg2 to
  578. lea (,reg1,2), reg2
  579. lea (reg2,reg1,4), reg2
  580. imul 6, reg1 to
  581. lea (reg1,reg1,2), reg1
  582. add reg1, reg1}
  583. If (aktoptprocessor <= Class386)
  584. Then
  585. Begin
  586. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  587. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  588. Then
  589. Begin
  590. TmpRef^.base := Paicpu(p)^.oper[2].reg;
  591. TmpRef^.ScaleFactor := 4;
  592. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  593. End
  594. Else
  595. Begin
  596. Dispose(TmpRef);
  597. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  598. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  599. End;
  600. hp1^.fileinfo := p^.fileinfo;
  601. InsertLLItem(AsmL,p, p^.next, hp1);
  602. New(TmpRef);
  603. Reset_reference(tmpref^);
  604. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  605. TmpRef^.ScaleFactor := 2;
  606. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  607. Then
  608. Begin
  609. TmpRef^.base := R_NO;
  610. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef,
  611. Paicpu(p)^.oper[2].reg));
  612. End
  613. Else
  614. Begin
  615. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  616. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  617. End;
  618. hp1^.fileinfo := p^.fileinfo;
  619. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  620. Dispose(p, Done);
  621. p := Pai(hp1^.next);
  622. End
  623. Else Dispose(TmpRef);
  624. End;
  625. 9: Begin
  626. {imul 9, reg1, reg2 to
  627. lea (reg1,reg1,8), reg2
  628. imul 9, reg1 to
  629. lea (reg1,reg1,8), reg1}
  630. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  631. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  632. TmpRef^.ScaleFactor := 8;
  633. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  634. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg))
  635. Else
  636. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  637. hp1^.fileinfo := p^.fileinfo;
  638. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  639. Dispose(p, Done);
  640. p := hp1;
  641. End;
  642. 10: Begin
  643. {imul 10, reg1, reg2 to
  644. lea (reg1,reg1,4), reg2
  645. add reg2, reg2
  646. imul 10, reg1 to
  647. lea (reg1,reg1,4), reg1
  648. add reg1, reg1}
  649. If (aktoptprocessor <= Class386) Then
  650. Begin
  651. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  652. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  653. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  654. Else
  655. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  656. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  657. hp1^.fileinfo := p^.fileinfo;
  658. InsertLLItem(AsmL,p, p^.next, hp1);
  659. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  660. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  661. TmpRef^.ScaleFactor := 4;
  662. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  663. Then
  664. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg))
  665. Else
  666. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  667. hp1^.fileinfo := p^.fileinfo;
  668. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  669. Dispose(p, Done);
  670. p := Pai(hp1^.next);
  671. End
  672. Else Dispose(TmpRef);
  673. End;
  674. 12: Begin
  675. {imul 12, reg1, reg2 to
  676. lea (,reg1,4), reg2
  677. lea (,reg1,8) reg2
  678. imul 12, reg1 to
  679. lea (reg1,reg1,2), reg1
  680. lea (,reg1,4), reg1}
  681. If (aktoptprocessor <= Class386)
  682. Then
  683. Begin
  684. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  685. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  686. Begin
  687. TmpRef^.base := Paicpu(p)^.oper[2].reg;
  688. TmpRef^.ScaleFactor := 8;
  689. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  690. End
  691. Else
  692. Begin
  693. TmpRef^.base := R_NO;
  694. TmpRef^.ScaleFactor := 4;
  695. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  696. End;
  697. hp1^.fileinfo := p^.fileinfo;
  698. InsertLLItem(AsmL,p, p^.next, hp1);
  699. New(TmpRef);
  700. Reset_reference(tmpref^);
  701. TmpRef^.Index := Paicpu(p)^.oper[1].reg;
  702. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  703. Begin
  704. TmpRef^.base := R_NO;
  705. TmpRef^.ScaleFactor := 4;
  706. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[2].reg));
  707. End
  708. Else
  709. Begin
  710. TmpRef^.base := Paicpu(p)^.oper[1].reg;
  711. TmpRef^.ScaleFactor := 2;
  712. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef, Paicpu(p)^.oper[1].reg));
  713. End;
  714. hp1^.fileinfo := p^.fileinfo;
  715. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  716. Dispose(p, Done);
  717. p := Pai(hp1^.next);
  718. End
  719. Else Dispose(TmpRef);
  720. End
  721. Else Dispose(TmpRef);
  722. End;
  723. End;
  724. End;
  725. A_LEA:
  726. Begin
  727. {removes seg register prefixes from LEA operations, as they
  728. don't do anything}
  729. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  730. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  731. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  732. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  733. (Paicpu(p)^.oper[0].ref^.Offset = 0) And
  734. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  735. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  736. Then
  737. Begin
  738. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  739. Paicpu(p)^.oper[1].reg));
  740. hp1^.fileinfo := p^.fileinfo;
  741. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  742. Dispose(p, Done);
  743. p := hp1;
  744. Continue;
  745. End
  746. Else
  747. Begin
  748. hp1 := Pai(p^.Next);
  749. AsmL^.Remove(p);
  750. Dispose(p, Done);
  751. p := hp1;
  752. Continue;
  753. End;
  754. End;
  755. A_MOV:
  756. Begin
  757. TmpUsedRegs := UsedRegs;
  758. If (Paicpu(p)^.oper[1].typ = top_reg) And
  759. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  760. GetNextInstruction(p, hp1) And
  761. (Pai(hp1)^.typ = ait_instruction) And
  762. (Paicpu(hp1)^.opcode = A_MOV) And
  763. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  764. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  765. Then
  766. {we have "mov x, %treg; mov %treg, y}
  767. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  768. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  769. Case Paicpu(p)^.oper[0].typ Of
  770. top_reg:
  771. Begin
  772. { change "mov %reg, %treg; mov %treg, y"
  773. to "mov %reg, y" }
  774. Paicpu(hp1)^.LoadOper(0,Paicpu(p)^.oper[0]);
  775. AsmL^.Remove(p);
  776. Dispose(p, Done);
  777. p := hp1;
  778. continue;
  779. End;
  780. top_ref:
  781. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  782. Begin
  783. { change "mov mem, %treg; mov %treg, %reg"
  784. to "mov mem, %reg" }
  785. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  786. AsmL^.Remove(hp1);
  787. Dispose(hp1, Done);
  788. continue;
  789. End;
  790. End
  791. Else
  792. {remove an instruction which never makes sense: we've got
  793. "mov mem, %reg1; mov %reg1, %edi" and then EDI isn't used anymore!}
  794. { Begin
  795. If (Paicpu(hp1)^.oper[1].reg = R_EDI) And
  796. Not(GetNextInstruction(hp1, hp2) And
  797. (Pai(hp2)^.typ = ait_instruction) And
  798. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  799. (Paicpu(hp2)^.oper[1] = Pointer(R_ESI))) Then
  800. Begin
  801. AsmL^.Remove(hp1);
  802. Dispose(hp1, Done);
  803. Continue;
  804. End
  805. End}
  806. Else
  807. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  808. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  809. penalty}
  810. If (Paicpu(p)^.oper[0].typ = top_reg) And
  811. (Paicpu(p)^.oper[1].typ = top_reg) And
  812. GetNextInstruction(p,hp1) And
  813. (Pai(hp1)^.typ = ait_instruction) And
  814. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  815. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  816. Then
  817. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  818. Begin
  819. If ((Paicpu(hp1)^.opcode = A_OR) Or
  820. (Paicpu(hp1)^.opcode = A_TEST)) And
  821. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  822. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  823. Then
  824. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  825. Begin
  826. TmpUsedRegs := UsedRegs;
  827. If GetNextInstruction(hp1, hp2) And
  828. (hp2^.typ = ait_instruction) And
  829. paicpu(hp2)^.is_jmp and
  830. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  831. Then
  832. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  833. "test %reg1, %reg1; jxx"}
  834. Begin
  835. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  836. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  837. AsmL^.Remove(p);
  838. Dispose(p, done);
  839. p := hp1;
  840. continue
  841. End
  842. Else
  843. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  844. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  845. Begin
  846. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  847. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  848. End;
  849. End
  850. { Else
  851. If (Paicpu(p^.next)^.opcode
  852. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  853. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  854. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  855. End
  856. Else
  857. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  858. x >= RetOffset) as it doesn't do anything (it writes either to a
  859. parameter or to the temporary storage room for the function
  860. result)}
  861. If GetNextInstruction(p, hp1) And
  862. (Pai(hp1)^.typ = ait_instruction)
  863. Then
  864. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  865. (Paicpu(hp1)^.opcode = A_RET)) And
  866. (Paicpu(p)^.oper[1].typ = top_ref) And
  867. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  868. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
  869. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  870. (Paicpu(p)^.oper[0].typ = top_reg)
  871. Then
  872. Begin
  873. AsmL^.Remove(p);
  874. Dispose(p, done);
  875. p := hp1;
  876. End
  877. Else
  878. If (Paicpu(p)^.oper[0].typ = top_reg) And
  879. (Paicpu(p)^.oper[1].typ = top_ref) And
  880. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  881. (Paicpu(hp1)^.opcode = A_CMP) And
  882. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  883. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^)
  884. Then
  885. {change "mov reg, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  886. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  887. { Next instruction is also a MOV ? }
  888. If GetNextInstruction(p, hp1) And
  889. (pai(hp1)^.typ = ait_instruction) and
  890. (Paicpu(hp1)^.opcode = A_MOV) and
  891. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  892. Then
  893. Begin
  894. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  895. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  896. Then
  897. {mov reg1, mem1 or mov mem1, reg1
  898. mov mem2, reg2 mov reg2, mem2}
  899. Begin
  900. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  901. {mov reg1, mem1 or mov mem1, reg1
  902. mov mem2, reg1 mov reg2, mem1}
  903. Begin
  904. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  905. { Removes the second statement from
  906. mov reg1, mem1
  907. mov mem1, reg1 }
  908. Begin
  909. AsmL^.remove(hp1);
  910. Dispose(hp1,done);
  911. End
  912. Else
  913. Begin
  914. TmpUsedRegs := UsedRegs;
  915. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  916. If (Paicpu(p)^.oper[0].typ = top_reg) And
  917. { mov reg1, mem1
  918. mov mem2, reg1 }
  919. GetNextInstruction(hp1, hp2) And
  920. (hp2^.typ = ait_instruction) And
  921. (Paicpu(hp2)^.opcode = A_CMP) And
  922. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  923. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  924. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  925. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  926. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  927. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  928. { change to
  929. mov reg1, mem1 mov reg1, mem1
  930. mov mem2, reg1 cmp reg1, mem2
  931. cmp mem1, reg1 }
  932. Begin
  933. AsmL^.Remove(hp2);
  934. Dispose(hp2, Done);
  935. Paicpu(hp1)^.opcode := A_CMP;
  936. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  937. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  938. End;
  939. End;
  940. End
  941. Else
  942. Begin
  943. If GetNextInstruction(hp1, hp2) And
  944. (Paicpu(p)^.oper[0].typ = top_ref) And
  945. (Paicpu(p)^.oper[1].typ = top_reg) And
  946. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  947. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  948. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  949. (Pai(hp2)^.typ = ait_instruction) And
  950. (Paicpu(hp2)^.opcode = A_MOV) And
  951. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  952. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  953. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  954. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^)
  955. Then
  956. If (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI])
  957. Then
  958. { mov mem1, %edi
  959. mov %edi, mem2
  960. mov mem2, reg2
  961. to:
  962. mov mem1, reg2
  963. mov reg2, mem2}
  964. Begin
  965. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  966. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  967. AsmL^.Remove(hp2);
  968. Dispose(hp2,Done);
  969. End
  970. Else
  971. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  972. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  973. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  974. Then
  975. { mov mem1, reg1 mov mem1, reg1
  976. mov reg1, mem2 mov reg1, mem2
  977. mov mem2, reg2 mov mem2, reg1
  978. to: to:
  979. mov mem1, reg1 mov mem1, reg1
  980. mov mem1, reg2 mov reg1, mem2
  981. mov reg1, mem2
  982. or (if mem1 depends on reg1
  983. and/or if mem2 depends on reg2)
  984. to:
  985. mov mem1, reg1
  986. mov reg1, mem2
  987. mov reg1, reg2
  988. }
  989. Begin
  990. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  991. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  992. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  993. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  994. End
  995. Else
  996. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  997. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg)
  998. Else
  999. Begin
  1000. AsmL^.Remove(hp2);
  1001. Dispose(hp2, Done);
  1002. End
  1003. End;
  1004. End
  1005. Else
  1006. (* {movl [mem1],reg1
  1007. movl [mem1],reg2
  1008. to:
  1009. movl [mem1],reg1
  1010. movl reg1,reg2 }
  1011. If (Paicpu(p)^.oper[0].typ = top_ref) and
  1012. (Paicpu(p)^.oper[1].typ = top_reg) and
  1013. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1014. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1015. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1016. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  1017. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  1018. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  1019. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  1020. Else*)
  1021. { movl const1,[mem1]
  1022. movl [mem1],reg1
  1023. to:
  1024. movl const1,reg1
  1025. movl reg1,[mem1] }
  1026. If (Paicpu(p)^.oper[0].typ = top_const) and
  1027. (Paicpu(p)^.oper[1].typ = top_ref) and
  1028. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1029. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1030. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1031. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  1032. Begin
  1033. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1034. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  1035. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  1036. End
  1037. End;
  1038. End;
  1039. A_MOVZX:
  1040. Begin
  1041. {removes superfluous And's after movzx's}
  1042. If (Paicpu(p)^.oper[1].typ = top_reg) And
  1043. GetNextInstruction(p, hp1) And
  1044. (Pai(hp1)^.typ = ait_instruction) And
  1045. (Paicpu(hp1)^.opcode = A_AND) And
  1046. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1047. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1048. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1049. Then
  1050. Case Paicpu(p)^.opsize Of
  1051. S_BL, S_BW:
  1052. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  1053. Begin
  1054. AsmL^.Remove(hp1);
  1055. Dispose(hp1, Done);
  1056. End;
  1057. S_WL:
  1058. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  1059. Begin
  1060. AsmL^.Remove(hp1);
  1061. Dispose(hp1, Done);
  1062. End;
  1063. End;
  1064. {changes some movzx constructs to faster synonims (all examples
  1065. are given with eax/ax, but are also valid for other registers)}
  1066. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1067. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1068. Case Paicpu(p)^.opsize of
  1069. S_BW:
  1070. Begin
  1071. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1072. Not(CS_LittleSize In aktglobalswitches)
  1073. Then
  1074. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1075. Begin
  1076. Paicpu(p)^.opcode := A_AND;
  1077. Paicpu(p)^.changeopsize(S_W);
  1078. Paicpu(p)^.LoadConst(0,$ff);
  1079. End
  1080. Else
  1081. If GetNextInstruction(p, hp1) And
  1082. (Pai(hp1)^.typ = ait_instruction) And
  1083. (Paicpu(hp1)^.opcode = A_AND) And
  1084. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1085. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1086. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1087. Then
  1088. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1089. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1090. Begin
  1091. Paicpu(p)^.opcode := A_MOV;
  1092. Paicpu(p)^.changeopsize(S_W);
  1093. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1094. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1095. End;
  1096. End;
  1097. S_BL:
  1098. Begin
  1099. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1100. Not(CS_LittleSize in aktglobalswitches)
  1101. Then
  1102. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1103. Begin
  1104. Paicpu(p)^.opcode := A_AND;
  1105. Paicpu(p)^.changeopsize(S_L);
  1106. Paicpu(p)^.loadconst(0,$ff)
  1107. End
  1108. Else
  1109. If GetNextInstruction(p, hp1) And
  1110. (Pai(hp1)^.typ = ait_instruction) And
  1111. (Paicpu(hp1)^.opcode = A_AND) And
  1112. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1113. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1114. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1115. Then
  1116. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1117. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1118. Begin
  1119. Paicpu(p)^.opcode := A_MOV;
  1120. Paicpu(p)^.changeopsize(S_L);
  1121. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1122. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1123. End
  1124. End;
  1125. S_WL:
  1126. Begin
  1127. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1128. Not(CS_LittleSize In aktglobalswitches)
  1129. Then
  1130. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1131. Begin
  1132. Paicpu(p)^.opcode := A_AND;
  1133. Paicpu(p)^.changeopsize(S_L);
  1134. Paicpu(p)^.LoadConst(0,$ffff);
  1135. End
  1136. Else
  1137. If GetNextInstruction(p, hp1) And
  1138. (Pai(hp1)^.typ = ait_instruction) And
  1139. (Paicpu(hp1)^.opcode = A_AND) And
  1140. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1141. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1142. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1143. Then
  1144. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1145. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1146. Begin
  1147. Paicpu(p)^.opcode := A_MOV;
  1148. Paicpu(p)^.changeopsize(S_L);
  1149. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1150. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1151. End;
  1152. End;
  1153. End
  1154. Else
  1155. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1156. Begin
  1157. If GetNextInstruction(p, hp1) And
  1158. (Pai(hp1)^.typ = ait_instruction) And
  1159. (Paicpu(hp1)^.opcode = A_AND) And
  1160. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1161. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1162. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1163. Begin
  1164. Paicpu(p)^.opcode := A_MOV;
  1165. Case Paicpu(p)^.opsize Of
  1166. S_BL:
  1167. Begin
  1168. Paicpu(p)^.changeopsize(S_L);
  1169. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1170. End;
  1171. S_WL:
  1172. Begin
  1173. Paicpu(p)^.changeopsize(S_L);
  1174. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1175. End;
  1176. S_BW:
  1177. Begin
  1178. Paicpu(p)^.changeopsize(S_W);
  1179. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1180. End;
  1181. End;
  1182. End;
  1183. End;
  1184. End;
  1185. A_POP:
  1186. Begin
  1187. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1188. GetNextInstruction(p, hp1) And
  1189. (pai(hp1)^.typ=ait_instruction) and
  1190. (Paicpu(hp1)^.opcode=A_PUSH) and
  1191. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1192. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1193. { This can't be done, because the register which is popped
  1194. can still be used after the push (PFV)
  1195. If (Not(cs_regalloc in aktglobalswitches)) Then
  1196. Begin
  1197. hp2:=pai(hp1^.next);
  1198. asml^.remove(p);
  1199. asml^.remove(hp1);
  1200. dispose(p,done);
  1201. dispose(hp1,done);
  1202. p:=hp2;
  1203. continue
  1204. End
  1205. Else }
  1206. Begin
  1207. { change it to a two op operation }
  1208. Paicpu(p)^.oper[1].typ:=top_none;
  1209. Paicpu(p)^.ops:=2;
  1210. Paicpu(p)^.opcode := A_MOV;
  1211. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1212. New(TmpRef);
  1213. Reset_reference(tmpref^);
  1214. TmpRef^.base := R_ESP;
  1215. Paicpu(p)^.LoadRef(0,TmpRef);
  1216. AsmL^.Remove(hp1);
  1217. Dispose(hp1, Done)
  1218. End;
  1219. end;
  1220. A_PUSH:
  1221. Begin
  1222. If (Paicpu(p)^.opsize = S_W) And
  1223. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1224. GetNextInstruction(p, hp1) And
  1225. (Pai(hp1)^.typ = ait_instruction) And
  1226. (Paicpu(hp1)^.opcode = A_PUSH) And
  1227. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1228. (Paicpu(hp1)^.opsize = S_W) Then
  1229. Begin
  1230. Paicpu(p)^.changeopsize(S_L);
  1231. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + Paicpu(hp1)^.oper[0].val);
  1232. AsmL^.Remove(hp1);
  1233. Dispose(hp1, Done)
  1234. End;
  1235. End;
  1236. A_SHL, A_SAL:
  1237. Begin
  1238. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1239. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1240. (Paicpu(p)^.opsize = S_L) And
  1241. (Paicpu(p)^.oper[0].val <= 3)
  1242. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1243. Then
  1244. Begin
  1245. TmpBool1 := True; {should we check the next instruction?}
  1246. TmpBool2 := False; {have we found an add/sub which could be
  1247. integrated in the lea?}
  1248. New(TmpRef);
  1249. Reset_reference(tmpref^);
  1250. TmpRef^.index := Paicpu(p)^.oper[1].reg;
  1251. TmpRef^.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1252. While TmpBool1 And
  1253. GetNextInstruction(p, hp1) And
  1254. (Pai(hp1)^.typ = ait_instruction) And
  1255. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1256. (Paicpu(hp1)^.opcode = A_SUB)) And
  1257. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1258. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1259. Begin
  1260. TmpBool1 := False;
  1261. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1262. Then
  1263. Begin
  1264. TmpBool1 := True;
  1265. TmpBool2 := True;
  1266. If Paicpu(hp1)^.opcode = A_ADD Then
  1267. Inc(TmpRef^.offset, Paicpu(hp1)^.oper[0].val)
  1268. Else
  1269. Dec(TmpRef^.offset, Paicpu(hp1)^.oper[0].val);
  1270. AsmL^.Remove(hp1);
  1271. Dispose(hp1, Done);
  1272. End
  1273. Else
  1274. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1275. (Paicpu(hp1)^.opcode = A_ADD) And
  1276. (TmpRef^.base = R_NO) Then
  1277. Begin
  1278. TmpBool1 := True;
  1279. TmpBool2 := True;
  1280. TmpRef^.base := Paicpu(hp1)^.oper[0].reg;
  1281. AsmL^.Remove(hp1);
  1282. Dispose(hp1, Done);
  1283. End;
  1284. End;
  1285. If TmpBool2 Or
  1286. ((aktoptprocessor < ClassP6) And
  1287. (Paicpu(p)^.oper[0].val <= 3) And
  1288. Not(CS_LittleSize in aktglobalswitches))
  1289. Then
  1290. Begin
  1291. If Not(TmpBool2) And
  1292. (Paicpu(p)^.oper[0].val = 1)
  1293. Then
  1294. Begin
  1295. Dispose(TmpRef);
  1296. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1297. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1298. End
  1299. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, TmpRef,
  1300. Paicpu(p)^.oper[1].reg));
  1301. hp1^.fileinfo := p^.fileinfo;
  1302. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1303. Dispose(p, Done);
  1304. p := hp1;
  1305. End;
  1306. End
  1307. Else
  1308. If (aktoptprocessor < ClassP6) And
  1309. (Paicpu(p)^.oper[0].typ = top_const) And
  1310. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1311. If (Paicpu(p)^.oper[0].val = 1)
  1312. Then
  1313. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1314. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1315. (unlike shl, which is only pairable in the U pipe)}
  1316. Begin
  1317. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1318. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1319. hp1^.fileinfo := p^.fileinfo;
  1320. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1321. Dispose(p, done);
  1322. p := hp1;
  1323. End
  1324. Else If (Paicpu(p)^.opsize = S_L) and
  1325. (Paicpu(p)^.oper[0].val<= 3) Then
  1326. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1327. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1328. Begin
  1329. New(TmpRef);
  1330. Reset_reference(tmpref^);
  1331. TmpRef^.index := Paicpu(p)^.oper[1].reg;
  1332. TmpRef^.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1333. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,TmpRef, Paicpu(p)^.oper[1].reg));
  1334. hp1^.fileinfo := p^.fileinfo;
  1335. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1336. Dispose(p, done);
  1337. p := hp1;
  1338. End
  1339. End;
  1340. A_SAR, A_SHR:
  1341. {changes the code sequence
  1342. shr/sar const1, x
  1343. shl const2, x
  1344. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1345. Begin
  1346. If GetNextInstruction(p, hp1) And
  1347. (pai(hp1)^.typ = ait_instruction) and
  1348. (Paicpu(hp1)^.opcode = A_SHL) and
  1349. (Paicpu(p)^.oper[0].typ = top_const) and
  1350. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1351. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1352. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1353. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1354. Then
  1355. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1356. Not(CS_LittleSize In aktglobalswitches)
  1357. Then
  1358. { shr/sar const1, %reg
  1359. shl const2, %reg
  1360. with const1 > const2 }
  1361. Begin
  1362. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1363. Paicpu(hp1)^.opcode := A_AND;
  1364. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1365. Case Paicpu(p)^.opsize Of
  1366. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1367. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1368. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1369. End;
  1370. End
  1371. Else
  1372. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1373. Not(CS_LittleSize In aktglobalswitches)
  1374. Then
  1375. { shr/sar const1, %reg
  1376. shl const2, %reg
  1377. with const1 < const2 }
  1378. Begin
  1379. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1380. Paicpu(p)^.opcode := A_AND;
  1381. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1382. Case Paicpu(p)^.opsize Of
  1383. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1384. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1385. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1386. End;
  1387. End
  1388. Else
  1389. { shr/sar const1, %reg
  1390. shl const2, %reg
  1391. with const1 = const2 }
  1392. Begin
  1393. Paicpu(p)^.opcode := A_AND;
  1394. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1395. Case Paicpu(p)^.opsize Of
  1396. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1397. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1398. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1399. End;
  1400. AsmL^.remove(hp1);
  1401. dispose(hp1, done);
  1402. End;
  1403. End;
  1404. A_SETcc :
  1405. Begin
  1406. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1407. GetNextInstruction(p, hp1) And
  1408. GetNextInstruction(hp1, hp2) And
  1409. (hp2^.typ = ait_instruction) And
  1410. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1411. (Paicpu(hp2)^.opcode = A_RET)) And
  1412. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1413. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1414. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  1415. (hp1^.typ = ait_instruction) And
  1416. (Paicpu(hp1)^.opcode = A_MOV) And
  1417. (Paicpu(hp1)^.opsize = S_B) And
  1418. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1419. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1420. Begin
  1421. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1422. AsmL^.Remove(hp1);
  1423. Dispose(hp1, Done)
  1424. End
  1425. End;
  1426. A_SUB:
  1427. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1428. { * change "sub/add const1, reg" or "dec reg" followed by
  1429. "sub const2, reg" to one "sub ..., reg" }
  1430. Begin
  1431. If (Paicpu(p)^.oper[0].typ = top_const) And
  1432. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1433. If (Paicpu(p)^.oper[0].val = 2) And
  1434. (Paicpu(p)^.oper[1].reg = R_ESP) Then
  1435. Begin
  1436. hp1 := Pai(p^.next);
  1437. While Assigned(hp1) And
  1438. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1439. Not((Pai(hp1)^.typ = ait_instruction) And
  1440. ((Paicpu(hp1)^.opcode = A_CALL) or
  1441. (Paicpu(hp1)^.opcode = A_PUSH) or
  1442. ((Paicpu(hp1)^.opcode = A_MOV) And
  1443. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1444. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1445. hp1 := Pai(hp1^.next);
  1446. If Assigned(hp1) And
  1447. (Pai(hp1)^.typ = ait_instruction) And
  1448. (Paicpu(hp1)^.opcode = A_PUSH) And
  1449. (Paicpu(hp1)^.opsize = S_W)
  1450. Then
  1451. Begin
  1452. Paicpu(hp1)^.changeopsize(S_L);
  1453. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1454. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1455. hp1 := Pai(p^.next);
  1456. AsmL^.Remove(p);
  1457. Dispose(p, Done);
  1458. p := hp1;
  1459. Continue
  1460. End;
  1461. If DoSubAddOpt(p) Then continue;
  1462. End
  1463. Else If DoSubAddOpt(p) Then Continue
  1464. End;
  1465. A_TEST, A_OR:
  1466. {removes the line marked with (x) from the sequence
  1467. And/or/xor/add/sub/... $x, %y
  1468. test/or %y, %y (x)
  1469. j(n)z _Label
  1470. as the first instruction already adjusts the ZF}
  1471. Begin
  1472. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1473. If GetLastInstruction(p, hp1) And
  1474. (pai(hp1)^.typ = ait_instruction) Then
  1475. Case Paicpu(hp1)^.opcode Of
  1476. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1477. Begin
  1478. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1479. Begin
  1480. hp1 := pai(p^.next);
  1481. asml^.remove(p);
  1482. dispose(p, done);
  1483. p := pai(hp1);
  1484. continue
  1485. End;
  1486. End;
  1487. A_DEC, A_INC, A_NEG:
  1488. Begin
  1489. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1490. Begin
  1491. Case Paicpu(hp1)^.opcode Of
  1492. A_DEC, A_INC:
  1493. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1494. Begin
  1495. Case Paicpu(hp1)^.opcode Of
  1496. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1497. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1498. End;
  1499. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1500. Paicpu(hp1)^.LoadConst(0,1);
  1501. Paicpu(hp1)^.ops:=2;
  1502. End
  1503. End;
  1504. hp1 := pai(p^.next);
  1505. asml^.remove(p);
  1506. dispose(p, done);
  1507. p := pai(hp1);
  1508. continue
  1509. End;
  1510. End
  1511. End
  1512. Else
  1513. End;
  1514. A_XOR:
  1515. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1516. (Paicpu(p)^.oper[1].typ = top_reg) And
  1517. (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
  1518. { temporarily change this to 'mov reg,0' to make it easier }
  1519. { for the CSE. Will be changed back in pass 2 }
  1520. begin
  1521. paicpu(p)^.opcode := A_MOV;
  1522. paicpu(p)^.loadconst(0,0);
  1523. end;
  1524. End;
  1525. end; { if is_jmp }
  1526. End;
  1527. { ait_label:
  1528. Begin
  1529. If Not(Pai_Label(p)^.l^.is_used)
  1530. Then
  1531. Begin
  1532. hp1 := Pai(p^.next);
  1533. AsmL^.Remove(p);
  1534. Dispose(p, Done);
  1535. p := hp1;
  1536. Continue
  1537. End;
  1538. End;}
  1539. End;
  1540. p:=pai(p^.next);
  1541. end;
  1542. end;
  1543. {$ifdef foldArithOps}
  1544. Function IsArithOp(opcode: TAsmOp): Boolean;
  1545. Begin
  1546. IsArithOp := False;
  1547. Case opcode Of
  1548. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR: IsArithOp := True
  1549. End;
  1550. End;
  1551. {$endif foldArithOps}
  1552. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1553. var
  1554. p,hp1,hp2: pai;
  1555. {$ifdef foldArithOps}
  1556. UsedRegs, TmpUsedRegs: TRegSet;
  1557. {$endif foldArithOps}
  1558. Begin
  1559. P := BlockStart;
  1560. {$ifdef foldArithOps}
  1561. UsedRegs := [];
  1562. {$endif foldArithOps}
  1563. While (P <> BlockEnd) Do
  1564. Begin
  1565. {$ifdef foldArithOps}
  1566. UpdateUsedRegs(UsedRegs, Pai(p^.next));
  1567. {$endif foldArithOps}
  1568. Case P^.Typ Of
  1569. Ait_Instruction:
  1570. Begin
  1571. Case Paicpu(p)^.opcode Of
  1572. A_CALL:
  1573. If (AktOptProcessor < ClassP6) And
  1574. GetNextInstruction(p, hp1) And
  1575. (hp1^.typ = ait_instruction) And
  1576. (paicpu(hp1)^.opcode = A_JMP) Then
  1577. Begin
  1578. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1579. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1580. hp2^.fileinfo := p^.fileinfo;
  1581. InsertLLItem(AsmL, p^.previous, p, hp2);
  1582. Paicpu(p)^.opcode := A_JMP;
  1583. AsmL^.Remove(hp1);
  1584. Dispose(hp1, Done)
  1585. End;
  1586. A_MOV:
  1587. Begin
  1588. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1589. (Paicpu(p)^.oper[1].typ = top_reg) And
  1590. GetNextInstruction(p, hp1) And
  1591. (hp1^.typ = ait_Instruction) And
  1592. ((Paicpu(hp1)^.opcode = A_MOV) or
  1593. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1594. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1595. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1596. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1597. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1598. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1599. (Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
  1600. {mov reg1, reg2
  1601. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1602. Begin
  1603. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1604. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1605. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1606. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1607. AsmL^.Remove(p);
  1608. Dispose(p, Done);
  1609. p := hp1;
  1610. Continue;
  1611. End
  1612. {$ifdef foldArithOps}
  1613. Else If (Paicpu(p)^.oper[0].typ = top_ref) And
  1614. GetNextInstruction(p,hp1) And
  1615. (hp1^.typ = ait_instruction) And
  1616. IsArithOp(Paicpu(hp1)^.opcode) And
  1617. (Paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) And
  1618. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1619. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) And
  1620. GetNextInstruction(hp1,hp2) And
  1621. (hp2^.typ = ait_instruction) And
  1622. (Paicpu(hp2)^.opcode = A_MOV) And
  1623. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  1624. (Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  1625. (Paicpu(hp2)^.oper[1].typ = top_ref) Then
  1626. Begin
  1627. TmpUsedRegs := UsedRegs;
  1628. UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
  1629. If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
  1630. Not(RegUsedAfterInstruction(Reg32(Paicpu(p)^.oper[1].reg),
  1631. hp2, TmpUsedRegs)))
  1632. Then
  1633. { change mov (ref), reg }
  1634. { add/sub/or/... reg2/$const, reg }
  1635. { mov (reg), ref }
  1636. { # relaese reg }
  1637. { to add/sub/or/... reg2/$const, (ref) }
  1638. Begin
  1639. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
  1640. AsmL^.Remove(p);
  1641. AsmL^.Remove(hp2);
  1642. Dispose(p,done);
  1643. Dispose(hp2,Done);
  1644. p := hp1
  1645. End;
  1646. End
  1647. {$endif foldArithOps}
  1648. else if (Paicpu(p)^.oper[0].typ = Top_Const) And
  1649. (Paicpu(p)^.oper[0].val = 0) And
  1650. (Paicpu(p)^.oper[1].typ = Top_Reg) Then
  1651. { change "mov $0, %reg" into "xor %reg, %reg" }
  1652. Begin
  1653. Paicpu(p)^.opcode := A_XOR;
  1654. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1655. End
  1656. End;
  1657. A_MOVZX:
  1658. Begin
  1659. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1660. If (Paicpu(p)^.oper[0].typ = top_reg)
  1661. Then
  1662. Case Paicpu(p)^.opsize of
  1663. S_BL:
  1664. Begin
  1665. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1666. Not(CS_LittleSize in aktglobalswitches) And
  1667. (aktoptprocessor = ClassP5)
  1668. Then
  1669. {Change "movzbl %reg1, %reg2" to
  1670. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1671. PentiumMMX}
  1672. Begin
  1673. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1674. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1675. hp1^.fileinfo := p^.fileinfo;
  1676. InsertLLItem(AsmL,p^.previous, p, hp1);
  1677. Paicpu(p)^.opcode := A_MOV;
  1678. Paicpu(p)^.changeopsize(S_B);
  1679. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1680. End;
  1681. End;
  1682. End
  1683. Else
  1684. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1685. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1686. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1687. Not(CS_LittleSize in aktglobalswitches) And
  1688. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1689. (aktoptprocessor = ClassP5) And
  1690. (Paicpu(p)^.opsize = S_BL)
  1691. Then
  1692. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1693. Pentium and PentiumMMX}
  1694. Begin
  1695. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1696. Paicpu(p)^.oper[1].reg));
  1697. hp1^.fileinfo := p^.fileinfo;
  1698. Paicpu(p)^.opcode := A_MOV;
  1699. Paicpu(p)^.changeopsize(S_B);
  1700. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1701. InsertLLItem(AsmL,p^.previous, p, hp1);
  1702. End;
  1703. End;
  1704. End;
  1705. End;
  1706. End;
  1707. p := Pai(p^.next)
  1708. End;
  1709. End;
  1710. End.
  1711. {
  1712. $Log$
  1713. Revision 1.74 1999-12-05 16:48:43 jonas
  1714. * CSE of constant loading in regs works properly again
  1715. + if a constant is stored into memory using "mov const, ref" and
  1716. there is a reg that contains this const, it is changed into
  1717. "mov reg, ref"
  1718. Revision 1.73 1999/12/02 11:26:41 peter
  1719. * newoptimizations define added
  1720. Revision 1.72 1999/11/30 10:40:45 peter
  1721. + ttype, tsymlist
  1722. Revision 1.71 1999/11/27 23:47:55 jonas
  1723. + change "mov var,reg; add/shr/... x,reg; mov reg,var" to
  1724. "add/shr/... x,var" (if x is a const or reg, suggestion from Peter)
  1725. Enable with -dfoldArithOps
  1726. Revision 1.70 1999/11/21 13:09:41 jonas
  1727. * fixed some missed optimizations because 8bit regs were not always
  1728. taken into account
  1729. Revision 1.69 1999/11/13 19:03:56 jonas
  1730. * don't remove align objects between JMP's and labels
  1731. Revision 1.68 1999/11/06 16:24:00 jonas
  1732. * getfinaldestination works completely again (a lot of functionality
  1733. got lost in the conversion resulting from the removal of
  1734. ait_labeled_instruction)
  1735. Revision 1.67 1999/11/06 14:34:23 peter
  1736. * truncated log to 20 revs
  1737. Revision 1.66 1999/09/27 23:44:55 peter
  1738. * procinfo is now a pointer
  1739. * support for result setting in sub procedure
  1740. Revision 1.65 1999/09/05 14:27:19 florian
  1741. + fld reg;fxxx to fxxxr reg optimization
  1742. Revision 1.64 1999/08/25 12:00:02 jonas
  1743. * changed pai386, paippc and paiapha (same for tai*) to paicpu (taicpu)
  1744. Revision 1.63 1999/08/23 10:20:46 jonas
  1745. * fixed pop/push optmization
  1746. Revision 1.62 1999/08/10 12:30:00 pierre
  1747. * avoid unused locals
  1748. Revision 1.61 1999/08/05 15:02:48 jonas
  1749. * "add/sub const,%esp;sub $2,%esp" wasn't always optimized
  1750. Revision 1.60 1999/08/04 00:23:16 florian
  1751. * renamed i386asm and i386base to cpuasm and cpubase
  1752. Revision 1.59 1999/08/03 17:13:28 jonas
  1753. * fix for sar/shr-shl optimization
  1754. Revision 1.58 1999/07/30 18:17:55 jonas
  1755. * fix so (,reg) gets optimized to (reg)
  1756. Revision 1.57 1999/07/01 18:12:16 jonas
  1757. * enabled "mov reg1,reg2;mov (reg2,..), reg2" also if the second mov is
  1758. a movzx or movsx
  1759. Revision 1.56 1999/06/23 12:33:52 jonas
  1760. * merged
  1761. Revision 1.54.2.2 1999/06/23 11:55:08 jonas
  1762. * fixed bug in "mov mem1,reg1;mov reg1,mem2;mov mem2,reg2" optimization
  1763. Revision 1.55 1999/06/18 09:55:31 peter
  1764. * merged
  1765. Revision 1.54.2.1 1999/06/18 09:52:40 peter
  1766. * pop;push -> mov (esp),reg always instead of being removed
  1767. Revision 1.54 1999/05/27 19:44:49 peter
  1768. * removed oldasm
  1769. * plabel -> pasmlabel
  1770. * -a switches to source writing automaticly
  1771. * assembler readers OOPed
  1772. * asmsymbol automaticly external
  1773. * jumptables and other label fixes for asm readers
  1774. Revision 1.53 1999/05/12 00:19:52 peter
  1775. * removed R_DEFAULT_SEG
  1776. * uniform float names
  1777. Revision 1.52 1999/05/05 16:19:04 jonas
  1778. + remove the segment prefixes from LEA instructions
  1779. Revision 1.51 1999/05/05 10:05:54 florian
  1780. * a delphi compiled compiler recompiles ppc
  1781. Revision 1.50 1999/05/02 21:33:55 florian
  1782. * several bugs regarding -Or fixed
  1783. Revision 1.49 1999/05/02 14:26:31 peter
  1784. * fixed dec -> sub $1 opt which didn't set ops=2
  1785. }