| .. |
|
aasmcpu.pas
|
095bd6da7d
* do not re-used gottpoff symbols as they are PC-relative
|
%!s(int64=6) %!d(string=hai) anos |
|
agarmgas.pas
|
8c362eac67
* always emit UAL when using LLVM (clang does not and will not support
|
%!s(int64=6) %!d(string=hai) anos |
|
aoptcpu.pas
|
94d7a02fae
* modified patch by Gareth Moreton to pool TmpUsedRegs in the assembler optimizers, resolves #34679
|
%!s(int64=6) %!d(string=hai) anos |
|
aoptcpub.pas
|
afd4599d26
* correctly handle LDRD in TAoptBaseCpu.RegModifiedByInstruction
|
%!s(int64=6) %!d(string=hai) anos |
|
aoptcpud.pas
|
790a4fe2d3
* log and id tags removed
|
%!s(int64=20) %!d(string=hai) anos |
|
armatt.inc
|
9d1646e2a8
Add support for writeback in RFE and SRS instructions.
|
%!s(int64=9) %!d(string=hai) anos |
|
armatts.inc
|
9d1646e2a8
Add support for writeback in RFE and SRS instructions.
|
%!s(int64=9) %!d(string=hai) anos |
|
armins.dat
|
4db5478acc
+ support msr regf,reg32 on arm in the internal assembler
|
%!s(int64=6) %!d(string=hai) anos |
|
armnop.inc
|
4db5478acc
+ support msr regf,reg32 on arm in the internal assembler
|
%!s(int64=6) %!d(string=hai) anos |
|
armop.inc
|
9d1646e2a8
Add support for writeback in RFE and SRS instructions.
|
%!s(int64=9) %!d(string=hai) anos |
|
armreg.dat
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
armtab.inc
|
4db5478acc
+ support msr regf,reg32 on arm in the internal assembler
|
%!s(int64=6) %!d(string=hai) anos |
|
cgcpu.pas
|
3a43ffd57b
* arm: Include pi_needs_got to current_procinfo.flags when the GOT register is accessed. It forces proper initialization of the GOT register at the beginning of a procedure. This fixes storing of a double constant to a field in a packed record and other rare copy operations when PIC is enabled.
|
%!s(int64=6) %!d(string=hai) anos |
|
cpubase.pas
|
7c4e7d6bd3
* support OS_32/OS_64 in cgsize2subreg for ARM MM registers to handle
|
%!s(int64=6) %!d(string=hai) anos |
|
cpuelf.pas
|
dbb91b5ef0
arm-netbsd: added platform define and dummy rtl files so the build passes for this platform. port not functional yet
|
%!s(int64=7) %!d(string=hai) anos |
|
cpuinfo.pas
|
5b755661d8
+ patch by Simon Ameis: adds all the STM32F091* microcontroller units to the list of supported ARM MCUs, resolves issue #32484
|
%!s(int64=7) %!d(string=hai) anos |
|
cpunode.pas
|
9f16c34329
+ initial work for tls-based threadvar support on arm-linux
|
%!s(int64=6) %!d(string=hai) anos |
|
cpupara.pas
|
bead1f8180
* properly set 8 byte parameter alignment for first parameter on ARM if
|
%!s(int64=6) %!d(string=hai) anos |
|
cpupi.pas
|
9f16c34329
+ initial work for tls-based threadvar support on arm-linux
|
%!s(int64=6) %!d(string=hai) anos |
|
cputarg.pas
|
86940dfb32
AROS: added arm-aros target to compiler and fpcmake
|
%!s(int64=8) %!d(string=hai) anos |
|
hlcgcpu.pas
|
4686f61002
* keep track of the temp position separately from the offset in references,
|
%!s(int64=7) %!d(string=hai) anos |
|
itcpugas.pas
|
47d43750e4
* remove unused units from uses statements
|
%!s(int64=12) %!d(string=hai) anos |
|
narmadd.pas
|
0b246f3dbd
* converted Boolean8 to an internal type, and mapped Boolean to the
|
%!s(int64=6) %!d(string=hai) anos |
|
narmcal.pas
|
f5f895e2a3
syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed
|
%!s(int64=8) %!d(string=hai) anos |
|
narmcnv.pas
|
c961c72c30
* tarmtypeconvnode.first_int_to_real should call the generic method in the parent class, if soft fpu code is generated, resolves #31350
|
%!s(int64=8) %!d(string=hai) anos |
|
narmcon.pas
|
4aa0ad6735
* use vmov.xx to load float constants if possible
|
%!s(int64=7) %!d(string=hai) anos |
|
narminl.pas
|
4686f61002
* keep track of the temp position separately from the offset in references,
|
%!s(int64=7) %!d(string=hai) anos |
|
narmld.pas
|
a277a5f8db
* Removed unused local vars.
|
%!s(int64=6) %!d(string=hai) anos |
|
narmmat.pas
|
71e71ad267
* fix currency division on non x86 32 bit targets
|
%!s(int64=7) %!d(string=hai) anos |
|
narmmem.pas
|
d6de2c03cb
* generic part of r26050 from the hlcgllvm branch: made tcgvecnode hlcg-safe
|
%!s(int64=10) %!d(string=hai) anos |
|
narmset.pas
|
07bd4ba517
* let all the case code generation work with tconstexprint instead of aint,
|
%!s(int64=6) %!d(string=hai) anos |
|
pp.lpi.template
|
1f032375c3
* improved template with help from Mattias Gaertner
|
%!s(int64=19) %!d(string=hai) anos |
|
raarm.pas
|
780e75bfac
o patch by Jeppe Johansen to fix mantis #17472:
|
%!s(int64=14) %!d(string=hai) anos |
|
raarmgas.pas
|
a186f48442
* cosmetics
|
%!s(int64=6) %!d(string=hai) anos |
|
rarmcon.inc
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
rarmdwa.inc
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
rarmnor.inc
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
rarmnum.inc
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
rarmrni.inc
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
rarmsri.inc
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
rarmsta.inc
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
rarmstd.inc
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
rarmsup.inc
|
387824c1ee
Added some APSR register bitmask definitions.
|
%!s(int64=10) %!d(string=hai) anos |
|
rgcpu.pas
|
4686f61002
* keep track of the temp position separately from the offset in references,
|
%!s(int64=7) %!d(string=hai) anos |
|
symcpu.pas
|
acf02ab64b
* when creating wrappers, add a prefix to parameter names to prevent them
|
%!s(int64=6) %!d(string=hai) anos |
yury
a277a5f8db
* Removed unused local vars.