nx64mat.pas 3.9 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl
  3. Generate x86-64 assembler for math nodes
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit nx64mat;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. node,nmat,nx86mat;
  22. type
  23. tx8664shlshrnode = class(tx86shlshrnode)
  24. procedure pass_generate_code;override;
  25. end;
  26. tx8664unaryminusnode = class(tx86unaryminusnode)
  27. end;
  28. tx8664notnode = class(tx86notnode)
  29. end;
  30. implementation
  31. uses
  32. globtype,constexp,
  33. aasmdata,defutil,
  34. pass_2,
  35. ncon,
  36. cgbase,cgutils,cgobj,hlcgobj;
  37. {*****************************************************************************
  38. TX8664SHLRSHRNODE
  39. *****************************************************************************}
  40. procedure tx8664shlshrnode.pass_generate_code;
  41. var
  42. op : topcg;
  43. opsize : tcgsize;
  44. mask : aint;
  45. begin
  46. secondpass(left);
  47. secondpass(right);
  48. { determine operator }
  49. if nodetype=shln then
  50. op:=OP_SHL
  51. else
  52. op:=OP_SHR;
  53. { special treatment of 32bit values for backwards compatibility }
  54. { mul optimizations require to keep the sign (FK) }
  55. if left.resultdef.size<=4 then
  56. begin
  57. if is_signed(left.resultdef) then
  58. opsize:=OS_S32
  59. else
  60. opsize:=OS_32;
  61. mask:=31;
  62. end
  63. else
  64. begin
  65. if is_signed(left.resultdef) then
  66. opsize:=OS_S64
  67. else
  68. opsize:=OS_64;
  69. mask:=63;
  70. end;
  71. { load left operators in a register }
  72. if not(left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
  73. { location_force_reg can be also used to change the size of a register }
  74. (left.location.size<>opsize) then
  75. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,cgsize_orddef(opsize),true);
  76. location_reset(location,LOC_REGISTER,opsize);
  77. location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
  78. { shifting by a constant directly coded: }
  79. if (right.nodetype=ordconstn) then
  80. cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,location.size,
  81. tordconstnode(right).value.uvalue and mask,left.location.register,location.register)
  82. else
  83. begin
  84. { load right operators in a register - this
  85. is done since most target cpu which will use this
  86. node do not support a shift count in a mem. location (cec)
  87. }
  88. if not(right.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
  89. { location_force_reg can be also used to change the size of a register }
  90. (right.location.size<>opsize) then
  91. hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,cgsize_orddef(opsize),true);
  92. cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,opsize,right.location.register,left.location.register,location.register);
  93. end;
  94. end;
  95. begin
  96. cunaryminusnode:=tx8664unaryminusnode;
  97. cmoddivnode:=tx86moddivnode;
  98. cshlshrnode:=tx8664shlshrnode;
  99. cnotnode:=tx8664notnode;
  100. end.