cpuinfo.pas 6.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232
  1. {
  2. Copyright (c) 2008 by the Free Pascal development team
  3. Basic Processor information for the AVR
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. {$if FPC_FULLVERSION>20700}
  17. bestrealrec = TDoubleRec;
  18. {$endif FPC_FULLVERSION>20700}
  19. ts32real = single;
  20. ts64real = double;
  21. ts80real = type extended;
  22. ts128real = type extended;
  23. ts64comp = comp;
  24. pbestreal=^bestreal;
  25. { possible supported processors for this target }
  26. tcputype =
  27. (cpu_none,
  28. cpu_avr1,
  29. cpu_avr2,
  30. cpu_avr25,
  31. cpu_avr3,
  32. cpu_avr31,
  33. cpu_avr35,
  34. cpu_avr4,
  35. cpu_avr5,
  36. cpu_avr51,
  37. cpu_avr6
  38. );
  39. tfputype =
  40. (fpu_none,
  41. fpu_soft,
  42. fp_libgcc
  43. );
  44. tcontrollertype =
  45. (ct_none,
  46. ct_avrsim,
  47. ct_atmega16,
  48. ct_atmega32,
  49. ct_atmega48,
  50. ct_atmega64,
  51. ct_atmega128
  52. );
  53. Const
  54. { Is there support for dealing with multiple microcontrollers available }
  55. { for this platform? }
  56. ControllerSupport = true;
  57. {# Size of native extended floating point type }
  58. extended_size = 12;
  59. {# Size of a multimedia register }
  60. mmreg_size = 16;
  61. { target cpu string (used by compiler options) }
  62. target_cpu_string = 'avr';
  63. { calling conventions supported by the code generator }
  64. supported_calling_conventions : tproccalloptions = [
  65. pocall_internproc,
  66. pocall_safecall,
  67. pocall_stdcall,
  68. { same as stdcall only different name mangling }
  69. pocall_cdecl,
  70. { same as stdcall only different name mangling }
  71. pocall_cppdecl,
  72. { same as stdcall but floating point numbers are handled like equal sized integers }
  73. pocall_softfloat
  74. ];
  75. cputypestr : array[tcputype] of string[5] = ('',
  76. 'AVR1',
  77. 'AVR2',
  78. 'AVR25',
  79. 'AVR3',
  80. 'AVR31',
  81. 'AVR35',
  82. 'AVR4',
  83. 'AVR5',
  84. 'AVR51',
  85. 'AVR6'
  86. );
  87. fputypestr : array[tfputype] of string[6] = (
  88. 'NONE',
  89. 'SOFT',
  90. 'LIBGCC'
  91. );
  92. { We know that there are fields after sramsize
  93. but we don't care about this warning }
  94. {$WARN 3177 OFF}
  95. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  96. ((
  97. controllertypestr:'';
  98. controllerunitstr:'';
  99. flashbase:0;
  100. flashsize:0;
  101. srambase:0;
  102. sramsize:0;
  103. eeprombase:0;
  104. eepromsize:0
  105. ),
  106. (
  107. controllertypestr:'AVRSIM';
  108. controllerunitstr:'AVRSIM';
  109. flashbase:0;
  110. flashsize:$20000;
  111. srambase:0;
  112. sramsize:4096;
  113. eeprombase:0;
  114. eepromsize:4096;
  115. ),
  116. (
  117. controllertypestr:'ATMEGA16';
  118. controllerunitstr:'ATMEGA16';
  119. flashbase:0;
  120. flashsize:$4000;
  121. srambase:0;
  122. sramsize:1024;
  123. eeprombase:0;
  124. eepromsize:512
  125. ),
  126. (
  127. controllertypestr:'ATMEGA32';
  128. controllerunitstr:'ATMEGA32';
  129. flashbase:0;
  130. flashsize:$8000;
  131. srambase:0;
  132. sramsize:1024;
  133. eeprombase:0;
  134. eepromsize:512
  135. ),
  136. (
  137. controllertypestr:'ATMEGA48';
  138. controllerunitstr:'ATMEGA48';
  139. flashbase:0;
  140. flashsize:$1000;
  141. srambase:0;
  142. sramsize:512;
  143. eeprombase:0;
  144. eepromsize:256;
  145. ),
  146. (
  147. controllertypestr:'ATMEGA64';
  148. controllerunitstr:'ATMEGA64';
  149. flashbase:0;
  150. flashsize:$10000;
  151. srambase:0;
  152. sramsize:4096;
  153. eeprombase:0;
  154. eepromsize:2048;
  155. ),
  156. (
  157. controllertypestr:'ATMEGA128';
  158. controllerunitstr:'ATMEGA128';
  159. flashbase:0;
  160. flashsize:$20000;
  161. srambase:0;
  162. sramsize:4096;
  163. eeprombase:0;
  164. eepromsize:4096;
  165. )
  166. );
  167. { Supported optimizations, only used for information }
  168. supported_optimizerswitches = genericlevel1optimizerswitches+
  169. genericlevel2optimizerswitches+
  170. genericlevel3optimizerswitches-
  171. { no need to write info about those }
  172. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  173. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  174. cs_opt_stackframe,cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath];
  175. level1optimizerswitches = genericlevel1optimizerswitches;
  176. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  177. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion];
  178. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
  179. level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
  180. type
  181. tcpuflags =
  182. (CPUAVR_HAS_JMP_CALL,
  183. CPUAVR_HAS_MOVW,
  184. CPUAVR_HAS_LPMX,
  185. CPUAVR_HAS_MUL,
  186. CPUAVR_HAS_RAMPZ,
  187. CPUAVR_HAS_ELPM,
  188. CPUAVR_HAS_ELPMX,
  189. CPUAVR_2_BYTE_PC,
  190. CPUAVR_3_BYTE_PC
  191. );
  192. const
  193. cpu_capabilities : array[tcputype] of set of tcpuflags =
  194. ( { cpu_none } [],
  195. { cpu_avr1 } [CPUAVR_2_BYTE_PC],
  196. { cpu_avr2 } [CPUAVR_2_BYTE_PC],
  197. { cpu_avr25 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC],
  198. { cpu_avr3 } [CPUAVR_HAS_JMP_CALL,CPUAVR_2_BYTE_PC],
  199. { cpu_avr31 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_2_BYTE_PC],
  200. { cpu_avr35 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC],
  201. { cpu_avr4 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC],
  202. { cpu_avr5 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC],
  203. { cpu_avr51 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_2_BYTE_PC],
  204. { cpu_avr6 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_3_BYTE_PC]
  205. );
  206. Implementation
  207. end.