ucontexth.inc 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132
  1. const
  2. {* Used by swapcontext(3). *}
  3. UCF_SWAPPED = $00000001;
  4. _MC_FPFMT_NODEV = $10000; {* device not present or configured *}
  5. _MC_FPFMT_387 = $10001;
  6. _MC_FPFMT_XMM = $10002;
  7. _MC_FPOWNED_NONE = $20000; {* FP state not used *}
  8. _MC_FPOWNED_FPU = $20001; {* FP state came from FPU *}
  9. _MC_FPOWNED_PCB = $20002; {* FP state came from PCB *}
  10. type
  11. plwpid_t = ^lwpid_t;
  12. lwpid_t = cint32;
  13. TLwPid = lwpid_t;
  14. PLwPid = ^lwpid_t;
  15. {$packrecords 16}
  16. TMCFPStateArray = record
  17. items: array[0..127] of cInt;
  18. end;
  19. {$packrecords C}
  20. {$if (defined(CPUi386) or defined(CPUX86_64))}
  21. mcontext_t = record
  22. {*
  23. * The first 20 fields must match the definition of
  24. * sigcontext. So that we can support sigcontext
  25. * and ucontext_t at the same time.
  26. *}
  27. mc_onstack: cInt; {* XXX - sigcontext compat. *}
  28. mc_gs: cInt; {* machine state (struct trapframe) *}
  29. mc_fs: cInt;
  30. mc_es: cInt;
  31. mc_ds: cInt;
  32. mc_edi: cInt;
  33. mc_esi: cInt;
  34. mc_ebp: cInt;
  35. mc_isp: cInt;
  36. mc_ebx: cInt;
  37. mc_edx: cInt;
  38. mc_ecx: cInt;
  39. mc_eax: cInt;
  40. mc_trapno: cInt;
  41. mc_err: cInt;
  42. mc_eip: cInt;
  43. mc_cs: cInt;
  44. mc_eflags: cInt;
  45. mc_esp: cInt;
  46. mc_ss: cInt;
  47. mc_len: cInt; {* sizeof(mcontext_t) *}
  48. mc_fpformat: cInt;
  49. mc_ownedfp: cInt;
  50. mc_spare1: array[0..0] of cInt; {* align next field to 16 bytes *}
  51. mc_fpstate: TMCFPStateArray;
  52. mc_spare2: array[0..7] of cInt;
  53. end;
  54. {$endif def x86}
  55. {$ifdef CPUAARCH64}
  56. gpregs = record
  57. gp_x: array[0..30] of cInt; { __register_t gp_x[30]; }
  58. gp_lr: cInt;
  59. gp_sp: cInt;
  60. gp_elr: cInt;
  61. gp_spsr: cuint32;
  62. gp_pad: cInt;
  63. end;
  64. fpregs = record
  65. fp_q: array[0..64] of cInt; { __uint128_t fp_q[32] }
  66. fp_sr: cuint32;
  67. fp_cr: cuint32;
  68. fp_flags: cInt;
  69. fp_pad: cInt;
  70. end;
  71. mcontext_t = record
  72. mc_gpregs: gpregs;
  73. mc_fpregs: fpregs;
  74. mc_flags: cint32;
  75. mc_pad: cint32;
  76. mc_spare: array[0..8] of cInt;
  77. end;
  78. {$endif cpuaarch64}
  79. {$ifdef CPUPOWERPC64}
  80. mcontext_t = record
  81. { version & flags }
  82. mc_vers : cint;
  83. mc_flags : cint;
  84. { saved sigstack flag and total size of this structure }
  85. mc_onstack : cint;
  86. mc_len : cint;
  87. { general-purpose CPU state (matches trapframe layout) }
  88. mc_gpr : array[0..31] of cuint64; { r0..r31 }
  89. mc_lr : cuint64; { link register }
  90. mc_cr : cuint64; { condition register }
  91. mc_xer : cuint64; { fixed-point exception }
  92. mc_ctr : cuint64; { count register }
  93. mc_srr0 : cuint64; { PC at signal (NIP) }
  94. mc_srr1 : cuint64; { MSR }
  95. { floating-point state }
  96. mc_fpscr : cdouble; { saved FPSCR as double }
  97. mc_fpreg : array[0..31] of cdouble; { FPR0..FPR31 }
  98. { Altivec / VSX state }
  99. { 32 vector registers, stored as 2x64-bit words each }
  100. mc_avec : array[0..(32*2)-1] of cuint64;
  101. { misc Altivec control: VSCR / VRSAVE (32-bit) }
  102. mc_av : array[0..1] of cuint32;
  103. end;
  104. {$endif}
  105. pucontext_t = ^ucontext_t;
  106. ucontext_t = record // required for kse threads
  107. {*
  108. * Keep the order of the first two fields. Also,
  109. * keep them the first two fields in the structure.
  110. * This way we can have a union with struct
  111. * sigcontext and ucontext_t. This allows us to
  112. * support them both at the same time.
  113. * note: the union is not defined, though.
  114. *}
  115. uc_sigmask: sigset_t;
  116. uc_mcontext: mcontext_t;
  117. uc_link: pucontext_t;
  118. uc_stack: stack_t;
  119. uc_flags: cInt;
  120. __spare__: array[0..3] of cInt;
  121. end;