m68k.inc 20 KB

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  1. {
  2. This file is part of the Free Pascal run time library.
  3. Copyright (c) 1999-2000 by Carl-Eric Codere,
  4. member of the Free Pascal development team.
  5. See the file COPYING.FPC, included in this distribution,
  6. for details about the copyright.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  10. **********************************************************************}
  11. {****************************************************************************
  12. m68k.inc : Processor dependent implementation of system unit
  13. For Motorola 680x0 Processor.
  14. *****************************************************************************}
  15. {****************************************************************************}
  16. { Credit where credit is due: }
  17. { -Some of the copy routines taken from the Atari dlib source code: }
  18. { Dale Schumacher (alias: Dalnefre') [email protected] }
  19. { 399 Beacon Ave. St. Paul, MN 55104,USA }
  20. { -Some of the routines taken from the freeware ATARI Sozobon C compiler }
  21. { 1988 by Sozobon, Limited. Author: Johann Ruegg (freeware) }
  22. { Thanks to all these people wherever they maybe today! }
  23. {****************************************************************************}
  24. {$IF DEFINED(FPU68881) OR DEFINED(FPUCOLDFIRE)}
  25. function GetFPCR: DWord; assembler; nostackframe;
  26. asm
  27. fmove.l fpcr,d0
  28. end;
  29. function GetFPSR: DWord; assembler; nostackframe;
  30. asm
  31. fmove.l fpsr, d0
  32. end;
  33. procedure SetFPCR(x: DWord); assembler; nostackframe;
  34. asm
  35. fmove.l x, fpcr
  36. end;
  37. procedure SetFPSR(x: DWord); assembler; nostackframe;
  38. asm
  39. fmove.l x, fpsr
  40. end;
  41. {$DEFINE FPC_SYSTEM_HAS_SYSRESETFPU}
  42. procedure SysResetFPU;
  43. begin
  44. SetFPCR(Default68KFPCR);
  45. SetFPSR(0);
  46. end;
  47. {$DEFINE FPC_SYSTEM_HAS_SYSINITFPU}
  48. procedure SysInitFPU;
  49. begin
  50. end;
  51. procedure fpc_cpuinit;
  52. begin
  53. if IsLibrary then
  54. begin
  55. Default68kFPCR:=GetFPCR;
  56. end;
  57. SysResetFPU;
  58. end;
  59. {$ELSE}
  60. procedure fpc_cpuinit;
  61. begin
  62. {$IFNDEF FPUNONE}
  63. SysResetFPU;
  64. if (not IsLibrary) then
  65. SysInitFPU;
  66. {$ENDIF}
  67. end;
  68. {$ENDIF}
  69. {$ifndef INTERNAL_BACKTRACE}
  70. {$define FPC_SYSTEM_HAS_GET_FRAME}
  71. function get_frame : pointer; assembler;nostackframe;
  72. asm
  73. move.l fp,d0
  74. end;
  75. {$endif not INTERNAL_BACKTRACE}
  76. {$define FPC_SYSTEM_HAS_GET_CALLER_ADDR}
  77. function get_caller_addr(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  78. asm
  79. move.l framebp,d0
  80. tst.l d0
  81. beq @Lnul_address
  82. move.l d0,a0
  83. move.l 4(a0),d0
  84. @Lnul_address:
  85. end;
  86. {$define FPC_SYSTEM_HAS_GET_CALLER_FRAME}
  87. function get_caller_frame(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  88. asm
  89. move.l framebp,d0
  90. tst.l d0
  91. beq @Lnul_frame
  92. move.l d0,a0
  93. move.l (a0),d0
  94. @Lnul_frame:
  95. end;
  96. {$define FPC_SYSTEM_HAS_SPTR}
  97. function Sptr : pointer; assembler;nostackframe;
  98. asm
  99. move.l sp,d0
  100. end;
  101. {$define FPC_SYSTEM_HAS_GET_PC_ADDR}
  102. function get_pc_addr : pointer;assembler;nostackframe;
  103. asm
  104. move.l (sp),d0
  105. end;
  106. {$define FPC_SYSTEM_HAS_FILLCHAR}
  107. procedure FillChar(var x; count : longint; value : byte); assembler; register; nostackframe;
  108. asm
  109. {$ifdef VER3_0}
  110. move.l x,a0
  111. move.l count,d0
  112. clr.l d1
  113. move.b value,d1
  114. {$endif VER3_0}
  115. { a0 is x, d0 is count, d1 is value }
  116. tst.l d0 { anything to fill at all? }
  117. ble @Lquit
  118. cmp.l #32,d0 { limits were tested against real hardware on various CPU }
  119. blt @LfillByte
  120. cmp.l #128,d0 { limits were tested against real hardware on various CPU }
  121. blt @LfillWord
  122. bra @LfillDWord
  123. {$ifndef CPUM68K_HAS_DBRA}
  124. @LfillByte:
  125. {$endif}
  126. @LfillByteLoop:
  127. move.b d1,(a0)+
  128. {$ifdef CPUM68K_HAS_DBRA}
  129. @LfillByte:
  130. dbra d0,@LfillByteLoop
  131. {$else}
  132. subq.l #1,d0
  133. bne @LfillByteLoop
  134. {$endif}
  135. rts
  136. @LfillWord:
  137. move.l d2,-(sp)
  138. move.l a0,d2
  139. btst #0,d2
  140. beq @Leven
  141. subq.l #1,d0
  142. move.b d1,(a0)+
  143. @Leven:
  144. move.b d1,d2 // copy value to upper byte
  145. {$ifdef CPUCOLDFIRE}
  146. lsl.l #8,d1
  147. {$else}
  148. lsl.w #8,d1
  149. {$endif}
  150. move.b d2,d1
  151. move.l d0,d2 // adjust d0 for leftover copy
  152. bclr #0,d2
  153. sub.l d2,d0
  154. lsr.l #1,d2
  155. {$ifdef CPUM68K_HAS_DBRA}
  156. subq.l #1,d2
  157. {$endif}
  158. @LfillWordLoop:
  159. move.w d1,(a0)+
  160. {$ifdef CPUM68K_HAS_DBRA}
  161. dbra d2,@LFillWordLoop
  162. {$else}
  163. subq.l #1,d2
  164. bne @LfillWordLoop
  165. {$endif}
  166. move.l (sp)+,d2
  167. tst.l d0
  168. bne @LfillByte
  169. rts
  170. @LfillDWord:
  171. move.l d2,-(sp)
  172. move.b d1,d2 // copy value to upper bytes
  173. {$ifdef CPUCOLDFIRE}
  174. lsl.l #8,d1
  175. {$else}
  176. lsl.w #8,d1
  177. {$endif}
  178. move.b d2,d1
  179. move.w d1,d2
  180. swap d1
  181. move.w d2,d1
  182. move.l a0,d2 // do initial byte and word fill, if the address is unaligned
  183. btst #0,d2
  184. beq @Ldeven
  185. subq.l #1,d0
  186. move.b d1,(a0)+
  187. @Ldeven:
  188. move.l a0,d2
  189. btst #1,d2
  190. beq @Ldquad
  191. subq.l #2,d0
  192. move.w d1,(a0)+
  193. @Ldquad:
  194. move.l d0,d2 // adjust d0 for leftover copy
  195. {$ifdef CPUCOLDFIRE}
  196. and.l #$fffffffc,d2
  197. {$else}
  198. and.b #$fc,d2
  199. {$endif}
  200. sub.l d2,d0
  201. lsr.l #2,d2
  202. bra @LfillLongLoopStart
  203. @LfillLongLoop:
  204. move.l d1,(a0)+
  205. move.l d1,(a0)+
  206. move.l d1,(a0)+
  207. move.l d1,(a0)+
  208. subq.l #4,d2
  209. @LfillLongLoopStart:
  210. cmp.l #4,d2
  211. bgt @LfillLongLoop
  212. {$ifdef CPUM68K_HAS_DBRA}
  213. subq.l #1,d2
  214. {$endif}
  215. @LfillDWordLoop:
  216. move.l d1,(a0)+
  217. {$ifdef CPUM68K_HAS_DBRA}
  218. dbra d2,@LFillDWordLoop
  219. {$else}
  220. subq.l #1,d2
  221. bne @LfillDWordLoop
  222. {$endif}
  223. move.l (sp)+,d2
  224. tst.l d0
  225. bne @LfillByte
  226. @Lquit:
  227. end;
  228. {$ifdef dummy}
  229. { procedure strcopy(dstr,sstr : pointer;len : longint);[public,alias: 'STRCOPY'];}
  230. procedure strcopy; assembler;[public,alias: 'FPC_STRCOPY'];
  231. {---------------------------------------------------}
  232. { Low-level routine to copy a string to another }
  233. { string with maximum length. Never call directly! }
  234. { On Entry: }
  235. { a1.l = string to copy to }
  236. { a0.l = source string }
  237. { d0.l = maximum length of copy }
  238. { registers destroyed: a0,a1,d0,d1 }
  239. {---------------------------------------------------}
  240. asm
  241. { move.l sstr,a0
  242. move.l dstr,a1
  243. move.l len,d1 }
  244. move.l d0,d1
  245. move.b (a0)+,d0 { Get source length }
  246. and.w #$ff,d0
  247. cmp.w d1,d0 { This is a signed comparison! }
  248. ble @LM4
  249. move.b d1,d0 { If longer than maximum size of target, cut
  250. source length }
  251. @LM4:
  252. andi.l #$ff,d0 { zero extend d0-byte }
  253. move.l d0,d1 { save length to copy }
  254. move.b d0,(a1)+ { save new length }
  255. { Check if copying length is zero - if so then }
  256. { exit without copying anything. }
  257. tst.b d1
  258. beq @Lend
  259. bra @LMSTRCOPY55
  260. @LMSTRCOPY56: { 68010 Fast loop mode }
  261. move.b (a0)+,(a1)+
  262. @LMSTRCOPY55:
  263. {$ifndef CPUM68K_HAS_DBRA}
  264. sub.l #1,d1
  265. bpl @LMSTRCOPY56
  266. {$else CPUM68K_HAS_DBRA}
  267. dbra d1,@LMSTRCOPY56
  268. {$endif CPUM68K_HAS_DBRA}
  269. @Lend:
  270. end;
  271. { Concatenate Strings }
  272. { PARAMETERS ARE REVERSED COMPARED TO NORMAL! }
  273. { therefore online assembler may not parse the params as normal }
  274. procedure strconcat(s1,s2 : pointer);[public,alias: 'STRCONCAT'];
  275. begin
  276. asm
  277. move.b #255,d0
  278. move.l s1,a0 { a0 = destination }
  279. move.l s2,a1 { a1 = source }
  280. sub.b (a0),d0 { copyl:= 255 -length(s1) }
  281. move.b (a1),d6
  282. and.w #$ff,d0 { Sign flags are checked! }
  283. and.w #$ff,d6
  284. cmp.w d6,d0 { if copyl > length(s2) then }
  285. ble @Lcontinue
  286. move.b (a1),d0 { copyl:=length(s2) }
  287. @Lcontinue:
  288. move.b (a0),d6
  289. and.l #$ff,d6
  290. lea 1(a0,d6),a0 { s1[length(s1)+1] }
  291. add.l #1,a1 { s2[1] }
  292. move.b d0,d6
  293. { Check if copying length is zero - if so then }
  294. { exit without copying anything. }
  295. tst.b d6
  296. beq @Lend
  297. bra @ALoop
  298. @Loop:
  299. move.b (a1)+,(a0)+ { s1[i] := s2[i]; }
  300. @ALoop:
  301. {$ifndef CPUM68K_HAS_DBRA}
  302. sub.l #1,d6
  303. bpl @Loop
  304. {$else CPUM68K_HAS_DBRA}
  305. dbra d6,@Loop
  306. {$endif CPUM68K_HAS_DBRA}
  307. move.l s1,a0
  308. add.b d0,(a0) { change to new string length }
  309. @Lend:
  310. end ['d0','d1','a0','a1','d6'];
  311. end;
  312. { Compares strings }
  313. { DO NOT CALL directly. }
  314. { a0 = pointer to first string to compare }
  315. { a1 = pointer to second string to compare }
  316. { ALL FLAGS are set appropriately. }
  317. { ZF = strings are equal }
  318. { REGISTERS DESTROYED: a0, a1, d0, d1, d6 }
  319. procedure strcmp; assembler;[public,alias:'FPC_STRCMP'];
  320. asm
  321. move.b (a0)+,d0 { Get length of first string }
  322. move.b (a1)+,d6 { Get length of 2nd string }
  323. move.b d6,d1 { Save length of string for final compare }
  324. cmp.b d0,d6 { Get shortest string length }
  325. ble @LSTRCONCAT1
  326. move.b d0,d6 { Set length to shortest string }
  327. @LSTRCONCAT1:
  328. tst.b d6 { Both strings have a length of zero, exit }
  329. beq @LSTRCONCAT2
  330. andi.l #$ff,d6
  331. subq.l #1,d6 { subtract first attempt }
  332. { if value is -1 then don't loop and just compare lengths of }
  333. { both strings before exiting. }
  334. bmi @LSTRCONCAT2
  335. or.l d0,d0 { Make sure to set Zerfo flag to 0 }
  336. @LSTRCONCAT5:
  337. { Workaroung for GAS v.134 bug }
  338. { old: cmp.b (a1)+,(a0)+ }
  339. cmpm.b (a1)+,(a0)+
  340. @LSTRCONCAT4:
  341. dbne d6,@LSTRCONCAT5 { Repeat until not equal }
  342. bne @LSTRCONCAT3
  343. @LSTRCONCAT2:
  344. { If length of both string are equal }
  345. { Then set zero flag }
  346. cmp.b d1,d0 { Compare length - set flag if equal length strings }
  347. @LSTRCONCAT3:
  348. end;
  349. {$endif dummy}
  350. {$define FPC_SYSTEM_HAS_MOVE}
  351. procedure move(const source;var dest;count : longint); assembler;
  352. { base pointer+8 = source }
  353. { base pointer+12 = destination }
  354. { base pointer+16 = number of bytes to move}
  355. asm
  356. move.l count, d0 { number of bytes }
  357. ble @LMOVE5 { anything to copy at all? }
  358. move.l dest, a1 { destination }
  359. move.l source, a0 { source }
  360. {$ifdef CPUM68K_HAS_DBRA}
  361. cmpi.l #65535, d0 { check, if this is a word move }
  362. ble @LMEMSET00 { use fast dbra mode 68010+ }
  363. {$endif CPUM68K_HAS_DBRA}
  364. cmp.l a0,a1 { check copy direction }
  365. bls @LMOVE3
  366. add.l d0,a0 { move pointers to end }
  367. add.l d0,a1
  368. @LMOVE1:
  369. move.b -(a0),-(a1) { (s < d) copy loop }
  370. subq.l #1,d0
  371. bne @LMOVE1
  372. bra @LMOVE5
  373. @LMOVE3:
  374. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  375. subq.l #1,d0
  376. bne @LMOVE3
  377. bra @LMOVE5
  378. {$ifdef CPUM68K_HAS_DBRA}
  379. @LMEMSET00: { use fast loop mode 68010+ }
  380. cmp.l a0,a1 { check copy direction }
  381. bls @LMOVE04
  382. add.l d0,a0 { move pointers to end }
  383. add.l d0,a1
  384. bra @LMOVE02
  385. @LMOVE01:
  386. move.b -(a0),-(a1) { (s < d) copy loop }
  387. @LMOVE02:
  388. dbra d0,@LMOVE01
  389. bra @LMOVE5
  390. @LMOVE03:
  391. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  392. @LMOVE04:
  393. dbra d0,@LMOVE03
  394. {$endif CPUM68K_HAS_DBRA}
  395. { end fast loop mode }
  396. @LMOVE5:
  397. end;
  398. {$ifdef CPUM68K_HAS_UNALIGNED}
  399. {$define FPC_SYSTEM_HAS_FILLWORD}
  400. procedure FillWord(var x; count : longint; value : word); assembler;
  401. asm
  402. move.l x, a0 { destination }
  403. move.w value, d1 { fill data }
  404. move.l count, d0 { number of bytes to fill }
  405. ble @LMEMSET3 { anything to fill at all? }
  406. bra @LMEMSET21
  407. @LMEMSET11:
  408. move.w d1,(a0)+
  409. @LMEMSET21:
  410. subq.l #1,d0
  411. bpl @LMEMSET11
  412. @LMEMSET3:
  413. end;
  414. {$endif}
  415. {$IFNDEF FPC_SYSTEM_HAS_INTERLOCKEDFUNCS}
  416. {$IFNDEF CPUM68K_HAS_CAS}
  417. var
  418. spinLock: byte;
  419. procedure getSpinLock; assembler; nostackframe;
  420. asm
  421. {$IFDEF CPUM68K_HAS_TAS}
  422. lea.l spinlock,a0
  423. @loop:
  424. tas (a0)
  425. bne @loop
  426. {$ENDIF}
  427. end;
  428. procedure releaseSpinLock; assembler; nostackframe;
  429. asm
  430. moveq.l #0,d0
  431. move.b d0,spinlock
  432. end;
  433. {$ENDIF}
  434. function InterLockedDecrement (var Target: longint) : longint;
  435. {$IFDEF CPUM68K_HAS_CAS}
  436. register; assembler;
  437. asm
  438. move.l (a0), d0
  439. @loop:
  440. move.l d0, d1
  441. subq.l #1, d1
  442. cas.l d0, d1, (a0)
  443. bne @loop
  444. move.l d1, d0
  445. end;
  446. {$ELSE}
  447. begin
  448. getSpinLock;
  449. Dec(Target);
  450. Result := Target;
  451. releaseSpinLock;
  452. end;
  453. {$ENDIF}
  454. function InterLockedIncrement (var Target: longint) : longint;
  455. {$IFDEF CPUM68K_HAS_CAS}
  456. register; assembler;
  457. asm
  458. move.l (a0), d0
  459. @loop:
  460. move.l d0, d1
  461. addq.l #1, d1
  462. cas.l d0, d1, (a0)
  463. bne @loop
  464. move.l d1, d0
  465. end;
  466. {$ELSE}
  467. begin
  468. getSpinLock;
  469. Inc(Target);
  470. Result := Target;
  471. releaseSpinLock;
  472. end;
  473. {$ENDIF}
  474. function InterLockedExchange (var Target: longint;Source : longint) : longint;
  475. {$IFDEF CPUM68K_HAS_CAS}
  476. register; assembler;
  477. asm
  478. move.l Source, d1
  479. move.l (a0), d0
  480. @loop:
  481. cas.l d0, d1, (a0)
  482. bne @loop
  483. end;
  484. {$ELSE}
  485. begin
  486. getSpinLock;
  487. Result := Target;
  488. Target := Source;
  489. releaseSpinLock;
  490. end;
  491. {$ENDIF}
  492. function InterLockedExchangeAdd (var Target: longint;Source : longint) : longint;
  493. {$IFDEF CPUM68K_HAS_CAS}
  494. register; assembler;
  495. asm
  496. move.l Source, a1
  497. move.l (a0), d0
  498. @loop:
  499. move.l a1, d1
  500. add.l d0, d1
  501. cas.l d0, d1, (a0)
  502. bne @loop
  503. end;
  504. {$ELSE}
  505. begin
  506. getSpinLock;
  507. Result := Target;
  508. Target := Target + Source;
  509. releaseSpinLock;
  510. end;
  511. {$ENDIF}
  512. function InterlockedCompareExchange(var Target: longint; NewValue: longint; Comperand: longint): longint;
  513. {$IFDEF CPUM68K_HAS_CAS}
  514. register; assembler;
  515. asm
  516. // Target = a0, NewValue = d0, Comperand = d1
  517. exg.l d0, d1
  518. cas.l d0, d1, (a0)
  519. end;
  520. {$ELSE}
  521. begin
  522. getSpinLock;
  523. Result := Target;
  524. if Target = Comperand then
  525. Target := NewValue;
  526. releaseSpinLock;
  527. end;
  528. {$ENDIF}
  529. {$ENDIF FPC_SYSTEM_HAS_INTERLOCKEDFUNCS}
  530. {$ifndef FPC_SYSTEM_HAS_TEST68K}
  531. procedure Test68k(var CPU: byte; var FPU: byte);
  532. begin
  533. {$warning Implement me!}
  534. CPU:=0;
  535. FPU:=0;
  536. end;
  537. {$endif}
  538. {$ifndef FPC_SYSTEM_HAS_SAR_QWORD}
  539. {$define FPC_SYSTEM_HAS_SAR_QWORD}
  540. function fpc_SarInt64(Const AValue : Int64;const Shift : Byte): Int64; [Public,Alias:'FPC_SARINT64']; compilerproc; assembler; nostackframe;
  541. asm
  542. // d0 = shift
  543. lea.l 4(sp),a0
  544. move.l d2,-(sp)
  545. move.l d0,d2
  546. {$ifndef CPUCOLDFIRE}
  547. and.w #63,d2
  548. cmp.w #32,d2
  549. {$else}
  550. and.l #63,d2
  551. cmp.l #32,d2
  552. {$endif}
  553. bge.s @longshift
  554. move.l (a0)+,d0
  555. move.l (a0),d1
  556. {$ifdef CPUM68K_HAS_ROLROR}
  557. cmp.w #1,d2
  558. beq.s @oneshift
  559. {$endif}
  560. {$ifdef CPU68000}
  561. cmp.w #16,d2
  562. beq.s @sixteenshift
  563. {$endif}
  564. move.l d3,a0
  565. move.l d4,a1
  566. move.l d0,d3
  567. moveq.l #32,d4
  568. {$ifndef CPUCOLDFIRE}
  569. sub.w d2,d4
  570. {$else}
  571. sub.l d2,d4
  572. {$endif}
  573. asr.l d2,d0
  574. lsl.l d4,d3
  575. lsr.l d2,d1
  576. or.l d3,d1
  577. move.l a0,d3
  578. move.l a1,d4
  579. bra.s @quit
  580. {$ifdef CPU68000}
  581. @sixteenshift:
  582. move.w d0,d1
  583. swap d1
  584. swap d0
  585. ext.l d0
  586. bra.s @quit
  587. {$endif}
  588. {$ifdef CPUM68K_HAS_ROLROR}
  589. @oneshift:
  590. asr.l #1,d0
  591. roxr.l #1,d1
  592. bra.s @quit
  593. {$endif}
  594. @longshift:
  595. move.l (a0),d0
  596. move.l d0,d1
  597. smi d0
  598. {$if defined(CPU68020) or defined(CPUCOLDFIRE)}
  599. extb.l d0
  600. {$else}
  601. ext.w d0
  602. ext.l d0
  603. {$endif}
  604. {$ifndef CPUCOLDFIRE}
  605. sub.w #32,d2
  606. {$else}
  607. sub.l #32,d2
  608. {$endif}
  609. asr.l d2,d1
  610. @quit:
  611. move.l (sp)+,d2
  612. end;
  613. {$endif}
  614. {$if defined(CPUM68K_HAS_BYTEREV) or defined(CPUM68K_HAS_ROLROR)}
  615. { Disabled for now, because not all cases below were tested. (KB) }
  616. {.$define FPC_SYSTEM_HAS_SWAPENDIAN}
  617. {$endif}
  618. {$if defined(FPC_SYSTEM_HAS_SWAPENDIAN)}
  619. function SwapEndian(const AValue: SmallInt): SmallInt; assembler; nostackframe;
  620. asm
  621. {$if defined(CPUM68K_HAS_ROLROR)}
  622. move.w avalue, d0
  623. ror.w #8, d0
  624. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  625. move.w avalue, d0
  626. byterev d0
  627. swap d0
  628. {$else}
  629. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  630. clr.l d0
  631. move.w avalue, d0
  632. move.w d0, d1
  633. lsr.l #8, d0
  634. lsl.l #8, d1
  635. or.l d1, d0
  636. {$endif}
  637. end;
  638. function SwapEndian(const AValue: Word): Word; assembler; nostackframe;
  639. asm
  640. {$if defined(CPUM68K_HAS_ROLROR)}
  641. move.w avalue, d0
  642. ror.w #8, d0
  643. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  644. move.w avalue, d0
  645. byterev d0
  646. swap d0
  647. {$else}
  648. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  649. clr.l d0
  650. move.w avalue, d0
  651. move.w d0, d1
  652. lsr.l #8, d0
  653. lsl.l #8, d1
  654. or.l d1, d0
  655. {$endif}
  656. end;
  657. function SwapEndian(const AValue: LongInt): LongInt; assembler; nostackframe;
  658. asm
  659. {$if defined(CPUM68K_HAS_ROLROR)}
  660. move.l avalue, d0
  661. ror.w #8, d0
  662. swap d0
  663. ror.w #8, d0
  664. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  665. move.l avalue, d0
  666. byterev d0
  667. {$else}
  668. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  669. move.l avalue, d0
  670. move.l d0, d1
  671. andi.l #$ff00ff00, d0
  672. andi.l #$00ff00ff, d1
  673. lsr.l #8, d0
  674. lsl.l #8, d1
  675. or.l d1, d0
  676. swap d0
  677. {$endif}
  678. end;
  679. function SwapEndian(const AValue: DWord): DWord; assembler; nostackframe;
  680. asm
  681. {$if defined(CPUM68K_HAS_ROLROR)}
  682. move.l avalue, d0
  683. ror.w #8, d0
  684. swap d0
  685. ror.w #8, d0
  686. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  687. move.l avalue, d0
  688. byterev d0
  689. {$else}
  690. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  691. move.l avalue, d0
  692. move.l d0, d1
  693. andi.l #$ff00ff00, d0
  694. andi.l #$00ff00ff, d1
  695. lsr.l #8, d0
  696. lsl.l #8, d1
  697. or.l d1, d0
  698. swap d0
  699. {$endif}
  700. end;
  701. function SwapEndian(const AValue: Int64): Int64; assembler; nostackframe;
  702. asm
  703. {$if defined(CPUM68K_HAS_ROLROR)}
  704. move.l avalue+4, d0
  705. ror.w #8, d0
  706. swap d0
  707. ror.w #8, d0
  708. move.l avalue, d1
  709. ror.w #8, d1
  710. swap d1
  711. ror.w #8, d1
  712. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  713. move.l avalue+4, d0
  714. move.l avalue, d1
  715. byterev d0
  716. byterev d1
  717. {$else}
  718. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  719. move.l d2, -(sp)
  720. move.l avalue+4, d0
  721. move.l d0, d1
  722. andi.l #$ff00ff00, d0
  723. andi.l #$00ff00ff, d1
  724. lsr.l #8, d0
  725. lsl.l #8, d1
  726. or.l d1, d0
  727. swap d0
  728. move.l avalue, d1
  729. move.l d1, d2
  730. andi.l #$ff00ff00, d1
  731. andi.l #$00ff00ff, d2
  732. lsr.l #8, d1
  733. lsl.l #8, d2
  734. or.l d2, d1
  735. swap d1
  736. move.l (sp)+, d2
  737. {$endif}
  738. end;
  739. function SwapEndian(const AValue: QWord): QWord; assembler; nostackframe;
  740. asm
  741. {$if defined(CPUM68K_HAS_ROLROR)}
  742. move.l avalue+4, d0
  743. ror.w #8, d0
  744. swap d0
  745. ror.w #8, d0
  746. move.l avalue, d1
  747. ror.w #8, d1
  748. swap d1
  749. ror.w #8, d1
  750. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  751. move.l avalue+4, d0
  752. move.l avalue, d1
  753. byterev d0
  754. byterev d1
  755. {$else}
  756. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  757. move.l d2, -(sp)
  758. move.l avalue+4, d0
  759. move.l d0, d1
  760. andi.l #$ff00ff00, d0
  761. andi.l #$00ff00ff, d1
  762. lsr.l #8, d0
  763. lsl.l #8, d1
  764. or.l d1, d0
  765. swap d0
  766. move.l avalue, d1
  767. move.l d1, d2
  768. andi.l #$ff00ff00, d1
  769. andi.l #$00ff00ff, d2
  770. lsr.l #8, d1
  771. lsl.l #8, d2
  772. or.l d2, d1
  773. swap d1
  774. move.l (sp)+, d2
  775. {$endif}
  776. end;
  777. {$endif FPC_SYSTEM_HAS_SWAPENDIAN}
  778. procedure fpc_cpucodeinit;
  779. begin
  780. Test68k(Test68000,Test68881);
  781. end;