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aasmcpu.pas
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e047e7db91
+ RiscV: initial support of pic generation
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4 years ago |
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agrvgas.pas
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0b49fba637
+ more RiscV extensions
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11 months ago |
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aoptcpurv.pas
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e8144afb6b
* draft of improving Addi0Op2Op
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10 months ago |
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cgrv.pas
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0b49fba637
+ more RiscV extensions
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11 months ago |
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cpubase.pas
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27a0da5a20
* typo corrected
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10 months ago |
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hlcgrv.pas
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637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
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5 years ago |
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itcpugas.pas
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6ef37d999a
+ Risc-V: instructions of B extension
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1 year ago |
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nrvadd.pas
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4888442fb4
* RiscV: more reliable use_fma
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10 months ago |
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nrvcnv.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
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nrvcon.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
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nrvinl.pas
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8dcf4e62b7
* FCVT.W.D returns only a 32 bit int
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1 year ago |
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nrvset.pas
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ccae78f97a
+ RiscV64: apply OptPass1OP also to addiw
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11 months ago |
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rarv.pas
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d1fb44044f
* unified RiscV32 and RiscV64 GAS readers
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4 years ago |
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rarvgas.pas
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a05aa25aad
* Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738
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3 years ago |
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rgcpu.pas
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92b0ea7d02
Add explicit smallint typecast to first marameter of SarSmallint call to avoid range check errors
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5 years ago |
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rvreg.dat
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ae457a18ad
* unified Risc-V 32 and 64 register data file
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3 years ago |
florian
e8144afb6b
* draft of improving Addi0Op2Op