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aopt386.pas
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ba5297be37
* support disabling the i386 peephole optimizer with -Oonopeephole
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11 lat temu |
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cgcpu.pas
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31edfdc05f
* i386: push references with size OS_F64 using less instructions.
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11 lat temu |
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cpubase.inc
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bfbb0c5b9d
* optimize mov/lea
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12 lat temu |
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cpuelf.pas
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74581a07af
AROS: assembler fixes
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11 lat temu |
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cpuinfo.pas
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d88d644925
+ support for FMA intrinsic: if there is no hardware support, the compiler throws an error.
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11 lat temu |
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cpunode.pas
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4a79481c51
* isolated segment-related functionality of tabsolutevarsym into i386/i8086-
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11 lat temu |
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cpupara.pas
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4ee15b84da
AROS: syscall (library call) support for based on the Amiga/68k and MorphOS/PPC versions
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11 lat temu |
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cpupi.pas
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b1dc518ac4
* removed systems_need_16_byte_stack_alignment and use target_info.stackalign instead
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13 lat temu |
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cputarg.pas
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4431ba2c08
merged/updated AROS/i386 target to trunk from AROS branch, to support Marcus Sackrow's work on AROS support which will hopefully benefit all Amiga-like targets (classic, MorphOS) on the long run. Compiler only, RTL comes in the next run.
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11 lat temu |
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csopt386.pas
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4d5119bf1c
* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables
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12 lat temu |
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daopt386.pas
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4d5119bf1c
* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables
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12 lat temu |
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hlcgcpu.pas
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26b53607f8
+ added method reference_reset_base with support for different pointer types to
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11 lat temu |
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i386att.inc
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dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
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11 lat temu |
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i386atts.inc
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dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
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11 lat temu |
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i386int.inc
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dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
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11 lat temu |
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i386nop.inc
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842e027a9f
+ prove of concept how FMA4 could be supported in inline assembler
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11 lat temu |
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i386op.inc
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dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
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11 lat temu |
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i386prop.inc
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dc628b8969
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
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11 lat temu |
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i386tab.inc
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842e027a9f
+ prove of concept how FMA4 could be supported in inline assembler
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11 lat temu |
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n386add.pas
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07ad2a04ac
* fix warnings when compiling the compiler with DFA optimizer enabled on i386
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11 lat temu |
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n386cal.pas
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4ee15b84da
AROS: syscall (library call) support for based on the Amiga/68k and MorphOS/PPC versions
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11 lat temu |
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n386flw.pas
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5479b6e722
* Provide initialization of all variables, fixes cycling with OPT="-dTEST_WIN32_SEH -OoDFA".
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11 lat temu |
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n386inl.pas
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66e82f1655
+ i386: generate optimized code for 64-bit arithmetic shifts by constant amount. Shifts by 63 and by less than 32 take just two instructions, shifts by 32..62 bits are done with 3 instructions.
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12 lat temu |
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n386ld.pas
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4a79481c51
* isolated segment-related functionality of tabsolutevarsym into i386/i8086-
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11 lat temu |
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n386mat.pas
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5356f17fa5
* i386: switch the div/mod node to shared code, leaving in place the specific optimization for division by power of 2.
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11 lat temu |
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n386mem.pas
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338c064beb
* moved x86-specific tpointerdef functionality to architecture-specific
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11 lat temu |
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n386set.pas
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d0db391d7c
* cleanup of unused units
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12 lat temu |
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popt386.pas
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2ee0c8de45
* i386: For integer comparisons with zero, emit "test $-1,%reg" instead of "test %reg,%reg". It is more spilling-friendly, because it transforms into "test $-1,spilltemp" and does not require a register.
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11 lat temu |
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r386ari.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386att.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386con.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386dwrf.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386int.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386iri.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386nasm.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386nor.inc
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283ff05127
* merged avx support in inline assembler developed by Torsten Grundke
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13 lat temu |
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r386nri.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386num.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386ot.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386rni.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386sri.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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r386stab.inc
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283ff05127
* merged avx support in inline assembler developed by Torsten Grundke
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13 lat temu |
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r386std.inc
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5af873ee5b
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
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12 lat temu |
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ra386att.pas
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757ed4e8d3
* standard assembler reader for i386
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20 lat temu |
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ra386int.pas
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6c6bf452ca
* Fixed level 2 comment warnings.
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17 lat temu |
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rgcpu.pas
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b7fe6797bf
Merged revisions 2921-2922,2925 via svnmerge from
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19 lat temu |
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rropt386.pas
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4d5119bf1c
* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables
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12 lat temu |
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symcpu.pas
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4ee15b84da
AROS: syscall (library call) support for based on the Amiga/68k and MorphOS/PPC versions
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11 lat temu |
sergei
5479b6e722
* Provide initialization of all variables, fixes cycling with OPT="-dTEST_WIN32_SEH -OoDFA".