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aasmcpu.pas
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8445381929
* merged ait_set and ait_thumb_set into a single tai class
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%!s(int64=10) %!d(string=hai) anos |
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agavrgas.pas
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38a72f2ddb
* renamed arm->avr to match the cpu
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%!s(int64=10) %!d(string=hai) anos |
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aoptcpu.pas
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db63693b7e
* tai returned by GetNextInstructionUsingReg must be checked if it is really an instruction
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%!s(int64=10) %!d(string=hai) anos |
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aoptcpub.pas
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e33550b67d
Added support for X,Y,and Z register aliases plus low/high forms, and post-incrementation in AVR assembler reader.
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%!s(int64=11) %!d(string=hai) anos |
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aoptcpud.pas
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bc73f9021c
Merged revisions 5891-10167,10169-10180 via svnmerge from
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%!s(int64=17) %!d(string=hai) anos |
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avrreg.dat
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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cgcpu.pas
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63bf17440c
* use volatile registers first
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%!s(int64=10) %!d(string=hai) anos |
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cpubase.pas
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2b9c0ef3b4
- jmp_instructions shouldn't include call/ret instructions
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%!s(int64=10) %!d(string=hai) anos |
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cpuinfo.pas
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dfd4d3656b
+ avrsim controller target requiring a special avr simulator with a certain memory location handling, see avrsim.pp controller helper unit for what it is needed
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%!s(int64=10) %!d(string=hai) anos |
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cpunode.pas
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b57c95043f
+ support overriding tdef/tsym methods with target-specific functionality:
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%!s(int64=11) %!d(string=hai) anos |
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cpupara.pas
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67b8aceaee
* synchronized with privatetrunk till r30095
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%!s(int64=10) %!d(string=hai) anos |
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cpupi.pas
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eeb15fc445
* Added virtual method tprocinfo.postprocess_code and moved target-specific processing from base class into target-specific descendant classes (ARM and AVR, other targets still to do).
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%!s(int64=11) %!d(string=hai) anos |
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cputarg.pas
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0e13d07a31
+ more avr code
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%!s(int64=17) %!d(string=hai) anos |
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hlcgcpu.pas
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b745dcc64c
* moved g_external_wrapper() to the hlcg, and also g_intf_wrapper() because
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%!s(int64=11) %!d(string=hai) anos |
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itcpugas.pas
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8d960cb608
+ implementation of shifting operations for avr
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%!s(int64=14) %!d(string=hai) anos |
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navradd.pas
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7fe4b13248
Fix broken peephole optimization that was testing the wrong register for modifications.
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%!s(int64=10) %!d(string=hai) anos |
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navrcnv.pas
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f419966f06
+ generic second_int_to_bool, depends on OP_OR setting flags
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%!s(int64=14) %!d(string=hai) anos |
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navrmat.pas
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e7ac66a6c4
* removed nested comments
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%!s(int64=11) %!d(string=hai) anos |
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raavr.pas
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0e13d07a31
+ more avr code
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%!s(int64=17) %!d(string=hai) anos |
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raavrgas.pas
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7e3abd4b38
* fixed warning about signed integer to pointer conversion
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%!s(int64=11) %!d(string=hai) anos |
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ravrcon.inc
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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ravrdwa.inc
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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ravrnor.inc
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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ravrnum.inc
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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ravrrni.inc
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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ravrsri.inc
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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ravrsta.inc
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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ravrstd.inc
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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ravrsup.inc
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4dee21c60e
+ NR_DEFAULTFLAGS and RS_DEFAULTFLAGS for all CPUs with flags added
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%!s(int64=13) %!d(string=hai) anos |
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rgcpu.pas
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5ef93e85b8
+ added extra "orgsupreg" parameter to do_spill_read/do_spill_written/
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%!s(int64=12) %!d(string=hai) anos |
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symcpu.pas
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02495c17bd
Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym".
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%!s(int64=11) %!d(string=hai) anos |
florian
63bf17440c
* use volatile registers first