| .. |
|
aasmcpu.pas
|
4056194e7c
* don't ignore by accident the next instruction after a newly inserted constant pool
|
%!s(int64=12) %!d(string=hai) anos |
|
agarmgas.pas
|
07762e5c25
+ proper assembler command line parameters for arm thumb
|
%!s(int64=12) %!d(string=hai) anos |
|
aoptcpu.pas
|
8c32802fcf
Added LdrbAnd2Ldrb Peephole optimizer for arm
|
%!s(int64=12) %!d(string=hai) anos |
|
aoptcpub.pas
|
7e5b8584cf
* set MaxOps to 4 for the optimizer because fpc generates now mla instructions
|
%!s(int64=13) %!d(string=hai) anos |
|
aoptcpuc.pas
|
790a4fe2d3
* log and id tags removed
|
%!s(int64=20) %!d(string=hai) anos |
|
aoptcpud.pas
|
790a4fe2d3
* log and id tags removed
|
%!s(int64=20) %!d(string=hai) anos |
|
armatt.inc
|
ac4a6accd3
+ SVC instruction
|
%!s(int64=12) %!d(string=hai) anos |
|
armatts.inc
|
ac4a6accd3
+ SVC instruction
|
%!s(int64=12) %!d(string=hai) anos |
|
armins.dat
|
ac4a6accd3
+ SVC instruction
|
%!s(int64=12) %!d(string=hai) anos |
|
armnop.inc
|
666332385d
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
|
%!s(int64=13) %!d(string=hai) anos |
|
armop.inc
|
ac4a6accd3
+ SVC instruction
|
%!s(int64=12) %!d(string=hai) anos |
|
armreg.dat
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
armtab.inc
|
666332385d
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
|
%!s(int64=13) %!d(string=hai) anos |
|
cgcpu.pas
|
0bb8d24e24
Add some immediate forms of shift instructions to tcgthumb.a_op_const_reg
|
%!s(int64=12) %!d(string=hai) anos |
|
cpubase.pas
|
086ae4b999
Merge r22905 and r22906
|
%!s(int64=12) %!d(string=hai) anos |
|
cpuelf.pas
|
32ffddaad8
+ ELF linker back-ends for ARM and MIPS.
|
%!s(int64=12) %!d(string=hai) anos |
|
cpuinfo.pas
|
0e9b8adb7a
patch by Michael Ring:
|
%!s(int64=12) %!d(string=hai) anos |
|
cpunode.pas
|
638d0d49c0
+ take advantage of the mla instruction when calculating array offsets
|
%!s(int64=13) %!d(string=hai) anos |
|
cpupara.pas
|
79334242a2
* arm thumb uses always the stack pointer as frame pointer
|
%!s(int64=12) %!d(string=hai) anos |
|
cpupi.pas
|
7ba197a221
* fix stack parameter handling for arm thumb
|
%!s(int64=12) %!d(string=hai) anos |
|
cputarg.pas
|
d26f0552a0
* Sync with trunk r23404.
|
%!s(int64=12) %!d(string=hai) anos |
|
hlcgcpu.pas
|
72e9cfee24
* create/destroy also the high level code generator for all architectures,
|
%!s(int64=14) %!d(string=hai) anos |
|
itcpugas.pas
|
47d43750e4
* remove unused units from uses statements
|
%!s(int64=12) %!d(string=hai) anos |
|
narmadd.pas
|
3a393f839e
* do not reuse register locations on arm fpa/vfp
|
%!s(int64=12) %!d(string=hai) anos |
|
narmcal.pas
|
8b8a786823
* moved ARM/x86 ifdef'ed code from ncgcal to virtual methods
|
%!s(int64=12) %!d(string=hai) anos |
|
narmcnv.pas
|
5051453806
+ support for LOC_(C)MMREGISTER in hlcg
|
%!s(int64=12) %!d(string=hai) anos |
|
narmcon.pas
|
47d43750e4
* remove unused units from uses statements
|
%!s(int64=12) %!d(string=hai) anos |
|
narminl.pas
|
5051453806
+ support for LOC_(C)MMREGISTER in hlcg
|
%!s(int64=12) %!d(string=hai) anos |
|
narmmat.pas
|
5051453806
+ support for LOC_(C)MMREGISTER in hlcg
|
%!s(int64=12) %!d(string=hai) anos |
|
narmmem.pas
|
36a32e153d
+ arm thumb: tarmloadparentfpnode moves the stack pointer to a different register to avoid illegal instruction encodings
|
%!s(int64=12) %!d(string=hai) anos |
|
narmset.pas
|
e5066a5f43
Update jumptabel generation for ARM Thumb
|
%!s(int64=12) %!d(string=hai) anos |
|
pp.lpi.template
|
1f032375c3
* improved template with help from Mattias Gaertner
|
%!s(int64=19) %!d(string=hai) anos |
|
raarm.pas
|
780e75bfac
o patch by Jeppe Johansen to fix mantis #17472:
|
%!s(int64=14) %!d(string=hai) anos |
|
raarmgas.pas
|
47d43750e4
* remove unused units from uses statements
|
%!s(int64=12) %!d(string=hai) anos |
|
rarmcon.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
rarmdwa.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
rarmnor.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
rarmnum.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
rarmrni.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
rarmsri.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
rarmsta.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
rarmstd.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
rarmsup.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
%!s(int64=13) %!d(string=hai) anos |
|
rgcpu.pas
|
1de40c8de7
* arm thumb: fix spilling with offsets >1020
|
%!s(int64=12) %!d(string=hai) anos |
florian
4056194e7c
* don't ignore by accident the next instruction after a newly inserted constant pool