m68k.inc 20 KB

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  1. {
  2. This file is part of the Free Pascal run time library.
  3. Copyright (c) 1999-2000 by Carl-Eric Codere,
  4. member of the Free Pascal development team.
  5. See the file COPYING.FPC, included in this distribution,
  6. for details about the copyright.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  10. **********************************************************************}
  11. {****************************************************************************
  12. m68k.inc : Processor dependent implementation of system unit
  13. For Motorola 680x0 Processor.
  14. *****************************************************************************}
  15. {****************************************************************************}
  16. { Credit where credit is due: }
  17. { -Some of the copy routines taken from the Atari dlib source code: }
  18. { Dale Schumacher (alias: Dalnefre') [email protected] }
  19. { 399 Beacon Ave. St. Paul, MN 55104,USA }
  20. { -Some of the routines taken from the freeware ATARI Sozobon C compiler }
  21. { 1988 by Sozobon, Limited. Author: Johann Ruegg (freeware) }
  22. { Thanks to all these people wherever they maybe today! }
  23. {****************************************************************************}
  24. {$IF DEFINED(FPU68881) OR DEFINED(FPUCOLDFIRE)}
  25. function GetFPCR: DWord; assembler; nostackframe;
  26. asm
  27. fmove.l fpcr,d0
  28. end;
  29. function GetFPSR: DWord; assembler; nostackframe;
  30. asm
  31. fmove.l fpsr, d0
  32. end;
  33. procedure SetFPCR(x: DWord); assembler; nostackframe;
  34. asm
  35. fmove.l x, fpcr
  36. end;
  37. procedure SetFPSR(x: DWord); assembler; nostackframe;
  38. asm
  39. fmove.l x, fpsr
  40. end;
  41. {$DEFINE FPC_SYSTEM_HAS_SYSRESETFPU}
  42. procedure SysResetFPU;
  43. begin
  44. SetFPCR(Default68KFPCR);
  45. SetFPSR(0);
  46. end;
  47. {$DEFINE FPC_SYSTEM_HAS_SYSINITFPU}
  48. procedure SysInitFPU;
  49. begin
  50. end;
  51. procedure fpc_cpuinit;
  52. begin
  53. if IsLibrary then
  54. begin
  55. Default68kFPCR:=GetFPCR;
  56. end;
  57. SysResetFPU;
  58. end;
  59. {$ELSE}
  60. procedure fpc_cpuinit;
  61. begin
  62. {$IFNDEF FPUNONE}
  63. SysResetFPU;
  64. if (not IsLibrary) then
  65. SysInitFPU;
  66. {$ENDIF}
  67. end;
  68. {$ENDIF}
  69. {$ifndef INTERNAL_BACKTRACE}
  70. {$define FPC_SYSTEM_HAS_GET_FRAME}
  71. function get_frame : pointer; assembler;nostackframe;
  72. asm
  73. move.l fp,d0
  74. end;
  75. {$endif not INTERNAL_BACKTRACE}
  76. {$define FPC_SYSTEM_HAS_GET_CALLER_ADDR}
  77. function get_caller_addr(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  78. asm
  79. move.l framebp,d0
  80. tst.l d0
  81. beq @Lnul_address
  82. move.l d0,a0
  83. move.l 4(a0),d0
  84. @Lnul_address:
  85. end;
  86. {$define FPC_SYSTEM_HAS_GET_CALLER_FRAME}
  87. function get_caller_frame(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  88. asm
  89. move.l framebp,d0
  90. tst.l d0
  91. beq @Lnul_frame
  92. move.l d0,a0
  93. move.l (a0),d0
  94. @Lnul_frame:
  95. end;
  96. {$define FPC_SYSTEM_HAS_SPTR}
  97. function Sptr : pointer; assembler;nostackframe;
  98. asm
  99. move.l sp,d0
  100. end;
  101. {$define FPC_SYSTEM_HAS_GET_PC_ADDR}
  102. function get_pc_addr : pointer;assembler;nostackframe;
  103. asm
  104. move.l (sp),d0
  105. end;
  106. {$define FPC_SYSTEM_HAS_FILLCHAR}
  107. procedure FillChar(var x; count : longint; value : byte); assembler; register; nostackframe;
  108. asm
  109. {$ifdef VER3_0}
  110. move.l x,a0
  111. move.l count,d0
  112. clr.l d1
  113. move.b value,d1
  114. {$endif VER3_0}
  115. { a0 is x, d0 is count, d1 is value }
  116. tst.l d0 { anything to fill at all? }
  117. ble @Lquit
  118. cmp.l #32,d0 { limits were tested against real hardware on various CPU }
  119. blt @LfillByte
  120. cmp.l #128,d0 { limits were tested against real hardware on various CPU }
  121. blt @LfillWord
  122. bra @LfillDWord
  123. {$ifndef CPUM68K_HAS_DBRA}
  124. @LfillByte:
  125. {$endif}
  126. @LfillByteLoop:
  127. move.b d1,(a0)+
  128. {$ifdef CPUM68K_HAS_DBRA}
  129. @LfillByte:
  130. dbra d0,@LfillByteLoop
  131. {$else}
  132. subq.l #1,d0
  133. bne @LfillByteLoop
  134. {$endif}
  135. rts
  136. @LfillWord:
  137. move.l d2,-(sp)
  138. move.l a0,d2
  139. btst #0,d2
  140. beq @Leven
  141. subq.l #1,d0
  142. move.b d1,(a0)+
  143. @Leven:
  144. move.b d1,d2 // copy value to upper byte
  145. {$ifdef CPUCOLDFIRE}
  146. lsl.l #8,d1
  147. {$else}
  148. lsl.w #8,d1
  149. {$endif}
  150. move.b d2,d1
  151. move.l d0,d2 // adjust d0 for leftover copy
  152. bclr #0,d2
  153. sub.l d2,d0
  154. lsr.l #1,d2
  155. {$ifdef CPUM68K_HAS_DBRA}
  156. subq.l #1,d2
  157. {$endif}
  158. @LfillWordLoop:
  159. move.w d1,(a0)+
  160. {$ifdef CPUM68K_HAS_DBRA}
  161. dbra d2,@LFillWordLoop
  162. {$else}
  163. subq.l #1,d2
  164. bne @LfillWordLoop
  165. {$endif}
  166. move.l (sp)+,d2
  167. tst.l d0
  168. bne @LfillByte
  169. rts
  170. @LfillDWord:
  171. move.l d2,-(sp)
  172. move.b d1,d2 // copy value to upper bytes
  173. {$ifdef CPUCOLDFIRE}
  174. lsl.l #8,d1
  175. {$else}
  176. lsl.w #8,d1
  177. {$endif}
  178. move.b d2,d1
  179. move.w d1,d2
  180. swap d1
  181. move.w d2,d1
  182. move.l a0,d2 // do initial byte and word fill, if the address is unaligned
  183. btst #0,d2
  184. beq @Ldeven
  185. subq.l #1,d0
  186. move.b d1,(a0)+
  187. @Ldeven:
  188. move.l a0,d2
  189. btst #1,d2
  190. beq @Ldquad
  191. subq.l #2,d0
  192. move.w d1,(a0)+
  193. @Ldquad:
  194. move.l d0,d2 // adjust d0 for leftover copy
  195. {$ifdef CPUCOLDFIRE}
  196. and.l #$fffffffc,d2
  197. {$else}
  198. and.b #$fc,d2
  199. {$endif}
  200. sub.l d2,d0
  201. lsr.l #2,d2
  202. bra @LfillLongLoopStart
  203. @LfillLongLoop:
  204. move.l d1,(a0)+
  205. move.l d1,(a0)+
  206. move.l d1,(a0)+
  207. move.l d1,(a0)+
  208. subq.l #4,d2
  209. @LfillLongLoopStart:
  210. cmp.l #4,d2
  211. bgt @LfillLongLoop
  212. {$ifdef CPUM68K_HAS_DBRA}
  213. subq.l #1,d2
  214. {$endif}
  215. @LfillDWordLoop:
  216. move.l d1,(a0)+
  217. {$ifdef CPUM68K_HAS_DBRA}
  218. dbra d2,@LFillDWordLoop
  219. {$else}
  220. subq.l #1,d2
  221. bne @LfillDWordLoop
  222. {$endif}
  223. move.l (sp)+,d2
  224. tst.l d0
  225. bne @LfillByte
  226. @Lquit:
  227. end;
  228. {$ifdef dummy}
  229. { procedure strcopy(dstr,sstr : pointer;len : longint);[public,alias: 'STRCOPY'];}
  230. procedure strcopy; assembler;[public,alias: 'FPC_STRCOPY'];
  231. {---------------------------------------------------}
  232. { Low-level routine to copy a string to another }
  233. { string with maximum length. Never call directly! }
  234. { On Entry: }
  235. { a1.l = string to copy to }
  236. { a0.l = source string }
  237. { d0.l = maximum length of copy }
  238. { registers destroyed: a0,a1,d0,d1 }
  239. {---------------------------------------------------}
  240. asm
  241. { move.l sstr,a0
  242. move.l dstr,a1
  243. move.l len,d1 }
  244. move.l d0,d1
  245. move.b (a0)+,d0 { Get source length }
  246. and.w #$ff,d0
  247. cmp.w d1,d0 { This is a signed comparison! }
  248. ble @LM4
  249. move.b d1,d0 { If longer than maximum size of target, cut
  250. source length }
  251. @LM4:
  252. andi.l #$ff,d0 { zero extend d0-byte }
  253. move.l d0,d1 { save length to copy }
  254. move.b d0,(a1)+ { save new length }
  255. { Check if copying length is zero - if so then }
  256. { exit without copying anything. }
  257. tst.b d1
  258. beq @Lend
  259. bra @LMSTRCOPY55
  260. @LMSTRCOPY56: { 68010 Fast loop mode }
  261. move.b (a0)+,(a1)+
  262. @LMSTRCOPY55:
  263. {$ifndef CPUM68K_HAS_DBRA}
  264. sub.l #1,d1
  265. bpl @LMSTRCOPY56
  266. {$else CPUM68K_HAS_DBRA}
  267. dbra d1,@LMSTRCOPY56
  268. {$endif CPUM68K_HAS_DBRA}
  269. @Lend:
  270. end;
  271. { Concatenate Strings }
  272. { PARAMETERS ARE REVERSED COMPARED TO NORMAL! }
  273. { therefore online assembler may not parse the params as normal }
  274. procedure strconcat(s1,s2 : pointer);[public,alias: 'STRCONCAT'];
  275. begin
  276. asm
  277. move.b #255,d0
  278. move.l s1,a0 { a0 = destination }
  279. move.l s2,a1 { a1 = source }
  280. sub.b (a0),d0 { copyl:= 255 -length(s1) }
  281. move.b (a1),d6
  282. and.w #$ff,d0 { Sign flags are checked! }
  283. and.w #$ff,d6
  284. cmp.w d6,d0 { if copyl > length(s2) then }
  285. ble @Lcontinue
  286. move.b (a1),d0 { copyl:=length(s2) }
  287. @Lcontinue:
  288. move.b (a0),d6
  289. and.l #$ff,d6
  290. lea 1(a0,d6),a0 { s1[length(s1)+1] }
  291. add.l #1,a1 { s2[1] }
  292. move.b d0,d6
  293. { Check if copying length is zero - if so then }
  294. { exit without copying anything. }
  295. tst.b d6
  296. beq @Lend
  297. bra @ALoop
  298. @Loop:
  299. move.b (a1)+,(a0)+ { s1[i] := s2[i]; }
  300. @ALoop:
  301. {$ifndef CPUM68K_HAS_DBRA}
  302. sub.l #1,d6
  303. bpl @Loop
  304. {$else CPUM68K_HAS_DBRA}
  305. dbra d6,@Loop
  306. {$endif CPUM68K_HAS_DBRA}
  307. move.l s1,a0
  308. add.b d0,(a0) { change to new string length }
  309. @Lend:
  310. end ['d0','d1','a0','a1','d6'];
  311. end;
  312. { Compares strings }
  313. { DO NOT CALL directly. }
  314. { a0 = pointer to first string to compare }
  315. { a1 = pointer to second string to compare }
  316. { ALL FLAGS are set appropriately. }
  317. { ZF = strings are equal }
  318. { REGISTERS DESTROYED: a0, a1, d0, d1, d6 }
  319. procedure strcmp; assembler;[public,alias:'FPC_STRCMP'];
  320. asm
  321. move.b (a0)+,d0 { Get length of first string }
  322. move.b (a1)+,d6 { Get length of 2nd string }
  323. move.b d6,d1 { Save length of string for final compare }
  324. cmp.b d0,d6 { Get shortest string length }
  325. ble @LSTRCONCAT1
  326. move.b d0,d6 { Set length to shortest string }
  327. @LSTRCONCAT1:
  328. tst.b d6 { Both strings have a length of zero, exit }
  329. beq @LSTRCONCAT2
  330. andi.l #$ff,d6
  331. subq.l #1,d6 { subtract first attempt }
  332. { if value is -1 then don't loop and just compare lengths of }
  333. { both strings before exiting. }
  334. bmi @LSTRCONCAT2
  335. or.l d0,d0 { Make sure to set Zerfo flag to 0 }
  336. @LSTRCONCAT5:
  337. { Workaroung for GAS v.134 bug }
  338. { old: cmp.b (a1)+,(a0)+ }
  339. cmpm.b (a1)+,(a0)+
  340. @LSTRCONCAT4:
  341. dbne d6,@LSTRCONCAT5 { Repeat until not equal }
  342. bne @LSTRCONCAT3
  343. @LSTRCONCAT2:
  344. { If length of both string are equal }
  345. { Then set zero flag }
  346. cmp.b d1,d0 { Compare length - set flag if equal length strings }
  347. @LSTRCONCAT3:
  348. end;
  349. {$endif dummy}
  350. {$define FPC_SYSTEM_HAS_MOVE}
  351. procedure move(const source;var dest;count : longint); assembler;
  352. { base pointer+8 = source }
  353. { base pointer+12 = destination }
  354. { base pointer+16 = number of bytes to move}
  355. asm
  356. move.l count, d0 { number of bytes }
  357. ble @LMOVE5 { anything to copy at all? }
  358. move.l dest, a1 { destination }
  359. move.l source, a0 { source }
  360. {$ifdef CPUM68K_HAS_DBRA}
  361. cmpi.l #65535, d0 { check, if this is a word move }
  362. ble @LMEMSET00 { use fast dbra mode 68010+ }
  363. {$endif CPUM68K_HAS_DBRA}
  364. cmp.l a0,a1 { check copy direction }
  365. bls @LMOVE3
  366. add.l d0,a0 { move pointers to end }
  367. add.l d0,a1
  368. @LMOVE1:
  369. move.b -(a0),-(a1) { (s < d) copy loop }
  370. subq.l #1,d0
  371. bne @LMOVE1
  372. bra @LMOVE5
  373. @LMOVE3:
  374. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  375. subq.l #1,d0
  376. bne @LMOVE3
  377. bra @LMOVE5
  378. {$ifdef CPUM68K_HAS_DBRA}
  379. @LMEMSET00: { use fast loop mode 68010+ }
  380. cmp.l a0,a1 { check copy direction }
  381. bls @LMOVE04
  382. add.l d0,a0 { move pointers to end }
  383. add.l d0,a1
  384. bra @LMOVE02
  385. @LMOVE01:
  386. move.b -(a0),-(a1) { (s < d) copy loop }
  387. @LMOVE02:
  388. dbra d0,@LMOVE01
  389. bra @LMOVE5
  390. @LMOVE03:
  391. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  392. @LMOVE04:
  393. dbra d0,@LMOVE03
  394. {$endif CPUM68K_HAS_DBRA}
  395. { end fast loop mode }
  396. @LMOVE5:
  397. end;
  398. {$ifdef CPUM68K_HAS_UNALIGNED}
  399. {$define FPC_SYSTEM_HAS_FILLWORD}
  400. procedure FillWord(var x; count : longint; value : word); assembler;
  401. asm
  402. move.l x, a0 { destination }
  403. move.w value, d1 { fill data }
  404. move.l count, d0 { number of bytes to fill }
  405. ble @LMEMSET3 { anything to fill at all? }
  406. bra @LMEMSET21
  407. @LMEMSET11:
  408. move.w d1,(a0)+
  409. @LMEMSET21:
  410. subq.l #1,d0
  411. bpl @LMEMSET11
  412. @LMEMSET3:
  413. end;
  414. {$endif}
  415. {$IFNDEF FPC_SYSTEM_HAS_INTERLOCKEDFUNCS}
  416. {$IFNDEF CPUM68K_HAS_CAS}
  417. var
  418. spinLock: byte;
  419. procedure getSpinLock; assembler; nostackframe;
  420. asm
  421. {$IFDEF CPUM68K_HAS_TAS}
  422. lea.l spinlock,a0
  423. @loop:
  424. tas (a0)
  425. bne @loop
  426. {$ENDIF}
  427. end;
  428. procedure releaseSpinLock; assembler; nostackframe;
  429. asm
  430. move.b #0,spinlock
  431. end;
  432. {$ENDIF}
  433. function InterLockedDecrement (var Target: longint) : longint;
  434. {$IFDEF CPUM68K_HAS_CAS}
  435. register; assembler;
  436. asm
  437. move.l (a0), d0
  438. @loop:
  439. move.l d0, d1
  440. subq.l #1, d1
  441. cas.l d0, d1, (a0)
  442. bne @loop
  443. move.l d1, d0
  444. end;
  445. {$ELSE}
  446. begin
  447. getSpinLock;
  448. Dec(Target);
  449. Result := Target;
  450. releaseSpinLock;
  451. end;
  452. {$ENDIF}
  453. function InterLockedIncrement (var Target: longint) : longint;
  454. {$IFDEF CPUM68K_HAS_CAS}
  455. register; assembler;
  456. asm
  457. move.l (a0), d0
  458. @loop:
  459. move.l d0, d1
  460. addq.l #1, d1
  461. cas.l d0, d1, (a0)
  462. bne @loop
  463. move.l d1, d0
  464. end;
  465. {$ELSE}
  466. begin
  467. getSpinLock;
  468. Inc(Target);
  469. Result := Target;
  470. releaseSpinLock;
  471. end;
  472. {$ENDIF}
  473. function InterLockedExchange (var Target: longint;Source : longint) : longint;
  474. {$IFDEF CPUM68K_HAS_CAS}
  475. register; assembler;
  476. asm
  477. move.l Source, d1
  478. move.l (a0), d0
  479. @loop:
  480. cas.l d0, d1, (a0)
  481. bne @loop
  482. end;
  483. {$ELSE}
  484. begin
  485. getSpinLock;
  486. Result := Target;
  487. Target := Source;
  488. releaseSpinLock;
  489. end;
  490. {$ENDIF}
  491. function InterLockedExchangeAdd (var Target: longint;Source : longint) : longint;
  492. {$IFDEF CPUM68K_HAS_CAS}
  493. register; assembler;
  494. asm
  495. move.l Source, a1
  496. move.l (a0), d0
  497. @loop:
  498. move.l a1, d1
  499. add.l d0, d1
  500. cas.l d0, d1, (a0)
  501. bne @loop
  502. end;
  503. {$ELSE}
  504. begin
  505. getSpinLock;
  506. Result := Target;
  507. Target := Target + Source;
  508. releaseSpinLock;
  509. end;
  510. {$ENDIF}
  511. function InterlockedCompareExchange(var Target: longint; NewValue: longint; Comperand: longint): longint;
  512. {$IFDEF CPUM68K_HAS_CAS}
  513. register; assembler;
  514. asm
  515. // Target = a0, NewValue = d0, Comperand = d1
  516. exg.l d0, d1
  517. cas.l d0, d1, (a0)
  518. end;
  519. {$ELSE}
  520. begin
  521. getSpinLock;
  522. Result := Target;
  523. if Target = Comperand then
  524. Target := NewValue;
  525. releaseSpinLock;
  526. end;
  527. {$ENDIF}
  528. {$ENDIF FPC_SYSTEM_HAS_INTERLOCKEDFUNCS}
  529. {$ifndef FPC_SYSTEM_HAS_TEST68K}
  530. procedure Test68k(var CPU: byte; var FPU: byte);
  531. begin
  532. {$warning Implement me!}
  533. CPU:=0;
  534. FPU:=0;
  535. end;
  536. {$endif}
  537. {$ifndef FPC_SYSTEM_HAS_SAR_QWORD}
  538. {$define FPC_SYSTEM_HAS_SAR_QWORD}
  539. function fpc_SarInt64(Const AValue : Int64;const Shift : Byte): Int64; [Public,Alias:'FPC_SARINT64']; compilerproc; assembler; nostackframe;
  540. asm
  541. // d0 = shift
  542. lea.l 4(sp),a0
  543. move.l d2,-(sp)
  544. move.l d0,d2
  545. {$ifndef CPUCOLDFIRE}
  546. and.w #63,d2
  547. cmp.w #32,d2
  548. {$else}
  549. and.l #63,d2
  550. cmp.l #32,d2
  551. {$endif}
  552. bge.s @longshift
  553. move.l (a0)+,d0
  554. move.l (a0),d1
  555. {$ifdef CPUM68K_HAS_ROLROR}
  556. cmp.w #1,d2
  557. beq.s @oneshift
  558. {$endif}
  559. {$ifdef CPU68000}
  560. cmp.w #16,d2
  561. beq.s @sixteenshift
  562. {$endif}
  563. move.l d3,a0
  564. move.l d4,a1
  565. move.l d0,d3
  566. moveq.l #32,d4
  567. {$ifndef CPUCOLDFIRE}
  568. sub.w d2,d4
  569. {$else}
  570. sub.l d2,d4
  571. {$endif}
  572. asr.l d2,d0
  573. lsl.l d4,d3
  574. lsr.l d2,d1
  575. or.l d3,d1
  576. move.l a0,d3
  577. move.l a1,d4
  578. bra.s @quit
  579. {$ifdef CPU68000}
  580. @sixteenshift:
  581. move.w d0,d1
  582. swap d1
  583. swap d0
  584. ext.l d0
  585. bra.s @quit
  586. {$endif}
  587. {$ifdef CPUM68K_HAS_ROLROR}
  588. @oneshift:
  589. asr.l #1,d0
  590. roxr.l #1,d1
  591. bra.s @quit
  592. {$endif}
  593. @longshift:
  594. move.l (a0),d0
  595. move.l d0,d1
  596. smi d0
  597. {$if defined(CPU68020) or defined(CPUCOLDFIRE)}
  598. extb.l d0
  599. {$else}
  600. ext.w d0
  601. ext.l d0
  602. {$endif}
  603. {$ifndef CPUCOLDFIRE}
  604. sub.w #32,d2
  605. {$else}
  606. sub.l #32,d2
  607. {$endif}
  608. asr.l d2,d1
  609. @quit:
  610. move.l (sp)+,d2
  611. end;
  612. {$endif}
  613. {$if defined(CPUM68K_HAS_BYTEREV) or defined(CPUM68K_HAS_ROLROR)}
  614. { Disabled for now, because not all cases below were tested. (KB) }
  615. {.$define FPC_SYSTEM_HAS_SWAPENDIAN}
  616. {$endif}
  617. {$if defined(FPC_SYSTEM_HAS_SWAPENDIAN)}
  618. function SwapEndian(const AValue: SmallInt): SmallInt; assembler; nostackframe;
  619. asm
  620. {$if defined(CPUM68K_HAS_ROLROR)}
  621. move.w avalue, d0
  622. ror.w #8, d0
  623. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  624. move.w avalue, d0
  625. byterev d0
  626. swap d0
  627. {$else}
  628. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  629. clr.l d0
  630. move.w avalue, d0
  631. move.w d0, d1
  632. lsr.l #8, d0
  633. lsl.l #8, d1
  634. or.l d1, d0
  635. {$endif}
  636. end;
  637. function SwapEndian(const AValue: Word): Word; assembler; nostackframe;
  638. asm
  639. {$if defined(CPUM68K_HAS_ROLROR)}
  640. move.w avalue, d0
  641. ror.w #8, d0
  642. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  643. move.w avalue, d0
  644. byterev d0
  645. swap d0
  646. {$else}
  647. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  648. clr.l d0
  649. move.w avalue, d0
  650. move.w d0, d1
  651. lsr.l #8, d0
  652. lsl.l #8, d1
  653. or.l d1, d0
  654. {$endif}
  655. end;
  656. function SwapEndian(const AValue: LongInt): LongInt; assembler; nostackframe;
  657. asm
  658. {$if defined(CPUM68K_HAS_ROLROR)}
  659. move.l avalue, d0
  660. ror.w #8, d0
  661. swap d0
  662. ror.w #8, d0
  663. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  664. move.l avalue, d0
  665. byterev d0
  666. {$else}
  667. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  668. move.l avalue, d0
  669. move.l d0, d1
  670. andi.l #$ff00ff00, d0
  671. andi.l #$00ff00ff, d1
  672. lsr.l #8, d0
  673. lsl.l #8, d1
  674. or.l d1, d0
  675. swap d0
  676. {$endif}
  677. end;
  678. function SwapEndian(const AValue: DWord): DWord; assembler; nostackframe;
  679. asm
  680. {$if defined(CPUM68K_HAS_ROLROR)}
  681. move.l avalue, d0
  682. ror.w #8, d0
  683. swap d0
  684. ror.w #8, d0
  685. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  686. move.l avalue, d0
  687. byterev d0
  688. {$else}
  689. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  690. move.l avalue, d0
  691. move.l d0, d1
  692. andi.l #$ff00ff00, d0
  693. andi.l #$00ff00ff, d1
  694. lsr.l #8, d0
  695. lsl.l #8, d1
  696. or.l d1, d0
  697. swap d0
  698. {$endif}
  699. end;
  700. function SwapEndian(const AValue: Int64): Int64; assembler; nostackframe;
  701. asm
  702. {$if defined(CPUM68K_HAS_ROLROR)}
  703. move.l avalue+4, d0
  704. ror.w #8, d0
  705. swap d0
  706. ror.w #8, d0
  707. move.l avalue, d1
  708. ror.w #8, d1
  709. swap d1
  710. ror.w #8, d1
  711. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  712. move.l avalue+4, d0
  713. move.l avalue, d1
  714. byterev d0
  715. byterev d1
  716. {$else}
  717. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  718. move.l d2, -(sp)
  719. move.l avalue+4, d0
  720. move.l d0, d1
  721. andi.l #$ff00ff00, d0
  722. andi.l #$00ff00ff, d1
  723. lsr.l #8, d0
  724. lsl.l #8, d1
  725. or.l d1, d0
  726. swap d0
  727. move.l avalue, d1
  728. move.l d1, d2
  729. andi.l #$ff00ff00, d1
  730. andi.l #$00ff00ff, d2
  731. lsr.l #8, d1
  732. lsl.l #8, d2
  733. or.l d2, d1
  734. swap d1
  735. move.l (sp)+, d2
  736. {$endif}
  737. end;
  738. function SwapEndian(const AValue: QWord): QWord; assembler; nostackframe;
  739. asm
  740. {$if defined(CPUM68K_HAS_ROLROR)}
  741. move.l avalue+4, d0
  742. ror.w #8, d0
  743. swap d0
  744. ror.w #8, d0
  745. move.l avalue, d1
  746. ror.w #8, d1
  747. swap d1
  748. ror.w #8, d1
  749. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  750. move.l avalue+4, d0
  751. move.l avalue, d1
  752. byterev d0
  753. byterev d1
  754. {$else}
  755. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  756. move.l d2, -(sp)
  757. move.l avalue+4, d0
  758. move.l d0, d1
  759. andi.l #$ff00ff00, d0
  760. andi.l #$00ff00ff, d1
  761. lsr.l #8, d0
  762. lsl.l #8, d1
  763. or.l d1, d0
  764. swap d0
  765. move.l avalue, d1
  766. move.l d1, d2
  767. andi.l #$ff00ff00, d1
  768. andi.l #$00ff00ff, d2
  769. lsr.l #8, d1
  770. lsl.l #8, d2
  771. or.l d2, d1
  772. swap d1
  773. move.l (sp)+, d2
  774. {$endif}
  775. end;
  776. {$endif FPC_SYSTEM_HAS_SWAPENDIAN}
  777. procedure fpc_cpucodeinit;
  778. begin
  779. Test68k(Test68000,Test68881);
  780. end;