* make use of cpuflags in the arm compiler

* armv5te architecture

git-svn-id: trunk@22103 -

compiler/arm/aoptcpu.pas

@@ -370,7 +370,7 @@ Implementation
                       into
                       strd reg1,ref
                     }
-                    else if not(current_settings.cputype in [cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5t]) and
+                    else if (CPUARM_HAS_LDRDSTRD in cpu_capabilities[current_settings.cputype]) and
                        (taicpu(p).oppostfix=PF_None) and
                        (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
                        GetNextInstruction(p,hp1) and
@@ -433,7 +433,7 @@ Implementation
                            ...
                            ldrd reg1,ref
                         }
-                        else if not(current_settings.cputype in [cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5t]) and
+                        else if (CPUARM_HAS_LDRDSTRD in cpu_capabilities[current_settings.cputype]) and
                           { ldrd does not allow any postfixes ... }
                           (taicpu(p).oppostfix=PF_None) and
                           not(odd(getsupreg(taicpu(p).oper[0]^.reg))) and

compiler/arm/cgcpu.pas

@@ -529,11 +529,10 @@ unit cgcpu;
         branchopcode: tasmop;
       begin
         { check not really correct: should only be used for non-Thumb cpus }
-        if (current_settings.cputype<cpu_armv5) or
-           (current_settings.cputype in cpu_thumb2) then
-          branchopcode:=A_BL
+        if CPUARM_HAS_BLX in cpu_capabilities[current_settings.cputype] then
+          branchopcode:=A_BLX
         else
-          branchopcode:=A_BLX;
+          branchopcode:=A_BL;
         if target_info.system<>system_arm_darwin then
           if not weak then
             list.concat(taicpu.op_sym(branchopcode,current_asmdata.RefAsmSymbol(s)))
@@ -554,7 +553,7 @@ unit cgcpu;
     procedure tcgarm.a_call_reg(list : TAsmList;reg: tregister);
       begin
         { check not really correct: should only be used for non-Thumb cpus }
-        if (current_settings.cputype<cpu_armv5) then
+        if not(CPUARM_HAS_BLX in cpu_capabilities[current_settings.cputype]) then
           begin
             list.concat(taicpu.op_reg_reg(A_MOV,NR_R14,NR_PC));
             list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,reg));
@@ -1808,7 +1807,7 @@ unit cgcpu;
 
                 if regs=[] then
                   begin
-                    if (current_settings.cputype<cpu_armv5) then
+                    if not(CPUARM_HAS_BX in cpu_capabilities[current_settings.cputype]) then
                       list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R14))
                     else
                       list.concat(taicpu.op_reg(A_BX,NR_R14))
@@ -1829,7 +1828,7 @@ unit cgcpu;
                 list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,R_INTREGISTER,R_SUBWHOLE,regs),PF_EA));
               end;
           end
-        else if (current_settings.cputype<cpu_armv5) then
+        else if not(CPUARM_HAS_BX in cpu_capabilities[current_settings.cputype]) then
           list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R14))
         else
           list.concat(taicpu.op_reg(A_BX,NR_R14))

compiler/arm/cpuinfo.pas

@@ -37,6 +37,7 @@ Type
        cpu_armv4t,
        cpu_armv5,
        cpu_armv5t,
+       cpu_armv5te,
        cpu_armv6,
        cpu_armv7,
        cpu_armv7m
@@ -198,6 +199,7 @@ Const
      'ARMV4T',
      'ARMV5',
      'ARMV5T',
+     'ARMV5TE',
      'ARMV6',
      'ARMV7',
      'ARMV7M'
@@ -1092,24 +1094,29 @@ Const
  type
    tcpuflags =
       (CPUARM_HAS_BX,
+       CPUARM_HAS_BLX,
+       CPUARM_HAS_LDRDSTRD,
+       CPUARM_HAS_PLD,
        CPUARM_HAS_REV,
-       CPUARM_HAS_IDIV,
-       CPUARM_HAS_LDREX
+       CPUARM_HAS_LDREX,
+       CPUARM_HAS_IDIV
       );
 
  const
    cpu_capabilities : array[tcputype] of set of tcpuflags =
-     ( { cpu_none   } [],
-       { cpu_armv3  } [],
-       { cpu_armv4  } [],
-       { cpu_armv4t } [CPUARM_HAS_BX],
-       { cpu_armv5  } [CPUARM_HAS_BX],
-       { cpu_armv5t } [CPUARM_HAS_BX],
-       { cpu_armv6  } [CPUARM_HAS_BX,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
-       { cpu_armv7  } [CPUARM_HAS_BX,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
-       { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_REV,CPUARM_HAS_IDIV,CPUARM_HAS_LDREX]
+     ( { cpu_none    } [],
+       { cpu_armv3   } [],
+       { cpu_armv4   } [],
+       { cpu_armv4t  } [CPUARM_HAS_BX],
+       { cpu_armv5   } [CPUARM_HAS_BX,CPUARM_HAS_BLX],
+       { cpu_armv5t  } [CPUARM_HAS_BX,CPUARM_HAS_BLX],
+       { cpu_armv5te } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD],
+       { cpu_armv6   } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
+       { cpu_armv7   } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
+       { cpu_armv7m  } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV]
      );
 
 Implementation
 
 end.
+

compiler/arm/narminl.pas

@@ -320,7 +320,7 @@ implementation
         ref : treference;
         r : tregister;
       begin
-        if current_settings.cputype>=cpu_armv5 then
+        if CPUARM_HAS_PLD in cpu_capabilities[current_settings.cputype] then
           begin
             secondpass(left);
             case left.location.loc of