Add cntfrq_el0 and cntpct_el0 AArch64 registers

compiler/aarch64/a64reg.dat

@@ -82,6 +82,9 @@ FPSR,$05,$00,$02,fpsr,0,0
 TPIDR_EL0,$05,$00,$03,tpidr_el0,0,0
 MPIDR_EL1,$05,$00,$04,mpidr_el1,0,0
 
+CNTFRQ_EL0,$03,$03,$0D,cntfrq_el0,0,0
+CNTPCT_EL0,$03,$03,$0E,cntpct_el0,0,0
+
 ; vfp registers
 ; generated by fpc/compiler/utils/gena64vfp.pp to avoid tedious typing
 B0,$04,$01,$00,b0,64,64

compiler/aarch64/ra64con.inc

@@ -71,6 +71,8 @@ NR_FPCR = tregister($05000001);
 NR_FPSR = tregister($05000002);
 NR_TPIDR_EL0 = tregister($05000003);
 NR_MPIDR_EL1 = tregister($05000004);
+NR_CNTFRQ_EL0 = tregister($0303000D);
+NR_CNTPCT_EL0 = tregister($0303000E);
 NR_B0 = tregister($04010000);
 NR_H0 = tregister($04030000);
 NR_S0 = tregister($04090000);

compiler/aarch64/ra64dwa.inc

@@ -71,6 +71,8 @@
 0,
 0,
 0,
+0,
+0,
 64,
 64,
 64,

compiler/aarch64/ra64nor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from a64reg.dat }
-648
+650

compiler/aarch64/ra64num.inc

@@ -71,6 +71,8 @@ tregister($05000001),
 tregister($05000002),
 tregister($05000003),
 tregister($05000004),
+tregister($0303000D),
+tregister($0303000E),
 tregister($04010000),
 tregister($04030000),
 tregister($04090000),

compiler/aarch64/ra64rni.inc

@@ -66,102 +66,40 @@
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 67,
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compiler/aarch64/ra64sri.inc

@@ -1,37 +1,73 @@
 { don't edit, this file is generated from a64reg.dat }
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@@ -64,42 +100,40 @@
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compiler/aarch64/ra64sta.inc

@@ -71,6 +71,8 @@
 0,
 0,
 0,
+0,
+0,
 64,
 64,
 64,

compiler/aarch64/ra64std.inc

@@ -71,6 +71,8 @@
 'fpsr',
 'tpidr_el0',
 'mpidr_el1',
+'cntfrq_el0',
+'cntpct_el0',
 'b0',
 'h0',
 's0',

compiler/aarch64/ra64sup.inc

@@ -71,6 +71,8 @@ RS_FPCR = $01;
 RS_FPSR = $02;
 RS_TPIDR_EL0 = $03;
 RS_MPIDR_EL1 = $04;
+RS_CNTFRQ_EL0 = $0D;
+RS_CNTPCT_EL0 = $0E;
 RS_B0 = $00;
 RS_H0 = $00;
 RS_S0 = $00;