 pierre
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9c90f593ab
Add global range check disable for i8086 cgcpu and x86 nx86add units
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6 år sedan |
 florian
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d4c65cdac4
* better register de-allocation after CWD/CWB
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7 år sedan |
 Jonas Maebe
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d69ad8fa41
* removed temppos field again from parameter locations: they're not allocated
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7 år sedan |
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Jonas Maebe
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4686f61002
* keep track of the temp position separately from the offset in references,
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7 år sedan |
 nickysn
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bd3d35f2da
+ add support for passing 32-bit values in a pair of registers in
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7 år sedan |
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nickysn
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4fc2fa7899
* alloc/dealloc NR_DEFAULTFLAGS in the a_cmp_* methods in the i8086 code
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7 år sedan |
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nickysn
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db09759763
* also integrated the getnextreg() implementation for 8-bit and 16-bit alus from
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7 år sedan |
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nickysn
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cf28b202eb
* integrated the getintregister() implementation for 8-bit and 16-bit alus from
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7 år sedan |
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nickysn
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ddba821561
* GetNextReg(), used by 16-bit and 8-bit code generators (i8086 and avr) moved
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7 år sedan |
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nickysn
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4e4e5d6d07
+ allocate and free the flags register (when necessary), when generating code
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8 år sedan |
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nickysn
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b8c4dd9e18
+ implemented 64-bit OP_SHR,OP_SHL and OP_SAR in a_op64_reg_reg for i8086 and
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8 år sedan |
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nickysn
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a82c89d894
+ implemented OP_SHR,OP_SHL and OP_SAR in a_op64_const_reg for i8086. The shlshr
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8 år sedan |
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nickysn
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65977f9f27
+ implemented OP_ROL and OP_ROR in tcg8086.a_op_reg_reg and .a_op_reg_ref
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8 år sedan |
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nickysn
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8c200fcfba
+ implemented OP_SHR,OP_SHL,OP_SAR,OP_ROL and OP_ROR in tcg8086.a_op_const_ref
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8 år sedan |
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nickysn
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50b1c9c088
+ implemented 32-bit OP_SHR,OP_SHL and OP_SAR in tcg8086.a_op_reg_ref
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8 år sedan |
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nickysn
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7ee0c07b8d
+ added flags register tracking for many i8086 operations
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8 år sedan |
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nickysn
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256dc546ac
+ implemented the in_neg_assign_x and in_not_assign_x inline nodes, which will
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8 år sedan |
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nickysn
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9093047a7a
* fixed a bug in the i8086 32-bit rol/ror code generation method rm_fast_386
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8 år sedan |
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nickysn
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1560f20e7f
+ implemented other 32-bit rol/ror by const methods for i8086 and added a
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8 år sedan |
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nickysn
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0fd860d9e7
* refactored the code generation for 32-bit rol/ror by const for i8086, so it
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8 år sedan |
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nickysn
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d5e33cce7f
* generate better i8086 code for ror32 by 1 and 17
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8 år sedan |
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nickysn
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321876252b
+ enabled the rol/ror intrinsic on i8086
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8 år sedan |
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nickysn
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76cb419241
* use 16-bit 386+ instructions (shld,shrd) for performing fast 32-bit
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8 år sedan |
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nickysn
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0ab4f01668
* implemented fast (loopless) 32-bit shift by constant for 8086 as well
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8 år sedan |
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nickysn
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0f2ad7b712
* generate faster (i.e. loopless) code for 32-bit shl/shr/sar by const on 186+
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8 år sedan |
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nickysn
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f0a63fa895
+ added an optimized implementation of a_op64_reg_ref for i8086; this improves
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8 år sedan |
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Jonas Maebe
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a25ebbba3e
+ added volatility information to all memory references
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8 år sedan |
 svenbarth
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c8202061dc
* get rid of addr_load_indirect again by having tcgx86 provide an internal implementation of both make_simple_ref() and a_load_ref_reg() so that make_direct_ref() can call the latter (and the latter the former) without fear of inifinite recursive calls due to the symbol; a_load_ref_reg() is additionally declared as "final" as a_load_ref_reg_internal() needs to be overloaded instead (which is the case for tcg8086)
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8 år sedan |
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Jonas Maebe
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aa1be3276f
- removed default value of _typ parameter of TAsmData.(Weak)RefAsmSymbol():
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9 år sedan |
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nickysn
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ac5658470e
+ use the 16-bit movsx and movzx instructions on 386+ in tcg8086.a_load_ref_reg
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9 år sedan |
