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aasmcpu.pas
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20dbda751a
* fixed sparc compilation after addr_lo/hi changes
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18 years ago |
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aoptcpu.pas
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da910d654c
+ SPARC: two more peephole optimizations
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11 years ago |
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aoptcpub.pas
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2f5ce095ce
* RefsHaveIndexReg -> cpurefshaveindexreg
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13 years ago |
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aoptcpud.pas
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790a4fe2d3
* log and id tags removed
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20 years ago |
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cgcpu.pas
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534ecbda9f
* SPARC: r26561 caused a_op_const_reg_reg used for zero-extending 8-bit values to be optimized away. Fixed by replacing it with an explicit instruction.
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11 years ago |
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cpubase.pas
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eaba90dda7
* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches.
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11 years ago |
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cpuelf.pas
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0aa7204707
+ Added codes of dynamic relocations to TElfTarget; since most targets use similar dynamic relocation model differing only in code values, this will allow to do majority of handling in the base class.
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12 years ago |
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cpugas.pas
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5e6669890a
Handle asmextraopt in powerpc, mips and sparc assemblers
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11 years ago |
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cpuinfo.pas
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e190f76dd9
* removed spaces from sparc cpu name strings so they can be much easier used
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12 years ago |
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cpunode.pas
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b270a1922b
* reverts r18960, should solve sparc trouble
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14 years ago |
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cpupara.pas
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e9268a0a14
* synchronised with trunk up till r26975
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11 years ago |
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cpupi.pas
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176d8434e4
* SPARC: completely rewrote PIC-related code, got it twice shorter in source lines and much less instructions in generated code.
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11 years ago |
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cputarg.pas
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7587145320
Add possibility to test sparc elf generator with -dTEST_AGSPARC_ELF
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13 years ago |
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hlcgcpu.pas
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72e9cfee24
* create/destroy also the high level code generator for all architectures,
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14 years ago |
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itcpugas.pas
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790a4fe2d3
* log and id tags removed
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20 years ago |
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ncpuadd.pas
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720b9bf560
* SPARC: reworked 64-bit comparisons so their result is always in flags. Comparisons are emitted as subtractions, sides are optionally swapped to avoid using Z flag (since it is not set correctly in multi-word subtraction). This generates significantly shorter code: when both sides are in registers it is just 3 instructions for equal/unequal and 2 instructions otherwise.
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11 years ago |
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ncpucall.pas
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51825b6f2e
compiler: change ret_in_param to accept tabstractprocdef instead of tproccalloption to allow check more options (required for record constructor implementation)
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12 years ago |
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ncpucnv.pas
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58cc531dd9
* SPARC: convert from int64/qword to float using genmath helpers. Removes dependency on softfloat code.
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11 years ago |
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ncpuinln.pas
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6b8aed593f
* remove registers{int/mmx/fpu} from firstpass
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18 years ago |
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ncpumat.pas
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cda81e1d18
* SPARC: emit "x shl 1" as "x+x", it yields shorter code.
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11 years ago |
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ncpuset.pas
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c673c32ad9
+ SPARC: generate position-independent case jump tables, as specified by ABI.
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11 years ago |
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opcode.inc
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9a486d73ba
+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.
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11 years ago |
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racpu.pas
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18eb495d0f
* give a regular error message instead of an internal error on x86
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17 years ago |
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racpugas.pas
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eaba90dda7
* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches.
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11 years ago |
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rgcpu.pas
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e9268a0a14
* synchronised with trunk up till r26975
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11 years ago |
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rspcon.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspdwrf.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspnor.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspnum.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rsprni.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspsri.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspstab.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspstd.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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rspsup.inc
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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spreg.dat
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c3da1aa542
Reenabled D0-D30 registers
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13 years ago |
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strinst.inc
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9a486d73ba
+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.
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11 years ago |
Jonas Maebe
e9268a0a14
* synchronised with trunk up till r26975