cpuinfo.pas 15 KB

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  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the MIPS
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. {$if FPC_FULLVERSION>20700}
  17. bestrealrec = TDoubleRec;
  18. {$endif FPC_FULLVERSION>20700}
  19. ts32real = single;
  20. ts64real = double;
  21. ts80real = type double;
  22. ts128real = type double;
  23. ts64comp = comp;
  24. pbestreal=^bestreal;
  25. { possible supported processors for this target }
  26. tcputype =
  27. (cpu_none,
  28. cpu_mips1,
  29. cpu_mips2,
  30. cpu_mips3,
  31. cpu_mips4,
  32. cpu_mips5,
  33. cpu_mips32,
  34. cpu_mips32r2,
  35. cpu_pic32mx
  36. );
  37. tfputype =(fpu_none,fpu_soft,fpu_mips2,fpu_mips3);
  38. tabitype =
  39. (
  40. abi_none,
  41. abi_default,
  42. abi_o32,
  43. abi_n32,
  44. abi_o64,
  45. abi_n64,
  46. abi_eabi
  47. );
  48. Const
  49. {# Size of native extended floating point type }
  50. extended_size = 8;
  51. {# Size of a multimedia register }
  52. mmreg_size = 0;
  53. { calling conventions supported by the code generator }
  54. supported_calling_conventions : tproccalloptions = [
  55. pocall_internproc,
  56. pocall_stdcall,
  57. pocall_safecall,
  58. { same as stdcall only different name mangling }
  59. pocall_cdecl,
  60. { same as stdcall only different name mangling }
  61. pocall_cppdecl
  62. ];
  63. { cpu strings as accepted by
  64. GNU assembler in -arch=XXX option
  65. this ilist needs to be uppercased }
  66. cputypestr : array[tcputype] of string[8] = ('',
  67. { cpu_mips1 } 'MIPS1',
  68. { cpu_mips2 } 'MIPS2',
  69. { cpu_mips3 } 'MIPS3',
  70. { cpu_mips4 } 'MIPS4',
  71. { cpu_mips5 } 'MIPS5',
  72. { cpu_mips32 } 'MIPS32',
  73. { cpu_mips32r2 } 'MIPS32R2',
  74. { cpu_pic32mx } 'PIC32MX'
  75. );
  76. fputypestr : array[tfputype] of string[9] = ('',
  77. 'SOFT',
  78. 'MIPS2','MIPS3'
  79. );
  80. { abi strings as accepted by
  81. GNU assembler in -abi=XXX option }
  82. abitypestr : array[tabitype] of string[4] =
  83. ({ abi_none } '',
  84. { abi_default } '32',
  85. { abi_o32 } '32',
  86. { abi_n32 } 'n32',
  87. { abi_o64 } 'o64',
  88. { abi_n64 } '64',
  89. { abi_eabi } 'eabi'
  90. );
  91. mips_abi : tabitype = abi_default;
  92. type
  93. tcpuflags=(
  94. CPUMIPS_HAS_CMOV, { conditional move instructions (mips4+) }
  95. CPUMIPS_HAS_ISA32R2 { mips32r2 instructions (also on PIC32) }
  96. );
  97. tcontrollerdatatype = record
  98. controllertypestr, controllerunitstr: string[20];
  99. cputype: tcputype; fputype: tfputype;
  100. flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
  101. end;
  102. const
  103. cpu_capabilities : array[tcputype] of set of tcpuflags =
  104. ( { cpu_none } [],
  105. { cpu_mips1 } [],
  106. { cpu_mips2 } [],
  107. { cpu_mips3 } [],
  108. { cpu_mips4 } [CPUMIPS_HAS_CMOV],
  109. { cpu_mips5 } [CPUMIPS_HAS_CMOV],
  110. { cpu_mips32 } [CPUMIPS_HAS_CMOV],
  111. { cpu_mips32r2 } [CPUMIPS_HAS_CMOV,CPUMIPS_HAS_ISA32R2],
  112. { cpu_pic32mx } [CPUMIPS_HAS_CMOV,CPUMIPS_HAS_ISA32R2]
  113. );
  114. {$ifndef MIPSEL}
  115. type
  116. tcontrollertype =
  117. (ct_none
  118. );
  119. Const
  120. { Is there support for dealing with multiple microcontrollers available }
  121. { for this platform? }
  122. ControllerSupport = false;
  123. { We know that there are fields after sramsize
  124. but we don't care about this warning }
  125. {$PUSH}
  126. {$WARN 3177 OFF}
  127. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  128. (
  129. (controllertypestr:''; controllerunitstr:''; cputype:cpu_none; fputype:fpu_none; flashbase:0; flashsize:0; srambase:0; sramsize:0));
  130. {$POP}
  131. {$ELSE MIPSEL}
  132. { Is there support for dealing with multiple microcontrollers available }
  133. { for this platform? }
  134. ControllerSupport = true;
  135. type
  136. tcontrollertype =
  137. (ct_none,
  138. { pic32mx }
  139. ct_pic32mx110f016b,
  140. ct_pic32mx110f016c,
  141. ct_pic32mx110f016d,
  142. ct_pic32mx120f032b,
  143. ct_pic32mx120f032c,
  144. ct_pic32mx120f032d,
  145. ct_pic32mx130f064b,
  146. ct_pic32mx130f064c,
  147. ct_pic32mx130f064d,
  148. ct_pic32mx150f128b,
  149. ct_pic32mx150f128c,
  150. ct_pic32mx150f128d,
  151. ct_pic32mx210f016b,
  152. ct_pic32mx210f016c,
  153. ct_pic32mx210f016d,
  154. ct_pic32mx220f032b,
  155. ct_pic32mx220f032c,
  156. ct_pic32mx220f032d,
  157. ct_pic32mx230f064b,
  158. ct_pic32mx230f064c,
  159. ct_pic32mx230f064d,
  160. ct_pic32mx250f128b,
  161. ct_pic32mx250f128c,
  162. ct_pic32mx250f128d,
  163. ct_pic32mx775f256h,
  164. ct_pic32mx775f256l,
  165. ct_pic32mx775f512h,
  166. ct_pic32mx775f512l,
  167. ct_pic32mx795f512h,
  168. ct_pic32mx795f512l
  169. );
  170. { We know that there are fields after sramsize
  171. but we don't care about this warning }
  172. {$WARN 3177 OFF}
  173. const
  174. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  175. (
  176. (controllertypestr:''; controllerunitstr:''; cputype: cpu_none; fputype: fpu_none; flashbase:0; flashsize:0; srambase:0; sramsize:0),
  177. { PIC32MX1xx Series}
  178. (controllertypestr:'PIC32MX110F016B'; controllerunitstr:'PIC32MX1xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  179. (controllertypestr:'PIC32MX110F016C'; controllerunitstr:'PIC32MX1xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  180. (controllertypestr:'PIC32MX110F016D'; controllerunitstr:'PIC32MX1xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  181. (controllertypestr:'PIC32MX120F032B'; controllerunitstr:'PIC32MX1xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  182. (controllertypestr:'PIC32MX120F032C'; controllerunitstr:'PIC32MX1xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  183. (controllertypestr:'PIC32MX120F032D'; controllerunitstr:'PIC32MX1xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  184. (controllertypestr:'PIC32MX130F064B'; controllerunitstr:'PIC32MX1xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  185. (controllertypestr:'PIC32MX130F064C'; controllerunitstr:'PIC32MX1xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  186. (controllertypestr:'PIC32MX130F064D'; controllerunitstr:'PIC32MX1xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  187. (controllertypestr:'PIC32MX150F128B'; controllerunitstr:'PIC32MX1xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  188. (controllertypestr:'PIC32MX150F128C'; controllerunitstr:'PIC32MX1xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  189. (controllertypestr:'PIC32MX150F128D'; controllerunitstr:'PIC32MX1xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  190. { PIC32MX2xx Series}
  191. (controllertypestr:'PIC32MX210F016B'; controllerunitstr:'PIC32MX2xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  192. (controllertypestr:'PIC32MX210F016C'; controllerunitstr:'PIC32MX2xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  193. (controllertypestr:'PIC32MX210F016D'; controllerunitstr:'PIC32MX2xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  194. (controllertypestr:'PIC32MX220F032B'; controllerunitstr:'PIC32MX2xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  195. (controllertypestr:'PIC32MX220F032C'; controllerunitstr:'PIC32MX2xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  196. (controllertypestr:'PIC32MX220F032D'; controllerunitstr:'PIC32MX2xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  197. (controllertypestr:'PIC32MX230F064B'; controllerunitstr:'PIC32MX2xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  198. (controllertypestr:'PIC32MX230F064C'; controllerunitstr:'PIC32MX2xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  199. (controllertypestr:'PIC32MX230F064D'; controllerunitstr:'PIC32MX2xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  200. (controllertypestr:'PIC32MX250F128B'; controllerunitstr:'PIC32MX2xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  201. (controllertypestr:'PIC32MX250F128C'; controllerunitstr:'PIC32MX2xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$80000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  202. (controllertypestr:'PIC32MX250F128D'; controllerunitstr:'PIC32MX2xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
  203. { PIC32MX7x5 Series}
  204. (controllertypestr:'PIC32MX775F256H'; controllerunitstr:'PIC32MX7x5FxxxH'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00040000; srambase:$A0000000; sramsize:$00010000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
  205. (controllertypestr:'PIC32MX775F256L'; controllerunitstr:'PIC32MX7x5FxxxL'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00040000; srambase:$A0000000; sramsize:$00010000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
  206. (controllertypestr:'PIC32MX775F512H'; controllerunitstr:'PIC32MX7x5FxxxH'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00080000; srambase:$A0000000; sramsize:$00010000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
  207. (controllertypestr:'PIC32MX775F512L'; controllerunitstr:'PIC32MX7x5FxxxL'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00080000; srambase:$A0000000; sramsize:$00010000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
  208. (controllertypestr:'PIC32MX795F512H'; controllerunitstr:'PIC32MX7x5FxxxH'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00080000; srambase:$A0000000; sramsize:$00020000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
  209. (controllertypestr:'PIC32MX795F512L'; controllerunitstr:'PIC32MX7x5FxxxL'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00080000; srambase:$A0000000; sramsize:$00020000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF)
  210. );
  211. {$endif MIPSEL}
  212. { Supported optimizations, only used for information }
  213. supported_optimizerswitches = [cs_opt_regvar,cs_opt_loopunroll,cs_opt_nodecse,
  214. cs_opt_reorder_fields,cs_opt_fastmath];
  215. level1optimizerswitches = genericlevel1optimizerswitches;
  216. level2optimizerswitches = level1optimizerswitches + [cs_opt_regvar,cs_opt_stackframe,cs_opt_nodecse];
  217. level3optimizerswitches = level2optimizerswitches + [cs_opt_loopunroll];
  218. level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
  219. function SetMipsABIType(const s : string) : boolean;
  220. Implementation
  221. uses
  222. cutils;
  223. function SetMipsABIType(const s : string) : boolean;
  224. var
  225. abi : tabitype;
  226. begin
  227. SetMipsABIType:=false;
  228. for abi := low(tabitype) to high(tabitype) do
  229. if (lower(s)=abitypestr[abi]) then
  230. begin
  231. mips_abi:=abi;
  232. SetMipsABIType:=true;
  233. break;
  234. end;
  235. end;
  236. end.