yury 039aee9568 * i386 PIC: Do not force EBX as a GOT register if tf_section_threadvars is not set. Actually forcing EBX here is a bad idea anyway. 6 lat temu
..
aoptcpu.pas a277a5f8db * Removed unused local vars. 6 lat temu
aoptcpub.pas 9b0ff05ee8 - get rid of MaxOps, it is redundant with max_operands 6 lat temu
aoptcpud.pas 3c2dab9878 * i386 peephole assembler uses largely the common peephole optimizer infrastructure, the resulting code is besides a few improvements the same 9 lat temu
cgcpu.pas 4da16992df * i386: Minor PIC initialization improvement if the GOT register is forced to EBX. 6 lat temu
cpubase.inc 518cdf9674 * replaced the saved_XXX_registers arrays with virtual methods inside 7 lat temu
cpuelf.pas 901275b4a1 Switch back to emitting BLX instructions and fix calculation of constant offsets(should rarely/never happen). 10 lat temu
cpuinfo.pas aec03309ef + added CPUX86_HAS_SSE2 to x86 tcpuflags 7 lat temu
cpunode.pas a0efde8167 * automatically generate necessary indirect symbols when a new assembler 9 lat temu
cpupara.pas 8b9e90dc7a * keep track of whether a routine has a C-style variadic parameter in the 6 lat temu
cpupi.pas 039aee9568 * i386 PIC: Do not force EBX as a GOT register if tf_section_threadvars is not set. Actually forcing EBX here is a bad idea anyway. 6 lat temu
cputarg.pas 4431ba2c08 merged/updated AROS/i386 target to trunk from AROS branch, to support Marcus Sackrow's work on AROS support which will hopefully benefit all Amiga-like targets (classic, MorphOS) on the long run. Compiler only, RTL comes in the next run. 11 lat temu
hlcgcpu.pas e5c2d13671 * Do not set pi_needs_got in current_procinfo.flags at the node level, since the GOT usage can only be estimated there. Instead set the pi_needs_got flag at places where the GOT register is accessed during the code generation. This eliminates generation of the unneeded initialization of the GOT register and fixes linker errors when the _GLOBAL_OFFSET_TABLE_ symbol is referenced but no actual GOT references are present. 6 lat temu
i386att.inc 4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 6 lat temu
i386atts.inc 4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 6 lat temu
i386int.inc 4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 6 lat temu
i386nop.inc 4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 6 lat temu
i386op.inc 4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 6 lat temu
i386prop.inc 4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 6 lat temu
i386tab.inc 4f0da5fcc3 + patch by Marģers to support the x86 assembler instructions blsi, blsr, blsmsk, adcx, adox, movbe, pclmulqdq, resolves #34815 and #34799 6 lat temu
n386add.pas a25ebbba3e + added volatility information to all memory references 8 lat temu
n386cal.pas f5f895e2a3 syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed 8 lat temu
n386flw.pas 91d5457b38 * moved around/replaced the following procedures to stop nflw from depending 6 lat temu
n386inl.pas aefa317474 + fast and branchless implementation of abs(int64) for i386 8 lat temu
n386ld.pas 3c6aa91a96 * factored out the loading of threadvars in its own method, and put the 10 lat temu
n386mat.pas 8c5606b41d + support mmx shifting 7 lat temu
n386mem.pas 3318703ece * moved nf_typedaddr to addrnodeflags (anf_typedaddr) 7 lat temu
n386set.pas 07bd4ba517 * let all the case code generation work with tconstexprint instead of aint, 6 lat temu
r386ari.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386att.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386con.inc 8b0bbdcaab * fix flag subregs after r38206 7 lat temu
r386dwrf.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386int.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386iri.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386nasm.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386nor.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386nri.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386num.inc 8b0bbdcaab * fix flag subregs after r38206 7 lat temu
r386ot.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386rni.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386sri.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386stab.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
r386std.inc c8487c4150 + added individual bits of the x86 flags register as subregisters 8 lat temu
ra386att.pas 757ed4e8d3 * standard assembler reader for i386 20 lat temu
ra386int.pas 6c6bf452ca * Fixed level 2 comment warnings. 17 lat temu
rgcpu.pas b7fe6797bf Merged revisions 2921-2922,2925 via svnmerge from 19 lat temu
symcpu.pas acf02ab64b * when creating wrappers, add a prefix to parameter names to prevent them 6 lat temu