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aasmcpu.pas
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e23ed15634
* MIPS: reworked and fixed procedure fixup_jmps:
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9 lat temu |
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aoptcpu.pas
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5165497498
* MIPS: fixed TCpuAsmOptimizer.InstructionLoadsFromReg, it now correctly considers instructions that read their first operand.
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8 lat temu |
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aoptcpub.pas
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9b0ff05ee8
- get rid of MaxOps, it is redundant with max_operands
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6 lat temu |
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aoptcpud.pas
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0c8546f94c
* more MIPS code of David Zhang integrated
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15 lat temu |
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cgcpu.pas
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d69ad8fa41
* removed temppos field again from parameter locations: they're not allocated
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7 lat temu |
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cpubase.pas
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92acd38f40
Fix for bug report #34380
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6 lat temu |
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cpuelf.pas
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578348817b
* MIPS: some progress with linker:
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9 lat temu |
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cpugas.pas
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74a49b5f91
* restructured the the TExternalAssembler constructors so that the
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8 lat temu |
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cpuinfo.pas
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73c46a5988
- removed unused constants
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8 lat temu |
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cpunode.pas
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a0efde8167
* automatically generate necessary indirect symbols when a new assembler
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9 lat temu |
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cpupara.pas
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8b9e90dc7a
* keep track of whether a routine has a C-style variadic parameter in the
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6 lat temu |
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cpupi.pas
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880d438704
* renamed t<cpuname>procinfo to tcpuprocinfo for all targets, so we can
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8 lat temu |
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cputarg.pas
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b2b26f84cf
* partially merged the mips-embedded branch of Michael Ring:
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11 lat temu |
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hlcgcpu.pas
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4686f61002
* keep track of the temp position separately from the offset in references,
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7 lat temu |
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itcpugas.pas
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11a9ff4a43
* Removed unused vars for mipsel compiler.
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10 lat temu |
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mipsreg.dat
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f870b0f8fc
Fix stabs number for FPU register, which start at 38 instead of 32
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8 lat temu |
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ncpuadd.pas
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11a9ff4a43
* Removed unused vars for mipsel compiler.
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10 lat temu |
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ncpucall.pas
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4c68ea1000
* use pocalls_cdecl and cstylearrayofconst more consistently instead of
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8 lat temu |
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ncpucnv.pas
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a25ebbba3e
+ added volatility information to all memory references
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8 lat temu |
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ncpuinln.pas
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4065483a50
* completed thlcgobj.location_force_fpureg(), use it everywhere and removed
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11 lat temu |
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ncpuld.pas
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4b820a1ca5
- Removed tcgloadnode.generate_picvaraccess, it is never used and is not necessary because PIC stuff is handled at lower levels.
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12 lat temu |
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ncpumat.pas
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7949bebb8d
* synchronised with r28168 of trunk
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11 lat temu |
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ncpuset.pas
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07bd4ba517
* let all the case code generation work with tconstexprint instead of aint,
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6 lat temu |
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opcode.inc
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4e7c908b0d
+ MIPS: added movn and movz instructions.
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11 lat temu |
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racpugas.pas
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1b66995754
* factored out check to determine whether a variable can be subscripted in
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7 lat temu |
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rgcpu.pas
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4686f61002
* keep track of the temp position separately from the offset in references,
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7 lat temu |
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rmipscon.inc
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 lat temu |
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rmipsdwf.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 lat temu |
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rmipsgas.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 lat temu |
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rmipsgri.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 lat temu |
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rmipsgss.inc
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f58fcdf401
+ basic mips stuff
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20 lat temu |
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rmipsnor.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 lat temu |
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rmipsnum.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 lat temu |
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rmipsrni.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 lat temu |
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rmipssri.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 lat temu |
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rmipssta.inc
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fd6d3b4971
Regenerated after change in mipsreg.dat
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8 lat temu |
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rmipsstd.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 lat temu |
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rmipssup.inc
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 lat temu |
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strinst.inc
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4e7c908b0d
+ MIPS: added movn and movz instructions.
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11 lat temu |
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symcpu.pas
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7dd1d6aa77
o fixes handling of iso i/o parameters/program parameters:
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10 lat temu |
Jonas Maebe
07bd4ba517
* let all the case code generation work with tconstexprint instead of aint,