florian ca1511b83c + RiscV: CPU type rv32imafc added 2 周之前
..
aoptcpu.pas 63c4bc29ba * cleanup 3 周之前
aoptcpub.pas 9b0ff05ee8 - get rid of MaxOps, it is redundant with max_operands 7 年之前
aoptcpuc.pas ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk. 7 年之前
aoptcpud.pas ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk. 7 年之前
cgcpu.pas b2f5f6ac7d + RiscV32: use sext.b if available 7 月之前
cpuinfo.pas ca1511b83c + RiscV: CPU type rv32imafc added 2 周之前
cpunode.pas 971d97c179 + RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0 9 月之前
cpupara.pas b7608b045b * RiscV: push_addr_param unified 9 月之前
cpupi.pas 281b3ad276 * fix case completeness and unreachable code warnings in compiler that would 6 年之前
cputarg.pas bedd4edc72 + first work for esp32-c3 support 2 年之前
hlcgcpu.pas ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk. 7 年之前
nrv32add.pas c83e6c34a9 riscv32: Fix 64bit comparisons 3 年之前
nrv32cal.pas 44150f43ac * RISC-V 32 compilation fixed 7 年之前
nrv32cnv.pas 281b3ad276 * fix case completeness and unreachable code warnings in compiler that would 6 年之前
nrv32mat.pas a291347d98 * emit_div/mod_reg_reg_reg takes now three operands 3 周之前
nrv32util.pas b4a83e29a4 * fixes RiscV32 building 9 月之前
rrv32con.inc 8d0bdf2f16 + RiscV: vector registers 9 月之前
rrv32dwa.inc 8d0bdf2f16 + RiscV: vector registers 9 月之前
rrv32nor.inc 8d0bdf2f16 + RiscV: vector registers 9 月之前
rrv32num.inc 8d0bdf2f16 + RiscV: vector registers 9 月之前
rrv32rni.inc 8d0bdf2f16 + RiscV: vector registers 9 月之前
rrv32sri.inc 8d0bdf2f16 + RiscV: vector registers 9 月之前
rrv32sta.inc 8d0bdf2f16 + RiscV: vector registers 9 月之前
rrv32std.inc 8d0bdf2f16 + RiscV: vector registers 9 月之前
rrv32sup.inc 8d0bdf2f16 + RiscV: vector registers 9 月之前
symcpu.pas ceb38833f2 Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk. 7 年之前
tripletcpu.pas eb7ba1690e * mark all external assemblers using an LLVM tool using af_llvm 5 年之前