Initial experimental support for GCRA.

tsubregister is used as the register class specifier.
The Squeeze function is not yet built into the system, and ra_resize reg allocs should probably be used.

git-svn-id: branches/laksen/gcra@29035 -

compiler/arm/armreg.dat

@@ -42,69 +42,69 @@ F7,$02,$00,$07,f7,32,23
 ; numbers to allow implementation of the "EABI VFP hardfloat" calling convention.
 
 S0,$04,$06,$00,s0,0,0
-S1,$04,$06,$20,s1,0,0
-D0,$04,$07,$00,d0,0,0
-S2,$04,$06,$01,s2,0,0
-S3,$04,$06,$21,s3,0,0
-D1,$04,$07,$01,d1,0,0
-S4,$04,$06,$02,s4,0,0
-S5,$04,$06,$22,s5,0,0
-D2,$04,$07,$02,d2,0,0
-S6,$04,$06,$03,s6,0,0
-S7,$04,$06,$23,s7,0,0
-D3,$04,$07,$03,d3,0,0
-S8,$04,$06,$04,s8,0,0
-S9,$04,$06,$24,s9,0,0
-D4,$04,$07,$04,d4,0,0
-S10,$04,$06,$05,s10,0,0
-S11,$04,$06,$25,s11,0,0
-D5,$04,$07,$05,d5,0,0
-S12,$04,$06,$06,s12,0,0
-S13,$04,$06,$26,s13,0,0
-D6,$04,$07,$06,d6,0,0
-S14,$04,$06,$07,s14,0,0
-S15,$04,$06,$27,s15,0,0
-D7,$04,$07,$07,d7,0,0
-S16,$04,$06,$08,s16,0,0
-S17,$04,$06,$28,s17,0,0
-D8,$04,$07,$08,d8,0,0
-S18,$04,$06,$09,s18,0,0
-S19,$04,$06,$29,s19,0,0
-D9,$04,$07,$09,d9,0,0
-S20,$04,$06,$0A,s20,0,0
-S21,$04,$06,$2A,s21,0,0
-D10,$04,$07,$0A,d10,0,0
-S22,$04,$06,$0B,s22,0,0
-S23,$04,$06,$2B,s23,0,0
-D11,$04,$07,$0B,d11,0,0
-S24,$04,$06,$0C,s24,0,0
-S25,$04,$06,$2C,s25,0,0
-D12,$04,$07,$0C,d12,0,0
-S26,$04,$06,$0D,s26,0,0
-S27,$04,$06,$2D,s27,0,0
-D13,$04,$07,$0D,d13,0,0
-S28,$04,$06,$0E,s28,0,0
-S29,$04,$06,$2E,s29,0,0
-D14,$04,$07,$0E,d14,0,0
-S30,$04,$06,$0F,s30,0,0
-S31,$04,$06,$2F,s21,0,0
-D15,$04,$07,$0F,d15,0,0
-D16,$04,$07,$10,d16,0,0
-D17,$04,$07,$11,d17,0,0
-D18,$04,$07,$12,d18,0,0
-D19,$04,$07,$13,d19,0,0
-D20,$04,$07,$14,d20,0,0
-D21,$04,$07,$15,d21,0,0
-D22,$04,$07,$16,d22,0,0
-D23,$04,$07,$17,d23,0,0
-D24,$04,$07,$18,d24,0,0
-D25,$04,$07,$19,d25,0,0
-D26,$04,$07,$1A,d26,0,0
-D27,$04,$07,$1B,d27,0,0
-D28,$04,$07,$1C,d28,0,0
-D29,$04,$07,$1D,d29,0,0
-D30,$04,$07,$1E,d30,0,0
-D31,$04,$07,$1F,d31,0,0
+S1,$04,$06,$01,s1,0,0
+S2,$04,$06,$02,s2,0,0
+S3,$04,$06,$03,s3,0,0
+S4,$04,$06,$04,s4,0,0
+S5,$04,$06,$05,s5,0,0
+S6,$04,$06,$06,s6,0,0
+S7,$04,$06,$07,s7,0,0
+S8,$04,$06,$08,s8,0,0
+S9,$04,$06,$09,s9,0,0
+S10,$04,$06,$0a,s10,0,0
+S11,$04,$06,$0b,s11,0,0
+S12,$04,$06,$0c,s12,0,0
+S13,$04,$06,$0d,s13,0,0
+S14,$04,$06,$0e,s14,0,0
+S15,$04,$06,$0f,s15,0,0
+S16,$04,$06,$10,s16,0,0
+S17,$04,$06,$11,s17,0,0
+S18,$04,$06,$12,s18,0,0
+S19,$04,$06,$13,s19,0,0
+S20,$04,$06,$14,s20,0,0
+S21,$04,$06,$15,s21,0,0
+S22,$04,$06,$16,s22,0,0
+S23,$04,$06,$17,s23,0,0
+S24,$04,$06,$18,s24,0,0
+S25,$04,$06,$19,s25,0,0
+S26,$04,$06,$1a,s26,0,0
+S27,$04,$06,$1b,s27,0,0
+S28,$04,$06,$1c,s28,0,0
+S29,$04,$06,$1d,s29,0,0
+S30,$04,$06,$1e,s30,0,0
+S31,$04,$06,$1f,s31,0,0
+D0,$04,$07,$20,D0,0,0
+D1,$04,$07,$21,D1,0,0
+D2,$04,$07,$22,D2,0,0
+D3,$04,$07,$23,D3,0,0
+D4,$04,$07,$24,D4,0,0
+D5,$04,$07,$25,D5,0,0
+D6,$04,$07,$26,D6,0,0
+D7,$04,$07,$27,D7,0,0
+D8,$04,$07,$28,D8,0,0
+D9,$04,$07,$29,D9,0,0
+D10,$04,$07,$2a,D10,0,0
+D11,$04,$07,$2b,D11,0,0
+D12,$04,$07,$2c,D12,0,0
+D13,$04,$07,$2d,D13,0,0
+D14,$04,$07,$2e,D14,0,0
+D15,$04,$07,$2f,D15,0,0
+D16,$04,$07,$30,D16,0,0
+D17,$04,$07,$31,D17,0,0
+D18,$04,$07,$32,D18,0,0
+D19,$04,$07,$33,D19,0,0
+D20,$04,$07,$34,D20,0,0
+D21,$04,$07,$35,D21,0,0
+D22,$04,$07,$36,D22,0,0
+D23,$04,$07,$37,D23,0,0
+D24,$04,$07,$38,D24,0,0
+D25,$04,$07,$39,D25,0,0
+D26,$04,$07,$3a,D26,0,0
+D27,$04,$07,$3b,D27,0,0
+D28,$04,$07,$3c,D28,0,0
+D29,$04,$07,$3d,D29,0,0
+D30,$04,$07,$3e,D30,0,0
+D31,$04,$07,$3f,D31,0,0
 
 ; special registers
 CPSR,$05,$00,$00,cpsr,0,0

compiler/arm/cgcpu.pas

@@ -267,6 +267,8 @@ unit cgcpu;
 
 
     procedure tarmcgarm.init_register_allocators;
+      var
+        r: tsuperregister;
       begin
         inherited init_register_allocators;
         { currently, we always save R14, so we can use it }
@@ -288,8 +290,14 @@ unit cgcpu;
           rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
               [RS_R0,RS_R1,RS_R2,RS_R3,RS_R9,RS_R12,RS_R4,RS_R5,RS_R6,RS_R8,
                RS_R10,RS_R11,RS_R14],first_int_imreg,[]);
+
+        rg[R_INTREGISTER].define_class(R_SUBWHOLE,[RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15]);
+
         rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
             [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]);
+
+        rg[R_FPUREGISTER].define_class(R_SUBNONE,[RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7]);
+
         { The register allocator currently cannot deal with multiple
           non-overlapping subregs per register, so we can only use
           half the single precision registers for now (as sub registers of the
@@ -297,12 +305,32 @@ unit cgcpu;
         if current_settings.fputype=fpu_vfpv3 then
           rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD,
               [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,
+               RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15,
                RS_D16,RS_D17,RS_D18,RS_D19,RS_D20,RS_D21,RS_D22,RS_D23,RS_D24,RS_D25,RS_D26,RS_D27,RS_D28,RS_D29,RS_D30,RS_D31,
-               RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15
+               RS_S0,RS_S1,RS_S2,RS_S3,RS_S4,RS_S5,RS_S6,RS_S7,
+               RS_S8,RS_S9,RS_S10,RS_S11,RS_S12,RS_S13,RS_S14,RS_S15,
+               RS_S16,RS_S17,RS_S18,RS_S19,RS_S20,RS_S21,RS_S22,RS_S23,
+               RS_S24,RS_S25,RS_S26,RS_S27,RS_S28,RS_S29,RS_S30,RS_S31
               ],first_mm_imreg,[])
         else
           rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD,
               [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15],first_mm_imreg,[]);
+
+        rg[R_MMREGISTER].define_class(R_SUBFD,[RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,
+                                               RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15,
+                                               RS_D16,RS_D17,RS_D18,RS_D19,RS_D20,RS_D21,RS_D22,RS_D23,
+                                               RS_D24,RS_D25,RS_D26,RS_D27,RS_D28,RS_D29,RS_D30,RS_D31]);
+
+        for r:=RS_D0 to RS_D15 do
+          rg[R_MMREGISTER].define_alias(r,[RS_S0+(r-RS_D0)*2,RS_S1+(r-RS_D0)*2]);
+
+        rg[R_MMREGISTER].define_class(R_SUBFS,[RS_S0,RS_S1,RS_S2,RS_S3,RS_S4,RS_S5,RS_S6,RS_S7,
+                                               RS_S8,RS_S9,RS_S10,RS_S11,RS_S12,RS_S13,RS_S14,RS_S15,
+                                               RS_S16,RS_S17,RS_S18,RS_S19,RS_S20,RS_S21,RS_S22,RS_S23,
+                                               RS_S24,RS_S25,RS_S26,RS_S27,RS_S28,RS_S29,RS_S30,RS_S31]);
+
+        for r:=RS_S0 to RS_S15 do
+          rg[R_MMREGISTER].define_alias(r,[RS_D0+((r-RS_S0) div 2)]);
       end;
 
 

compiler/arm/cpubase.pas

@@ -90,7 +90,7 @@ unit cpubase;
 
       { MM Super register first and last }
       first_mm_supreg    = RS_S0;
-      first_mm_imreg     = $30;
+      first_mm_imreg     = $40;
 
 { TODO: Calculate bsstart}
       regnumber_count_bsstart = 64;

compiler/arm/rarmcon.inc

@@ -25,69 +25,69 @@ NR_F5 = tregister($02000005);
 NR_F6 = tregister($02000006);
 NR_F7 = tregister($02000007);
 NR_S0 = tregister($04060000);
-NR_S1 = tregister($04060020);
-NR_D0 = tregister($04070000);
-NR_S2 = tregister($04060001);
-NR_S3 = tregister($04060021);
-NR_D1 = tregister($04070001);
-NR_S4 = tregister($04060002);
-NR_S5 = tregister($04060022);
-NR_D2 = tregister($04070002);
-NR_S6 = tregister($04060003);
-NR_S7 = tregister($04060023);
-NR_D3 = tregister($04070003);
-NR_S8 = tregister($04060004);
-NR_S9 = tregister($04060024);
-NR_D4 = tregister($04070004);
-NR_S10 = tregister($04060005);
-NR_S11 = tregister($04060025);
-NR_D5 = tregister($04070005);
-NR_S12 = tregister($04060006);
-NR_S13 = tregister($04060026);
-NR_D6 = tregister($04070006);
-NR_S14 = tregister($04060007);
-NR_S15 = tregister($04060027);
-NR_D7 = tregister($04070007);
-NR_S16 = tregister($04060008);
-NR_S17 = tregister($04060028);
-NR_D8 = tregister($04070008);
-NR_S18 = tregister($04060009);
-NR_S19 = tregister($04060029);
-NR_D9 = tregister($04070009);
-NR_S20 = tregister($0406000A);
-NR_S21 = tregister($0406002A);
-NR_D10 = tregister($0407000A);
-NR_S22 = tregister($0406000B);
-NR_S23 = tregister($0406002B);
-NR_D11 = tregister($0407000B);
-NR_S24 = tregister($0406000C);
-NR_S25 = tregister($0406002C);
-NR_D12 = tregister($0407000C);
-NR_S26 = tregister($0406000D);
-NR_S27 = tregister($0406002D);
-NR_D13 = tregister($0407000D);
-NR_S28 = tregister($0406000E);
-NR_S29 = tregister($0406002E);
-NR_D14 = tregister($0407000E);
-NR_S30 = tregister($0406000F);
-NR_S31 = tregister($0406002F);
-NR_D15 = tregister($0407000F);
-NR_D16 = tregister($04070010);
-NR_D17 = tregister($04070011);
-NR_D18 = tregister($04070012);
-NR_D19 = tregister($04070013);
-NR_D20 = tregister($04070014);
-NR_D21 = tregister($04070015);
-NR_D22 = tregister($04070016);
-NR_D23 = tregister($04070017);
-NR_D24 = tregister($04070018);
-NR_D25 = tregister($04070019);
-NR_D26 = tregister($0407001A);
-NR_D27 = tregister($0407001B);
-NR_D28 = tregister($0407001C);
-NR_D29 = tregister($0407001D);
-NR_D30 = tregister($0407001E);
-NR_D31 = tregister($0407001F);
+NR_S1 = tregister($04060001);
+NR_S2 = tregister($04060002);
+NR_S3 = tregister($04060003);
+NR_S4 = tregister($04060004);
+NR_S5 = tregister($04060005);
+NR_S6 = tregister($04060006);
+NR_S7 = tregister($04060007);
+NR_S8 = tregister($04060008);
+NR_S9 = tregister($04060009);
+NR_S10 = tregister($0406000a);
+NR_S11 = tregister($0406000b);
+NR_S12 = tregister($0406000c);
+NR_S13 = tregister($0406000d);
+NR_S14 = tregister($0406000e);
+NR_S15 = tregister($0406000f);
+NR_S16 = tregister($04060010);
+NR_S17 = tregister($04060011);
+NR_S18 = tregister($04060012);
+NR_S19 = tregister($04060013);
+NR_S20 = tregister($04060014);
+NR_S21 = tregister($04060015);
+NR_S22 = tregister($04060016);
+NR_S23 = tregister($04060017);
+NR_S24 = tregister($04060018);
+NR_S25 = tregister($04060019);
+NR_S26 = tregister($0406001a);
+NR_S27 = tregister($0406001b);
+NR_S28 = tregister($0406001c);
+NR_S29 = tregister($0406001d);
+NR_S30 = tregister($0406001e);
+NR_S31 = tregister($0406001f);
+NR_D0 = tregister($04070020);
+NR_D1 = tregister($04070021);
+NR_D2 = tregister($04070022);
+NR_D3 = tregister($04070023);
+NR_D4 = tregister($04070024);
+NR_D5 = tregister($04070025);
+NR_D6 = tregister($04070026);
+NR_D7 = tregister($04070027);
+NR_D8 = tregister($04070028);
+NR_D9 = tregister($04070029);
+NR_D10 = tregister($0407002a);
+NR_D11 = tregister($0407002b);
+NR_D12 = tregister($0407002c);
+NR_D13 = tregister($0407002d);
+NR_D14 = tregister($0407002e);
+NR_D15 = tregister($0407002f);
+NR_D16 = tregister($04070030);
+NR_D17 = tregister($04070031);
+NR_D18 = tregister($04070032);
+NR_D19 = tregister($04070033);
+NR_D20 = tregister($04070034);
+NR_D21 = tregister($04070035);
+NR_D22 = tregister($04070036);
+NR_D23 = tregister($04070037);
+NR_D24 = tregister($04070038);
+NR_D25 = tregister($04070039);
+NR_D26 = tregister($0407003a);
+NR_D27 = tregister($0407003b);
+NR_D28 = tregister($0407003c);
+NR_D29 = tregister($0407003d);
+NR_D30 = tregister($0407003e);
+NR_D31 = tregister($0407003f);
 NR_CPSR = tregister($05000000);
 NR_FPSCR = tregister($05000001);
 NR_SPSR = tregister($05000002);

compiler/arm/rarmnum.inc

@@ -25,69 +25,69 @@ tregister($02000005),
 tregister($02000006),
 tregister($02000007),
 tregister($04060000),
-tregister($04060020),
-tregister($04070000),
 tregister($04060001),
-tregister($04060021),
-tregister($04070001),
 tregister($04060002),
-tregister($04060022),
-tregister($04070002),
 tregister($04060003),
-tregister($04060023),
-tregister($04070003),
 tregister($04060004),
-tregister($04060024),
-tregister($04070004),
 tregister($04060005),
-tregister($04060025),
-tregister($04070005),
 tregister($04060006),
-tregister($04060026),
-tregister($04070006),
 tregister($04060007),
-tregister($04060027),
-tregister($04070007),
 tregister($04060008),
-tregister($04060028),
-tregister($04070008),
 tregister($04060009),
-tregister($04060029),
-tregister($04070009),
-tregister($0406000A),
-tregister($0406002A),
-tregister($0407000A),
-tregister($0406000B),
-tregister($0406002B),
-tregister($0407000B),
-tregister($0406000C),
-tregister($0406002C),
-tregister($0407000C),
-tregister($0406000D),
-tregister($0406002D),
-tregister($0407000D),
-tregister($0406000E),
-tregister($0406002E),
-tregister($0407000E),
-tregister($0406000F),
-tregister($0406002F),
-tregister($0407000F),
-tregister($04070010),
-tregister($04070011),
-tregister($04070012),
-tregister($04070013),
-tregister($04070014),
-tregister($04070015),
-tregister($04070016),
-tregister($04070017),
-tregister($04070018),
-tregister($04070019),
-tregister($0407001A),
-tregister($0407001B),
-tregister($0407001C),
-tregister($0407001D),
-tregister($0407001E),
-tregister($0407001F),
+tregister($0406000a),
+tregister($0406000b),
+tregister($0406000c),
+tregister($0406000d),
+tregister($0406000e),
+tregister($0406000f),
+tregister($04060010),
+tregister($04060011),
+tregister($04060012),
+tregister($04060013),
+tregister($04060014),
+tregister($04060015),
+tregister($04060016),
+tregister($04060017),
+tregister($04060018),
+tregister($04060019),
+tregister($0406001a),
+tregister($0406001b),
+tregister($0406001c),
+tregister($0406001d),
+tregister($0406001e),
+tregister($0406001f),
+tregister($04070020),
+tregister($04070021),
+tregister($04070022),
+tregister($04070023),
+tregister($04070024),
+tregister($04070025),
+tregister($04070026),
+tregister($04070027),
+tregister($04070028),
+tregister($04070029),
+tregister($0407002a),
+tregister($0407002b),
+tregister($0407002c),
+tregister($0407002d),
+tregister($0407002e),
+tregister($0407002f),
+tregister($04070030),
+tregister($04070031),
+tregister($04070032),
+tregister($04070033),
+tregister($04070034),
+tregister($04070035),
+tregister($04070036),
+tregister($04070037),
+tregister($04070038),
+tregister($04070039),
+tregister($0407003a),
+tregister($0407003b),
+tregister($0407003c),
+tregister($0407003d),
+tregister($0407003e),
+tregister($0407003f),
 tregister($05000000),
 tregister($05000001),
 tregister($05000002),

compiler/arm/rarmrni.inc

@@ -25,52 +25,52 @@
 23,
 24,
 25,
-28,
-31,
-34,
-37,
-40,
-43,
-46,
-49,
-52,
-55,
-58,
-61,
-64,
-67,
-70,
 26,
-29,
-32,
-35,
-38,
-41,
-44,
-47,
-50,
-53,
-56,
-59,
-62,
-65,
-68,
-71,
 27,
+28,
+29,
 30,
+31,
+32,
 33,
+34,
+35,
 36,
+37,
+38,
 39,
+40,
+41,
 42,
+43,
+44,
 45,
+46,
+47,
 48,
+49,
+50,
 51,
+52,
+53,
 54,
+55,
+56,
 57,
+58,
+59,
 60,
+61,
+62,
 63,
+64,
+65,
 66,
+67,
+68,
 69,
+70,
+71,
 72,
 73,
 74,

compiler/arm/rarmsri.inc

@@ -1,4 +1,36 @@
 { don't edit, this file is generated from armreg.dat }
+57,
+58,
+67,
+68,
+69,
+70,
+71,
+72,
+73,
+74,
+75,
+76,
+59,
+77,
+78,
+79,
+80,
+81,
+82,
+83,
+84,
+85,
+86,
+60,
+87,
+88,
+61,
+62,
+63,
+64,
+65,
+66,
 0,
 110,
 92,
@@ -22,38 +54,6 @@
 100,
 101,
 102,
-27,
-30,
-57,
-60,
-63,
-66,
-69,
-72,
-73,
-74,
-75,
-76,
-33,
-77,
-78,
-79,
-80,
-81,
-82,
-83,
-84,
-85,
-86,
-36,
-87,
-88,
-39,
-42,
-45,
-48,
-51,
-54,
 115,
 112,
 17,
@@ -92,34 +92,34 @@
 10,
 25,
 26,
+35,
+36,
+37,
+38,
+39,
 40,
 41,
+42,
 43,
 44,
+27,
+45,
 46,
 47,
+48,
 49,
 50,
+51,
 52,
 53,
+54,
 28,
 55,
-71,
 56,
-58,
-59,
-61,
-62,
-64,
-65,
-67,
-68,
 29,
-70,
+30,
 31,
 32,
+33,
 34,
-35,
-37,
-38,
 91

compiler/arm/rarmstd.inc

@@ -26,68 +26,68 @@
 'f7',
 's0',
 's1',
-'d0',
 's2',
 's3',
-'d1',
 's4',
 's5',
-'d2',
 's6',
 's7',
-'d3',
 's8',
 's9',
-'d4',
 's10',
 's11',
-'d5',
 's12',
 's13',
-'d6',
 's14',
 's15',
-'d7',
 's16',
 's17',
-'d8',
 's18',
 's19',
-'d9',
 's20',
 's21',
-'d10',
 's22',
 's23',
-'d11',
 's24',
 's25',
-'d12',
 's26',
 's27',
-'d13',
 's28',
 's29',
-'d14',
 's30',
-'s21',
-'d15',
-'d16',
-'d17',
-'d18',
-'d19',
-'d20',
-'d21',
-'d22',
-'d23',
-'d24',
-'d25',
-'d26',
-'d27',
-'d28',
-'d29',
-'d30',
-'d31',
+'s31',
+'D0',
+'D1',
+'D2',
+'D3',
+'D4',
+'D5',
+'D6',
+'D7',
+'D8',
+'D9',
+'D10',
+'D11',
+'D12',
+'D13',
+'D14',
+'D15',
+'D16',
+'D17',
+'D18',
+'D19',
+'D20',
+'D21',
+'D22',
+'D23',
+'D24',
+'D25',
+'D26',
+'D27',
+'D28',
+'D29',
+'D30',
+'D31',
 'cpsr',
 'fpscr',
 'spsr',

compiler/arm/rarmsup.inc

@@ -25,69 +25,69 @@ RS_F5 = $05;
 RS_F6 = $06;
 RS_F7 = $07;
 RS_S0 = $00;
-RS_S1 = $20;
-RS_D0 = $00;
-RS_S2 = $01;
-RS_S3 = $21;
-RS_D1 = $01;
-RS_S4 = $02;
-RS_S5 = $22;
-RS_D2 = $02;
-RS_S6 = $03;
-RS_S7 = $23;
-RS_D3 = $03;
-RS_S8 = $04;
-RS_S9 = $24;
-RS_D4 = $04;
-RS_S10 = $05;
-RS_S11 = $25;
-RS_D5 = $05;
-RS_S12 = $06;
-RS_S13 = $26;
-RS_D6 = $06;
-RS_S14 = $07;
-RS_S15 = $27;
-RS_D7 = $07;
-RS_S16 = $08;
-RS_S17 = $28;
-RS_D8 = $08;
-RS_S18 = $09;
-RS_S19 = $29;
-RS_D9 = $09;
-RS_S20 = $0A;
-RS_S21 = $2A;
-RS_D10 = $0A;
-RS_S22 = $0B;
-RS_S23 = $2B;
-RS_D11 = $0B;
-RS_S24 = $0C;
-RS_S25 = $2C;
-RS_D12 = $0C;
-RS_S26 = $0D;
-RS_S27 = $2D;
-RS_D13 = $0D;
-RS_S28 = $0E;
-RS_S29 = $2E;
-RS_D14 = $0E;
-RS_S30 = $0F;
-RS_S31 = $2F;
-RS_D15 = $0F;
-RS_D16 = $10;
-RS_D17 = $11;
-RS_D18 = $12;
-RS_D19 = $13;
-RS_D20 = $14;
-RS_D21 = $15;
-RS_D22 = $16;
-RS_D23 = $17;
-RS_D24 = $18;
-RS_D25 = $19;
-RS_D26 = $1A;
-RS_D27 = $1B;
-RS_D28 = $1C;
-RS_D29 = $1D;
-RS_D30 = $1E;
-RS_D31 = $1F;
+RS_S1 = $01;
+RS_S2 = $02;
+RS_S3 = $03;
+RS_S4 = $04;
+RS_S5 = $05;
+RS_S6 = $06;
+RS_S7 = $07;
+RS_S8 = $08;
+RS_S9 = $09;
+RS_S10 = $0a;
+RS_S11 = $0b;
+RS_S12 = $0c;
+RS_S13 = $0d;
+RS_S14 = $0e;
+RS_S15 = $0f;
+RS_S16 = $10;
+RS_S17 = $11;
+RS_S18 = $12;
+RS_S19 = $13;
+RS_S20 = $14;
+RS_S21 = $15;
+RS_S22 = $16;
+RS_S23 = $17;
+RS_S24 = $18;
+RS_S25 = $19;
+RS_S26 = $1a;
+RS_S27 = $1b;
+RS_S28 = $1c;
+RS_S29 = $1d;
+RS_S30 = $1e;
+RS_S31 = $1f;
+RS_D0 = $20;
+RS_D1 = $21;
+RS_D2 = $22;
+RS_D3 = $23;
+RS_D4 = $24;
+RS_D5 = $25;
+RS_D6 = $26;
+RS_D7 = $27;
+RS_D8 = $28;
+RS_D9 = $29;
+RS_D10 = $2a;
+RS_D11 = $2b;
+RS_D12 = $2c;
+RS_D13 = $2d;
+RS_D14 = $2e;
+RS_D15 = $2f;
+RS_D16 = $30;
+RS_D17 = $31;
+RS_D18 = $32;
+RS_D19 = $33;
+RS_D20 = $34;
+RS_D21 = $35;
+RS_D22 = $36;
+RS_D23 = $37;
+RS_D24 = $38;
+RS_D25 = $39;
+RS_D26 = $3a;
+RS_D27 = $3b;
+RS_D28 = $3c;
+RS_D29 = $3d;
+RS_D30 = $3e;
+RS_D31 = $3f;
 RS_CPSR = $00;
 RS_FPSCR = $01;
 RS_SPSR = $02;

compiler/arm/rgcpu.pas

@@ -338,19 +338,7 @@ unit rgcpu;
 
 
     procedure trgcpu.add_constraints(reg:tregister);
-      var
-        supreg,i : Tsuperregister;
       begin
-        case getsubreg(reg) of
-          { Let 32bit floats conflict with all double precision regs > 15
-            (since these don't have 32 bit equivalents) }
-          R_SUBFS:
-            begin
-              supreg:=getsupreg(reg);
-              for i:=RS_D16 to RS_D31 do
-                add_edge(supreg,i);
-            end;
-        end;
       end;
 
 

compiler/i386/cgcpu.pas

@@ -93,8 +93,50 @@ unit cgcpu;
             rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,[RS_EAX,RS_EDX,RS_ECX,RS_EBX,RS_ESI,RS_EDI,RS_EBP],first_int_imreg,[])
           else
             rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,[RS_EAX,RS_EDX,RS_ECX,RS_EBX,RS_ESI,RS_EDI],first_int_imreg,[RS_EBP]);
+
+        rg[R_INTREGISTER].define_class(R_SUBD,[RS_EAX,RS_EDX,RS_ECX,RS_EBX,RS_ESI,RS_EDI,RS_EBP]);
+        rg[R_INTREGISTER].define_class(R_SUBW,[RS_AX,RS_DX,RS_CX,RS_BX,RS_DI,RS_SI,RS_BP]);
+        rg[R_INTREGISTER].define_class(R_SUBL,[RS_AL,RS_DL,RS_CL,RS_BL]);
+        rg[R_INTREGISTER].define_class(R_SUBH,[RS_AH,RS_DH,RS_CH,RS_BH]);
+
+        rg[R_INTREGISTER].define_alias(RS_EAX,[RS_AX,RS_AL,RS_AH]);
+        rg[R_INTREGISTER].define_alias(RS_EDX,[RS_DX,RS_DL,RS_DH]);
+        rg[R_INTREGISTER].define_alias(RS_ECX,[RS_CX,RS_CL,RS_CH]);
+        rg[R_INTREGISTER].define_alias(RS_EBX,[RS_BX,RS_BL,RS_BH]);
+
+        rg[R_INTREGISTER].define_alias(RS_AX,[RS_EAX,RS_AL,RS_AH]);
+        rg[R_INTREGISTER].define_alias(RS_DX,[RS_EDX,RS_DL,RS_DH]);
+        rg[R_INTREGISTER].define_alias(RS_CX,[RS_ECX,RS_CL,RS_CH]);
+        rg[R_INTREGISTER].define_alias(RS_BX,[RS_EBX,RS_BL,RS_BH]);
+
+        rg[R_INTREGISTER].define_alias(RS_AL,[RS_EAX,RS_AX,RS_AH]);
+        rg[R_INTREGISTER].define_alias(RS_DL,[RS_EDX,RS_DX,RS_DH]);
+        rg[R_INTREGISTER].define_alias(RS_CL,[RS_ECX,RS_CX,RS_CH]);
+        rg[R_INTREGISTER].define_alias(RS_BL,[RS_EBX,RS_BX,RS_BH]);
+
+        rg[R_INTREGISTER].define_alias(RS_AH,[RS_EAX,RS_AL,RS_AX]);
+        rg[R_INTREGISTER].define_alias(RS_DH,[RS_EDX,RS_DL,RS_DX]);
+        rg[R_INTREGISTER].define_alias(RS_CH,[RS_ECX,RS_CL,RS_CX]);
+        rg[R_INTREGISTER].define_alias(RS_BH,[RS_EBX,RS_BL,RS_BX]);
+
+        rg[R_INTREGISTER].define_alias(RS_EDI,[RS_DI]);
+        rg[R_INTREGISTER].define_alias(RS_DI,[RS_EDI]);
+
+        rg[R_INTREGISTER].define_alias(RS_ESI,[RS_SI]);
+        rg[R_INTREGISTER].define_alias(RS_SI,[RS_ESI]);
+
+        rg[R_INTREGISTER].define_alias(RS_ESP,[RS_SP]);
+        rg[R_INTREGISTER].define_alias(RS_SP,[RS_ESP]);
+
+        rg[R_INTREGISTER].define_alias(RS_EBP,[RS_BP]);
+        rg[R_INTREGISTER].define_alias(RS_BP,[RS_EBP]);
+
         rg[R_MMXREGISTER]:=trgcpu.create(R_MMXREGISTER,R_SUBNONE,[RS_XMM0,RS_XMM1,RS_XMM2,RS_XMM3,RS_XMM4,RS_XMM5,RS_XMM6,RS_XMM7],first_mm_imreg,[]);
+        rg[R_MMXREGISTER].define_class(R_SUBNONE,[RS_XMM0,RS_XMM1,RS_XMM2,RS_XMM3,RS_XMM4,RS_XMM5,RS_XMM6,RS_XMM7]);
+
         rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBWHOLE,[RS_XMM0,RS_XMM1,RS_XMM2,RS_XMM3,RS_XMM4,RS_XMM5,RS_XMM6,RS_XMM7],first_mm_imreg,[]);
+        rg[R_MMREGISTER].define_class(R_SUBWHOLE,[RS_XMM0,RS_XMM1,RS_XMM2,RS_XMM3,RS_XMM4,RS_XMM5,RS_XMM6,RS_XMM7]);
+
         rgfpu:=Trgx86fpu.create;
       end;
 

compiler/rgobj.pas

@@ -24,7 +24,6 @@
 { Allow duplicate allocations, can be used to get the .s file written }
 { $define ALLOWDUPREG}
 
-
 unit rgobj;
 
   interface
@@ -128,6 +127,9 @@ unit rgobj;
       by cpu-specific implementations.
 
       --------------------------------------------------------------------}
+
+       { trgobj }
+
        trgobj=class
         preserved_by_proc : tcpuregisterset;
         used_in_proc : tcpuregisterset;
@@ -139,6 +141,9 @@ unit rgobj;
                            Apreserved_by_proc:Tcpuregisterset);
         destructor destroy;override;
 
+        procedure define_class(asubclass:TSubRegister;const Aregs:array of TSuperRegister);
+        procedure define_alias(aregister:TSuperRegister;const Aregs:array of TSuperRegister);
+
         { Allocate a register. An internalerror will be generated if there is
          no more free registers which can be allocated.}
         function getregister(list:TAsmList;subreg:Tsubregister):Tregister;virtual;
@@ -171,6 +176,8 @@ unit rgobj;
         { can be overridden to add cpu specific interferences }
         procedure add_cpu_interferences(p : tai);virtual;
         procedure add_constraints(reg:Tregister);virtual;
+        procedure add_class_constraints(reg:Tregister);
+        procedure add_alias_constraints(reg:Tregister);
         function  getregisterinline(list:TAsmList;const subregconstraints:Tsubregisterset):Tregister;
         procedure ungetregisterinline(list:TAsmList;r:Tregister);
         function  get_spill_subreg(r : tregister) : tsubregister;virtual;
@@ -192,6 +199,13 @@ unit rgobj;
         usable_registers_cnt : word;
         usable_registers  : array[0..maxcpuregister] of tsuperregister;
         usable_register_set : tcpuregisterset;
+
+        alias_registers_cnt : word;
+        alias_register_def  : array[0..maxcpuregister] of tsuperregister;
+        alias_registers     : array[0..maxcpuregister] of tsuperregisterset;
+
+        reg_class           : array[TSubRegister] of tsuperregisterset;
+
         ibitmap           : Tinterferencebitmap;
         spillednodes,
         simplifyworklist,
@@ -217,6 +231,7 @@ unit rgobj;
         procedure colour_registers;
         procedure insert_regalloc_info(list:TAsmList;u:tsuperregister);
         procedure generate_interference_graph(list:TAsmList;headertai:tai);
+        function squeeze(n_class, S_class: TSubRegister): longint;
         { translates the registers in the given assembler list }
         procedure translate_registers(list:TAsmList);
         function  spill_registers(list:TAsmList;headertai:tai):boolean;virtual;
@@ -248,6 +263,8 @@ unit rgobj;
         procedure writegraph(loopidx:longint);
 {$endif EXTDEBUG}
         procedure combine(u,v:Tsuperregister);
+
+        function reg_count(subreg:TSubRegister):integer;
         { set v as an alias for u }
         procedure set_alias(u,v:Tsuperregister);
         function  get_alias(n:Tsuperregister):Tsuperregister;
@@ -437,25 +454,45 @@ unit rgobj;
       backwards_was_first.free;
     end;
 
-    procedure Trgobj.dispose_reginfo;
+    procedure trgobj.define_class(asubclass: TSubRegister; const Aregs: array of TSuperRegister);
+      var
+        reg: TSuperRegister;
+      begin
+        supregset_reset(reg_class[asubclass],false,first_imaginary);
 
-    var i:cardinal;
+        for reg in aregs do
+          supregset_include(reg_class[asubclass],reg);
+      end;
 
-    begin
-      if reginfo<>nil then
-        begin
-          for i:=0 to maxreg-1 do
-            with reginfo[i] do
-              begin
-                if adjlist<>nil then
-                  dispose(adjlist,done);
-                if movelist<>nil then
-                  dispose(movelist);
-              end;
-          freemem(reginfo);
-          reginfo:=nil;
-        end;
-    end;
+    procedure trgobj.define_alias(aregister: TSuperRegister; const Aregs: array of TSuperRegister);
+      var
+        reg: TSuperRegister;
+      begin
+        alias_register_def[aregister]:=aregister;
+        supregset_reset(alias_registers[aregister],false,first_imaginary);
+        for reg in aregs do
+          supregset_include(alias_registers[aregister],reg);
+        inc(alias_registers_cnt);
+      end;
+
+    procedure trgobj.dispose_reginfo;
+      var
+        i:cardinal;
+      begin
+        if reginfo<>nil then
+          begin
+            for i:=0 to maxreg-1 do
+              with reginfo[i] do
+                begin
+                  if adjlist<>nil then
+                    dispose(adjlist,done);
+                  if movelist<>nil then
+                    dispose(movelist);
+                end;
+            freemem(reginfo);
+            reginfo:=nil;
+          end;
+      end;
 
     function trgobj.getnewreg(subreg:tsubregister):tsuperregister;
       var
@@ -595,9 +632,37 @@ unit rgobj;
 
 
     procedure trgobj.add_constraints(reg:Tregister);
+      begin
+      end;
 
-    begin
-    end;
+
+    procedure trgobj.add_class_constraints(reg: Tregister);
+      var
+        supreg: TSuperRegister;
+        subreg: TSubRegister;
+      begin
+        {subreg:=getsubreg(reg);
+        for supreg:=0 to first_imaginary-1 do
+          if not supregset_in(reg_class[subreg],supreg) then
+            add_edge(supreg,getsupreg(reg));}
+      end;
+
+
+    procedure trgobj.add_alias_constraints(reg: Tregister);
+      var
+        r,supreg: TSuperRegister;
+        subreg: TSubRegister;
+      begin
+        add_class_constraints(reg);
+
+        subreg:=getsubreg(reg);
+
+        {for supreg:=0 to first_imaginary-1 do
+          if supregset_in(reg_class[subreg],supreg) then
+            for r:=0 to first_imaginary-1 do
+              if supregset_in(alias_registers[supreg],r) then
+                add_edge(supreg,r);}
+      end;
 
 
     procedure trgobj.add_edge(u,v:Tsuperregister);
@@ -803,7 +868,7 @@ unit rgobj;
       end;
 
 
-    procedure trgobj.add_move_instruction(instr:Taicpu);
+  procedure trgobj.add_move_instruction(instr:Taicpu);
 
     {This procedure notifies a certain as a move instruction so the
      register allocator can try to eliminate it.}
@@ -838,7 +903,7 @@ unit rgobj;
       i.y:=dsupreg;
     end;
 
-    function trgobj.move_related(n:Tsuperregister):boolean;
+  function trgobj.move_related(n:Tsuperregister):boolean;
 
     var i:cardinal;
 
@@ -855,7 +920,7 @@ unit rgobj;
                 end;
     end;
 
-    procedure Trgobj.sort_simplify_worklist;
+  procedure trgobj.sort_simplify_worklist;
 
     {Sorts the simplifyworklist by the number of interferences the
      registers in it cause. This allows simplify to execute in
@@ -900,9 +965,37 @@ unit rgobj;
         end;
     end;
 
-    procedure trgobj.make_work_list;
+
+  function trgobj.squeeze(n_class,S_class:TSubRegister):longint;
+    var
+      r,r2:tsuperregister;
+      rs:tsuperregisterset;
+      t:integer;
+    begin
+      result:=0;
+
+      rs:=reg_class[n_class];
+
+      for r:=0 to usable_registers_cnt-1 do
+        if supregset_in(reg_class[S_class],r) then
+          begin
+            t:=0;
+            for r2:=0 to usable_registers_cnt-1 do
+              if supregset_in(alias_registers[r],r2) then
+                supregset_exclude(rs,r2);
+
+            for r2:=0 to usable_registers_cnt-1 do
+              if supregset_in(rs,r2) then
+                inc(t);
+
+            result:=max(result,t);
+          end;
+    end;
+
+  procedure trgobj.make_work_list;
 
     var n:cardinal;
+      i: Integer;
 
     begin
       {If we have 7 cpu registers, and the degree of a node is 7, we cannot
@@ -913,8 +1006,16 @@ unit rgobj;
             if adjlist=nil then
               degree:=0
             else
-              degree:=adjlist^.length;
-            if degree>=usable_registers_cnt then
+              begin
+                //degree:=adjlist^.length;
+                degree:=0;
+                for i:=0 to adjlist^.length-1 do
+                  begin
+                    degree:=max(degree,
+                      squeeze(reginfo[n].subreg,reginfo[adjlist^.buf^[i]].subreg));
+                  end;
+              end;
+            if degree>=reg_count(reginfo[n].subreg) then
               spillworklist.add(n)
             else if move_related(n) then
               freezeworklist.add(n)
@@ -957,7 +1058,7 @@ unit rgobj;
           end;
     end;
 
-    procedure Trgobj.decrement_degree(m:Tsuperregister);
+  procedure trgobj.decrement_degree(m: Tsuperregister);
 
     var adj : Psuperregisterworklist;
         n : tsuperregister;
@@ -966,11 +1067,22 @@ unit rgobj;
     begin
       with reginfo[m] do
         begin
-          d:=degree;
+          {d:=degree;
           if d=0 then
             internalerror(200312151);
-          dec(degree);
-          if d=usable_registers_cnt then
+          dec(degree);}
+
+          //degree:=0;
+
+          if assigned(adjlist) then
+            for i:=0 to adjlist^.length-1 do
+              begin
+                degree:=max(degree,
+                  squeeze(reginfo[m].subreg,reginfo[adjlist^.buf^[i]].subreg));
+              end;
+          d:=degree;
+
+          if d=reg_count(subreg) then
             begin
               {Enable moves for m.}
               enable_moves(m);
@@ -1035,7 +1147,7 @@ unit rgobj;
       begin
         if (u>=first_imaginary) and
            (not move_related(u)) and
-           (reginfo[u].degree<usable_registers_cnt) then
+           (reginfo[u].degree<reg_count(reginfo[u].subreg)) then
           begin
             if not freezeworklist.delete(u) then
               internalerror(200308161); {must be found}
@@ -1054,7 +1166,7 @@ unit rgobj;
         ok:=(t<first_imaginary) or
             // disabled for now, see issue #22405
             // ((r<first_imaginary) and (r in usable_register_set)) or
-            (reginfo[t].degree<usable_registers_cnt) or
+            (reginfo[t].degree<reg_count(reginfo[t].subreg)) or
             ibitmap[r,t];
       end;
 
@@ -1080,7 +1192,7 @@ unit rgobj;
         end;
     end;
 
-    function trgobj.conservative(u,v:Tsuperregister):boolean;
+  function trgobj.conservative(u,v:Tsuperregister):boolean;
 
     var adj : Psuperregisterworklist;
         done : Tsuperregisterset; {To prevent that we count nodes twice.}
@@ -1100,7 +1212,7 @@ unit rgobj;
                 if flags*[ri_coalesced,ri_selected]=[] then
                   begin
                     supregset_include(done,n);
-                    if reginfo[n].degree>=usable_registers_cnt then
+                    if reginfo[n].degree>=reg_count(reginfo[n].subreg) then
                       inc(k);
                   end;
               end;
@@ -1111,11 +1223,11 @@ unit rgobj;
           begin
             n:=adj^.buf^[i-1];
             if not supregset_in(done,n) and
-               (reginfo[n].degree>=usable_registers_cnt) and
+               (reginfo[n].degree>=reg_count(reginfo[n].subreg)) and
                (reginfo[u].flags*[ri_coalesced,ri_selected]=[]) then
               inc(k);
           end;
-      conservative:=(k<usable_registers_cnt);
+      conservative:=(k<max(reg_count(reginfo[u].subreg),reg_count(reginfo[v].subreg)));
     end;
 
     procedure trgobj.set_alias(u,v:Tsuperregister);
@@ -1241,12 +1353,24 @@ unit rgobj;
                     end;
                 end;
           end;
-      if (reginfo[u].degree>=usable_registers_cnt) and freezeworklist.delete(u) then
+      if (reginfo[u].degree>=reg_count(reginfo[u].subreg)) and freezeworklist.delete(u) then
         spillworklist.add(u);
     end;
 
 
-    procedure trgobj.coalesce;
+  function trgobj.reg_count(subreg: TSubRegister): integer;
+    var
+      r:TSuperRegister;
+    begin
+      result:=0;
+
+      for r:=0 to first_imaginary-1 do
+        if supregset_in(reg_class[subreg],r) then
+          inc(result);
+    end;
+
+
+  procedure trgobj.coalesce;
 
     var m:Tmoveins;
         x,y,u,v:cardinal;
@@ -1331,7 +1455,7 @@ unit rgobj;
                 frozen_moves.insert(m);
 
                 if (v>=first_imaginary) and not(move_related(v)) and
-                   (reginfo[v].degree<usable_registers_cnt) then
+                   (reginfo[v].degree<reg_count(reginfo[v].subreg)) then
                   begin
                     freezeworklist.delete(v);
                     simplifyworklist.add(v);
@@ -1405,6 +1529,7 @@ unit rgobj;
         adj_colours:set of 0..255;
         found : boolean;
         tmpr: tregister;
+        r: Integer;
     begin
       spillednodes.clear;
       {Reset colours}
@@ -1426,7 +1551,13 @@ unit rgobj;
               begin
                 a:=get_alias(adj^.buf^[j]);
                 if supregset_in(colourednodes,a) and (reginfo[a].colour<=255) then
-                  include(adj_colours,reginfo[a].colour);
+                  begin
+                    include(adj_colours,reginfo[a].colour);
+
+                    for r:=0 to usable_registers_cnt-1 do
+                      if supregset_in(alias_registers[reginfo[a].colour],r) then
+                        Include(adj_colours,r);
+                  end;
               end;
           { FIXME: temp variable r is needed here to avoid Internal error 20060521 }
           {        while compiling the compiler. }
@@ -1439,14 +1570,15 @@ unit rgobj;
           for k:=0 to usable_registers_cnt-1 do
             begin
               c:=usable_registers[k];
-               if not(c in adj_colours) then
-                 begin
-                   reginfo[n].colour:=c;
-                   found:=true;
-                   supregset_include(colourednodes,n);
-                   include(used_in_proc,c);
-                   break;
-                 end;
+              if supregset_in(reg_class[reginfo[n].subreg],c) and
+                 not(c in adj_colours) then
+                begin
+                  reginfo[n].colour:=c;
+                  found:=true;
+                  supregset_include(colourednodes,n);
+                  include(used_in_proc,c);
+                  break;
+                end;
             end;
           if not found then
             spillednodes.add(n);
@@ -1555,11 +1687,15 @@ unit rgobj;
         result:=newreg(regtype,p,subreg);
         add_edges_used(p);
         add_constraints(result);
+        add_alias_constraints(result);
         { also add constraints for other sizes used for this register }
         if subreg<>low(tsubregister) then
           for subreg:=pred(subreg) downto low(tsubregister) do
             if subreg in subregconstraints then
-              add_constraints(newreg(regtype,getsupreg(result),subreg));
+              begin
+                add_constraints(newreg(regtype,getsupreg(result),subreg));
+                add_alias_constraints(newreg(regtype,getsupreg(result),subreg));
+              end;
       end;
 
 
@@ -1643,6 +1779,7 @@ unit rgobj;
 {$if defined(EXTDEBUG) or defined(DEBUG_REGISTERLIFE)}
         i : integer;
 {$endif defined(EXTDEBUG) or defined(DEBUG_REGISTERLIFE)}
+        r,
         supreg : tsuperregister;
       begin
         { All allocations are available. Now we can generate the
@@ -1686,6 +1823,7 @@ unit rgobj;
                       end;
                       { constraints needs always to be updated }
                       add_constraints(reg);
+                      add_alias_constraints(reg);
                     end;
                 end;
             add_cpu_interferences(p);
@@ -1709,13 +1847,13 @@ unit rgobj;
     procedure trgobj.translate_register(var reg : tregister);
       begin
         if (getregtype(reg)=regtype) then
-          setsupreg(reg,reginfo[getsupreg(reg)].colour)
-        else
-          internalerror(200602021);
+          setsupreg(reg,reginfo[getsupreg(reg)].colour);
+        //else
+          //internalerror(200602021);
       end;
 
 
-    procedure Trgobj.translate_registers(list:TAsmList);
+    procedure trgobj.translate_registers(list: TAsmList);
       var
         hp,p,q:Tai;
         i:shortint;
@@ -1750,7 +1888,7 @@ unit rgobj;
                           end
                         else
                           begin
-                            setsupreg(reg,reginfo[getsupreg(reg)].colour);
+                            translate_register(reg);
                             {
                               Remove sequences of release and
                               allocation of the same register like. Other combinations
@@ -1783,10 +1921,10 @@ unit rgobj;
                     begin
                       if (cs_asm_source in current_settings.globalswitches) then
                         begin
-                          setsupreg(tai_varloc(p).newlocation,reginfo[getsupreg(tai_varloc(p).newlocation)].colour);
+                          translate_register(tai_varloc(p).newlocation);
                           if tai_varloc(p).newlocationhi<>NR_NO then
                             begin
-                              setsupreg(tai_varloc(p).newlocationhi,reginfo[getsupreg(tai_varloc(p).newlocationhi)].colour);
+                              translate_register(tai_varloc(p).newlocationhi);
                                 hp:=Tai_comment.Create(strpnew('Var '+tai_varloc(p).varsym.realname+' located in register '+
                                   std_regname(tai_varloc(p).newlocationhi)+':'+std_regname(tai_varloc(p).newlocation)));
                             end
@@ -1816,51 +1954,19 @@ unit rgobj;
                       with oper[i]^ do
                         case typ of
                           Top_reg:
-                             if (getregtype(reg)=regtype) then
-                               begin
-                                 u:=getsupreg(reg);
-{$ifdef EXTDEBUG}
-                                 if (u>=maxreginfo) then
-                                   internalerror(2012101903);
-{$endif}
-                                 setsupreg(reg,reginfo[u].colour);
-                               end;
+                             translate_register(reg);
                           Top_ref:
                             begin
                               if regtype in [R_INTREGISTER,R_ADDRESSREGISTER] then
                                 with ref^ do
                                   begin
-                                    if (base<>NR_NO) and
-                                       (getregtype(base)=regtype) then
-                                      begin
-                                        u:=getsupreg(base);
-{$ifdef EXTDEBUG}
-                                        if (u>=maxreginfo) then
-                                          internalerror(2012101904);
-{$endif}
-                                        setsupreg(base,reginfo[u].colour);
-                                      end;
-                                    if (index<>NR_NO) and
-                                       (getregtype(index)=regtype) then
-                                      begin
-                                        u:=getsupreg(index);
-{$ifdef EXTDEBUG}
-                                        if (u>=maxreginfo) then
-                                          internalerror(2012101905);
-{$endif}
-                                        setsupreg(index,reginfo[u].colour);
-                                      end;
+                                    if (base<>NR_NO) then
+                                      translate_register(base);
+                                    if (index<>NR_NO) then
+                                      translate_register(index);
 {$if defined(x86)}
-                                    if (segment<>NR_NO) and
-                                       (getregtype(segment)=regtype) then
-                                      begin
-                                        u:=getsupreg(segment);
-{$ifdef EXTDEBUG}
-                                        if (u>=maxreginfo) then
-                                          internalerror(2013052401);
-{$endif}
-                                        setsupreg(segment,reginfo[u].colour);
-                                      end;
+                                    if (segment<>NR_NO) then
+                                      translate_register(segment);
 {$endif defined(x86)}
                                   end;
                             end;
@@ -1868,12 +1974,8 @@ unit rgobj;
                           Top_shifterop:
                             begin
                               if regtype=R_INTREGISTER then
-                                begin
-                                  so:=shifterop;
-                                  if (so^.rs<>NR_NO) and
-                                     (getregtype(so^.rs)=regtype) then
-                                    setsupreg(so^.rs,reginfo[getsupreg(so^.rs)].colour);
-                                end;
+                                if (shifterop^.rs<>NR_NO) then
+                                  translate_register(shifterop^.rs);
                             end;
 {$endif arm}
                         end;
@@ -2012,7 +2114,7 @@ unit rgobj;
       end;
 
 
-    procedure Trgobj.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
+        procedure trgobj.do_spill_written(list: TAsmList; pos: tai; const spilltemp: treference; tempreg: tregister);
       var
         ins:Taicpu;
       begin

compiler/x86/cpubase.pas

@@ -87,22 +87,35 @@ uses
       RS_R15        = $0f;      {R15}
       { create aliases to allow code sharing between x86-64 and i386 }
       RS_EAX        = RS_RAX;
-      RS_EBX        = RS_RBX;
       RS_ECX        = RS_RCX;
       RS_EDX        = RS_RDX;
+      RS_EBX        = RS_RBX;
       RS_ESI        = RS_RSI;
       RS_EDI        = RS_RDI;
       RS_EBP        = RS_RBP;
       RS_ESP        = RS_RSP;
       { create aliases to allow code sharing between i386 and i8086 }
       RS_AX        = RS_RAX;
-      RS_BX        = RS_RBX;
       RS_CX        = RS_RCX;
       RS_DX        = RS_RDX;
+      RS_BX        = RS_RBX;
       RS_SI        = RS_RSI;
       RS_DI        = RS_RDI;
       RS_BP        = RS_RBP;
       RS_SP        = RS_RSP;
+      { 8-bit aliases }
+      RS_AL        = RS_RAX;
+      RS_AH        = RS_RAX;
+      RS_CL        = RS_RCX;
+      RS_CH        = RS_RCX;
+      RS_DL        = RS_RDX;
+      RS_DH        = RS_RDX;
+      RS_BL        = RS_RBX;
+      RS_BH        = RS_RBX;
+      RS_SIL       = RS_RSI;
+      RS_DIL       = RS_RDI;
+      RS_BPL       = RS_RBP;
+      RS_SPL       = RS_RSP;
 
       { Number of first imaginary register }
       first_int_imreg     = $10;

compiler/x86/x86reg.dat

@@ -15,41 +15,41 @@
 ;    this is due to asm optimizer coding style
 
 NR_NO,$00000000,INVALID,INVALID,INVALID,INVALID,-1,-1,-1,OT_NONE,0
-NR_AL,$01010000,al,%al,al,al,0,0,0,OT_REG_AL,0
-NR_AH,$01020000,ah,%ah,ah,ah,0,0,0,OT_REG8,4
-NR_AX,$01030000,ax,%ax,ax,ax,0,0,0,OT_REG_AX,0
-NR_EAX,$01040000,eax,%eax,eax,eax,0,0,0,OT_REG_EAX,0
+NR_AL,$01010021,al,%al,al,al,0,0,0,OT_REG_AL,0
+NR_AH,$01020022,ah,%ah,ah,ah,0,0,0,OT_REG8,4
+NR_AX,$01030018,ax,%ax,ax,ax,0,0,0,OT_REG_AX,0
+NR_EAX,$01040010,eax,%eax,eax,eax,0,0,0,OT_REG_EAX,0
 NR_RAX,$01050000,rax,%rax,rax,rax,0,0,0,OT_REG_RAX,0,64
-NR_CL,$01010001,cl,%cl,cl,cl,1,1,2,OT_REG_CL,1
-NR_CH,$01020001,ch,%ch,ch,ch,1,1,2,OT_REG8,5
-NR_CX,$01030001,cx,%cx,cx,cx,1,1,2,OT_REG_CX,1
-NR_ECX,$01040001,ecx,%ecx,ecx,ecx,1,1,2,OT_REG_ECX,1
+NR_CL,$01010023,cl,%cl,cl,cl,1,1,2,OT_REG_CL,1
+NR_CH,$01020024,ch,%ch,ch,ch,1,1,2,OT_REG8,5
+NR_CX,$01030019,cx,%cx,cx,cx,1,1,2,OT_REG_CX,1
+NR_ECX,$01040011,ecx,%ecx,ecx,ecx,1,1,2,OT_REG_ECX,1
 NR_RCX,$01050001,rcx,%rcx,rcx,rcx,1,1,2,OT_REG_RCX,1,64
-NR_DL,$01010002,dl,%dl,dl,dl,2,2,1,OT_REG8,2
-NR_DH,$01020002,dh,%dh,dh,dh,2,2,1,OT_REG8,6
-NR_DX,$01030002,dx,%dx,dx,dx,2,2,1,OT_REG_DX,2
-NR_EDX,$01040002,edx,%edx,edx,edx,2,2,1,OT_REG32,2
+NR_DL,$01010025,dl,%dl,dl,dl,2,2,1,OT_REG8,2
+NR_DH,$01020026,dh,%dh,dh,dh,2,2,1,OT_REG8,6
+NR_DX,$0103001a,dx,%dx,dx,dx,2,2,1,OT_REG_DX,2
+NR_EDX,$01040012,edx,%edx,edx,edx,2,2,1,OT_REG32,2
 NR_RDX,$01050002,rdx,%rdx,rdx,rdx,2,2,1,OT_REG64,2,64
-NR_BL,$01010003,bl,%bl,bl,bl,3,3,3,OT_REG8,3
-NR_BH,$01020003,bh,%bh,bh,bh,3,3,3,OT_REG8,7
-NR_BX,$01030003,bx,%bx,bx,bx,3,3,3,OT_REG16,3
-NR_EBX,$01040003,ebx,%ebx,ebx,ebx,3,3,3,OT_REG32,3
+NR_BL,$01010027,bl,%bl,bl,bl,3,3,3,OT_REG8,3
+NR_BH,$01020028,bh,%bh,bh,bh,3,3,3,OT_REG8,7
+NR_BX,$0103001b,bx,%bx,bx,bx,3,3,3,OT_REG16,3
+NR_EBX,$01040013,ebx,%ebx,ebx,ebx,3,3,3,OT_REG32,3
 NR_RBX,$01050003,rbx,%rbx,rbx,rbx,3,3,3,OT_REG64,3,64
-NR_SIL,$01010004,sil,%sil,sil,sil,6,6,4,OT_REG8,6,64
-NR_SI,$01030004,si,%si,si,si,6,6,4,OT_REG16,6
-NR_ESI,$01040004,esi,%esi,esi,esi,6,6,4,OT_REG32,6
+NR_SIL,$01010029,sil,%sil,sil,sil,6,6,4,OT_REG8,6,64
+NR_SI,$0103001c,si,%si,si,si,6,6,4,OT_REG16,6
+NR_ESI,$01040014,esi,%esi,esi,esi,6,6,4,OT_REG32,6
 NR_RSI,$01050004,rsi,%rsi,rsi,rsi,6,6,4,OT_REG64,6,64
-NR_DIL,$01010005,dil,%dil,dil,dil,7,7,5,OT_REG8,7,64
-NR_DI,$01030005,di,%di,di,di,7,7,5,OT_REG16,7
-NR_EDI,$01040005,edi,%edi,edi,edi,7,7,5,OT_REG32,7
+NR_DIL,$0101002a,dil,%dil,dil,dil,7,7,5,OT_REG8,7,64
+NR_DI,$0103001e,di,%di,di,di,7,7,5,OT_REG16,7
+NR_EDI,$01040015,edi,%edi,edi,edi,7,7,5,OT_REG32,7
 NR_RDI,$01050005,rdi,%rdi,rdi,rdi,7,7,5,OT_REG64,7,64
-NR_BPL,$01010006,bpl,%bpl,bpl,bpl,5,5,6,OT_REG8,5,64
-NR_BP,$01030006,bp,%bp,bp,bp,5,5,6,OT_REG16,5
-NR_EBP,$01040006,ebp,%ebp,ebp,ebp,5,5,6,OT_REG32,5
+NR_BPL,$0101002b,bpl,%bpl,bpl,bpl,5,5,6,OT_REG8,5,64
+NR_BP,$0103001f,bp,%bp,bp,bp,5,5,6,OT_REG16,5
+NR_EBP,$01040016,ebp,%ebp,ebp,ebp,5,5,6,OT_REG32,5
 NR_RBP,$01050006,rbp,%rbp,rbp,rbp,5,5,6,OT_REG64,5,64
-NR_SPL,$01010007,spl,%spl,spl,spl,4,4,7,OT_REG8,4,64
-NR_SP,$01030007,sp,%sp,sp,sp,4,4,7,OT_REG16,4
-NR_ESP,$01040007,esp,%esp,esp,esp,4,4,7,OT_REG32,4
+NR_SPL,$0101002c,spl,%spl,spl,spl,4,4,7,OT_REG8,4,64
+NR_SP,$01030020,sp,%sp,sp,sp,4,4,7,OT_REG16,4
+NR_ESP,$01040017,esp,%esp,esp,esp,4,4,7,OT_REG32,4
 NR_RSP,$01050007,rsp,%rsp,rsp,rsp,4,4,7,OT_REG64,4,64
 NR_R8,$01050008,r8,%r8,r8,r8,-1,-1,8,OT_REG64,0,64
 NR_R8L,$01010008,r8b,%r8b,r8b,r8b,-1,-1,8,OT_REG8,0,64