* MIPS improvements:

  * reworked condition codes, changed BC1T and BC1F from separate instructions to condition jumps.
  - removed A_P_SW, A_P_LW and A_SPARC8UNIMP
  + support '.set at' and '.set noat' directives
  + prepare to support bgtz,bgez,bltz,blez instructions.

git-svn-id: trunk@24631 -

compiler/mips/cpubase.pas

@@ -112,19 +112,16 @@ unit cpubase;
     type
       TAsmCond=(C_None,
         C_EQ, C_NE, C_LT, C_LE, C_GT, C_GE, C_LTU, C_LEU, C_GTU, C_GEU,
-        C_FEQ,  {Equal}
-        C_FNE, {Not Equal}
-        C_FGT,  {Greater}
-        C_FLT,  {Less}
-        C_FGE, {Greater or Equal}
-        C_FLE  {Less or Equal}
-
+        C_LTZ, C_LEZ, C_GTZ, C_GEZ,
+        C_COP1TRUE,
+        C_COP1FALSE
       );
 
     const
       cond2str : array[TAsmCond] of string[3]=('',
         'eq','ne','lt','le','gt','ge','ltu','leu','gtu','geu',
-        'feq','fne','fgt','flt','fge','fle'
+        'ltz','lez','gtz','gez',
+        'c1t','c1f'
       );
 
 {*****************************************************************************
@@ -326,7 +323,7 @@ unit cpubase;
 
     function is_calljmp(o:tasmop):boolean;
       begin
-        is_calljmp:= o in [A_J,A_JAL,A_JALR,{ A_JALX, }A_JR, A_BA, A_BC, A_BC1T, A_BC1F];
+        is_calljmp:= o in [A_J,A_JAL,A_JALR,{ A_JALX, }A_JR, A_BA, A_BC];
       end;
 
 
@@ -334,12 +331,9 @@ unit cpubase;
       const
         inverse: array[TAsmCond] of TAsmCond=(C_None,
         C_NE, C_EQ, C_GE, C_GT, C_LE, C_LT, C_GEU, C_GTU, C_LEU, C_LTU,
-        C_FNE, 
-        C_FEQ, 
-        C_FLE, 
-        C_FGE, 
-        C_FLT, 
-        C_FGT  
+        C_GEZ, C_GTZ, C_LEZ, C_LTZ,
+        C_COP1FALSE,
+        C_COP1TRUE
         );
       begin
         result := inverse[c];

compiler/mips/cpugas.pas

@@ -235,9 +235,11 @@ unit cpugas;
           (op=A_SEQ) or (op = A_SGE) or (op=A_SGEU) or (op=A_SGT) or
           (op=A_SGTU) or (op=A_SLE) or (op=A_SLEU) or (op=A_SNE)
           { JAL is not here! See comments in TCGMIPS.a_call_name. }
-          or (op=A_LA) or ((op=A_BC) and not (ai.condition in [C_EQ,C_NE])) {or (op=A_JAL)}
+          or (op=A_LA) or ((op=A_BC) and
+            not (ai.condition in [C_EQ,C_NE,C_GTZ,C_GEZ,C_LTZ,C_LEZ,C_COP1TRUE,C_COP1FALSE])) {or (op=A_JAL)}
           or (op=A_REM) or (op=A_REMU)
           or (op=A_DIV) or (op=A_DIVU)
+          or (op=A_MULO) or (op=A_MULOU)
           { A_LI is only a macro if the immediate is not in thez 16-bit range }
           or (op=A_LI);
       end;
@@ -258,8 +260,7 @@ unit cpugas;
         case op of
           A_P_SET_NOMIPS16:
             begin
-              s := #9 + '.set' + #9 + 'nomips16';
-              owner.AsmWriteLn(s);
+              owner.AsmWriteLn(#9'.set'#9'nomips16');
             end;
           A_P_MASK,
           A_P_FMASK:
@@ -269,37 +270,33 @@ unit cpugas;
             end;
           A_P_SET_MACRO:
             begin
-              s := #9 + '.set' + #9 + 'macro';
-              owner.AsmWriteLn(s);
+              owner.AsmWriteLn(#9'.set'#9'macro');
               TMIPSGNUAssembler(owner).nomacro:=false;
             end;
           A_P_SET_REORDER:
             begin
-              s := #9 + '.set' + #9 + 'reorder';
-              owner.AsmWriteLn(s);
+              owner.AsmWriteLn(#9'.set'#9'reorder');
               TMIPSGNUAssembler(owner).noreorder:=false;
             end;
           A_P_SET_NOMACRO:
             begin
-              s := #9 + '.set' + #9 + 'nomacro';
-              owner.AsmWriteLn(s);
+              owner.AsmWriteLn(#9'.set'#9'nomacro');
               TMIPSGNUAssembler(owner).nomacro:=true;
             end;
           A_P_SET_NOREORDER:
             begin
-              s := #9 + '.set' + #9 + 'noreorder';
-              owner.AsmWriteLn(s);
+              owner.AsmWriteLn(#9'.set'#9'noreorder');
               TMIPSGNUAssembler(owner).noreorder:=true;
             end;
-          A_P_SW:
+          A_P_SET_NOAT:
             begin
-              s := #9 + gas_op2str[A_SW] + #9 + getopstr(taicpu(hp).oper[0]^)+ ',' + getopstr(taicpu(hp).oper[2]^) + '(' + getopstr(taicpu(hp).oper[1]^) + ')';
-              owner.AsmWriteLn(s);
+              owner.AsmWriteln(#9'.set'#9'noat');
+              TMIPSGNUAssembler(owner).noat:=true;
             end;
-          A_P_LW:
+          A_P_SET_AT:
             begin
-              s := #9 + gas_op2str[A_LW] + #9 + getopstr(taicpu(hp).oper[0]^)+ ',' + getopstr(taicpu(hp).oper[2]^) + '(' + getopstr(taicpu(hp).oper[1]^) + ')';
-              owner.AsmWriteLn(s);
+              owner.AsmWriteln(#9'.set'#9'at');
+              TMIPSGNUAssembler(owner).noat:=false;
             end;
           A_LDC1:
             begin

compiler/mips/ncpuadd.pas

@@ -343,8 +343,9 @@ const
 
 procedure tmipsaddnode.second_cmpfloat;
 var
-  op,op2: tasmop;
+  op: tasmop;
   lreg,rreg: tregister;
+  ai: Taicpu;
 begin
   pass_left_right;
   if nf_swapped in flags then
@@ -356,11 +357,6 @@ begin
 
   op:=ops_cmpfloat[left.location.size=OS_F64,nodetype];
 
-  if (nodetype=unequaln) then
-    op2:=A_BC1F
-  else
-    op2:=A_BC1T;
-
   if (nodetype in [gtn,gten]) then
     begin
       lreg:=right.location.register;
@@ -373,7 +369,12 @@ begin
     end;
 
   current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,lreg,rreg));
-  current_asmdata.CurrAsmList.concat(Taicpu.op_sym(op2,current_procinfo.CurrTrueLabel));
+  ai:=taicpu.op_sym(A_BC,current_procinfo.CurrTrueLabel);
+  if (nodetype=unequaln) then
+    ai.SetCondition(C_COP1FALSE)
+  else
+    ai.SetCondition(C_COP1TRUE);
+  current_asmdata.CurrAsmList.concat(ai);
   current_asmdata.CurrAsmList.concat(TAiCpu.Op_none(A_NOP));
   cg.a_jmp_always(current_asmdata.CurrAsmList,current_procinfo.CurrFalseLabel);
 end;

compiler/mips/opcode.inc

@@ -1,18 +1,17 @@
 A_NONE,
-A_P_LW,
 A_P_SET_NOMIPS16,
 A_P_SET_NOREORDER,
 A_P_SET_NOMACRO,
 A_P_SET_MACRO,
 A_P_SET_REORDER,
+A_P_SET_NOAT,
+A_P_SET_AT,
 A_P_FRAME,
 A_P_MASK,
 A_P_FMASK,
-A_P_SW,
 A_P_CPLOAD,
 A_P_CPRESTORE,
 A_P_CPADD,
-A_SPARC8UNIMP,
 A_NOP,
 A_NOT,
 A_NEG,
@@ -178,8 +177,6 @@ A_FLOOR_W_S,
 A_FLOOR_W_D,
 A_FLOOR_L_S,
 A_FLOOR_L_D,
-A_BC1T,
-A_BC1F,
 A_C_EQ_D,
 A_C_EQ_S,
 A_C_LE_D,
@@ -195,6 +192,7 @@ A_SLE,
 A_SLEU,
 A_SNE,
 A_SYSCALL,
+A_BREAK,
 A_ADD64SUB,
 A_SUB64SUB,
 A_MUL64SUB,

compiler/mips/strinst.inc

@@ -1,18 +1,17 @@
 'none',
-'p_lw',
 'p_set_nomips16',
 'p_set_noreorder',
 'p_set_nomacro',
 'p_set_macro',
 'p_set_reorder',
+'p_set_noat',
+'p_set_at',
 '.frame',
 '.mask',
 '.fmask',
-'p_sw',
 '.cpload',
 '.cprestore',
 '.cpadd',
-'sparc8unimp',
 'nop',
 'not',
 'neg',
@@ -178,8 +177,6 @@
 'floor.w.d',
 'floor.l.s',
 'floor.l.d',
-'bc1t',
-'bc1f',
 'c.eq.d',
 'c.eq.s',
 'c.le.d',
@@ -195,6 +192,7 @@
 'sleu',
 'sne',
 'syscall',
+'break',
 'add64sub',
 'sub64sub',
 'mul64sub',