m68k: added more cpu capabilities. changed the CG at a few places to actually use them

git-svn-id: trunk@42763 -

compiler/m68k/cgcpu.pas

@@ -514,7 +514,7 @@ unit cgcpu;
            end;
 
          { deal with large offsets on non-020+ }
-         if not (current_settings.cputype in cpu_mc68020p) then
+         if not (CPUM68K_HAS_BASEDISP in cpu_capabilities[current_settings.cputype]) then
            begin
              if ((ref.index<>NR_NO) and not isvalue8bit(ref.offset)) or
                 ((ref.base<>NR_NO) and not isvalue16bit(ref.offset)) then
@@ -1195,7 +1195,7 @@ unit cgcpu;
                 { NOTE: better have this as fast as possible on every CPU in all cases,
                         because the compiler uses OP_IMUL for array indexing... (KB) }
                 { ColdFire doesn't support MULS/MULU <imm>,dX }
-                if current_settings.cputype in cpu_coldfire then
+                if not (CPUM68K_HAS_MULIMM in cpu_capabilities[current_settings.cputype]) then
                   begin
                     { move const to a register first }
                     scratch_reg := getintregister(list,OS_INT);
@@ -1211,7 +1211,7 @@ unit cgcpu;
                   end
                 else
                   begin
-                    if current_settings.cputype in cpu_mc68020p then
+                    if CPUM68K_HAS_32BITMUL in cpu_capabilities[current_settings.cputype] then
                       begin
                         { do the multiplication }
                         scratch_reg := force_to_dataregister(list, size, reg);
@@ -1888,7 +1888,7 @@ unit cgcpu;
 
             if (parasize > 0) and not (current_procinfo.procdef.proccalloption in clearstack_pocalls) then
               begin
-                if current_settings.cputype in cpu_mc68020p then
+                if CPUM68K_HAS_RTD in cpu_capabilities[current_settings.cputype] then
                   list.concat(taicpu.op_const(A_RTD,S_NO,parasize))
                 else
                   begin

compiler/m68k/cpuinfo.pas

@@ -149,22 +149,26 @@ Const
 
 type
   tcpuflags =
-     (CPUM68K_HAS_DBRA,      { CPU supports the DBRA instruction                         }
-      CPUM68K_HAS_CAS,       { CPU supports the CAS instruction                          }
-      CPUM68K_HAS_TAS,       { CPU supports the TAS instruction                          }
-      CPUM68K_HAS_BRAL,      { CPU supports the BRA.L/Bcc.L instructions                 }
-      CPUM68K_HAS_ROLROR,    { CPU supports the ROL/ROR and ROXL/ROXR instructions       }
-      CPUM68K_HAS_BYTEREV,   { CPU supports the BYTEREV instruction                      }
-      CPUM68K_HAS_MVSMVZ,    { CPU supports the MVZ and MVS instructions                 }
-      CPUM68K_HAS_MOVE16,    { CPU supports the MOVE16 instruction                       }
-      CPUM68K_HAS_32BITMUL,  { CPU supports MULS/MULU 32x32 -> 32bit                     }
-      CPUM68K_HAS_64BITMUL,  { CPU supports MULS/MULU 32x32 -> 64bit                     }
-      CPUM68K_HAS_16BITDIV,  { CPU supports DIVS/DIVU 32/16 -> 16bit                     }
-      CPUM68K_HAS_32BITDIV,  { CPU supports DIVS/DIVU 32/32 -> 32bit                     }
-      CPUM68K_HAS_64BITDIV,  { CPU supports DIVS/DIVU 64/32 -> 32bit                     }
-      CPUM68K_HAS_REMSREMU,  { CPU supports the REMS/REMU instructions                   }
-      CPUM68K_HAS_UNALIGNED, { CPU supports unaligned access                             }
-      CPUM68K_HAS_BASEDISP   { CPU supports addressing with 32bit base displacements     }
+     (CPUM68K_HAS_DBRA,        { CPU supports the DBRA instruction                         }
+      CPUM68K_HAS_RTD,         { CPU supports the RTD instruction                          }
+      CPUM68K_HAS_CAS,         { CPU supports the CAS instruction                          }
+      CPUM68K_HAS_TAS,         { CPU supports the TAS instruction                          }
+      CPUM68K_HAS_BRAL,        { CPU supports the BRA.L/Bcc.L instructions                 }
+      CPUM68K_HAS_ROLROR,      { CPU supports the ROL/ROR and ROXL/ROXR instructions       }
+      CPUM68K_HAS_BYTEREV,     { CPU supports the BYTEREV instruction                      }
+      CPUM68K_HAS_MVSMVZ,      { CPU supports the MVZ and MVS instructions                 }
+      CPUM68K_HAS_MOVE16,      { CPU supports the MOVE16 instruction                       }
+      CPUM68K_HAS_MULIMM,      { CPU supports MULS/MULU with immediate value               }
+      CPUM68K_HAS_32BITMUL,    { CPU supports MULS/MULU 32x32 -> 32bit                     }
+      CPUM68K_HAS_64BITMUL,    { CPU supports MULS/MULU 32x32 -> 64bit                     }
+      CPUM68K_HAS_16BITDIV,    { CPU supports DIVS/DIVU 32/16 -> 16bit                     }
+      CPUM68K_HAS_32BITDIV,    { CPU supports DIVS/DIVU 32/32 -> 32bit                     }
+      CPUM68K_HAS_64BITDIV,    { CPU supports DIVS/DIVU 64/32 -> 32bit                     }
+      CPUM68K_HAS_REMSREMU,    { CPU supports the REMS/REMU instructions                   }
+      CPUM68K_HAS_UNALIGNED,   { CPU supports unaligned access                             }
+      CPUM68K_HAS_BASEDISP,    { CPU supports addressing with 32bit base displacements     }
+      CPUM68K_HAS_INDEXSCALE,  { CPU supports scaling the index register with 2 or 4       }
+      CPUM68K_HAS_INDEXSCALE8  { CPU supports scaling the index register with 2, 4 or 8    }
      );
 
   tfpuflags =
@@ -172,22 +176,22 @@ type
       FPUM68K_HAS_EXTENDED,        { FPU has 80 bit extended support }
       FPUM68K_HAS_TRIGONOMETRY,    { FPU supports trigonometric instructions (FSIN/FCOS, etc) }
       FPUM68K_HAS_RESULTPRECISION, { FPU supports encoding the result precision into instructions }
-      FPUM68K_HAS_FLOATIMMEDIATE,  { FPU supports floating pont immediate values }
+      FPUM68K_HAS_FLOATIMMEDIATE,  { FPU supports floating point immediate values }
       FPUM68K_HAS_FINTRZ           { FPU supports the FINT/FINTRZ instruction }
      );
 
 const
   cpu_capabilities : array[tcputype] of set of tcpuflags =
     ( { cpu_none     } [],
-      { cpu_68000    } [CPUM68K_HAS_DBRA,CPUM68K_HAS_TAS,CPUM68K_HAS_ROLROR,CPUM68K_HAS_16BITDIV],
-      { cpu_68020    } [CPUM68K_HAS_DBRA,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_BASEDISP,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_64BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_64BITDIV],
-      { cpu_68040    } [CPUM68K_HAS_DBRA,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_BASEDISP,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_64BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_64BITDIV,CPUM68K_HAS_MOVE16],
-      { cpu_68060    } [CPUM68K_HAS_DBRA,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_BASEDISP,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_MOVE16],
-      { cpu_isaa     } [CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU],
-      { cpu_isaap    } [CPUM68K_HAS_BRAL,CPUM68K_HAS_BYTEREV,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU],
-      { cpu_isab     } [CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_MVSMVZ,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU],
-      { cpu_isac     } [CPUM68K_HAS_TAS,CPUM68K_HAS_BYTEREV,CPUM68K_HAS_MVSMVZ,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU],
-      { cpu_cfv4e    } [CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_MVSMVZ,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU]
+      { cpu_68000    } [CPUM68K_HAS_DBRA,CPUM68K_HAS_TAS,CPUM68K_HAS_ROLROR,CPUM68K_HAS_MULIMM,CPUM68K_HAS_16BITDIV],
+      { cpu_68020    } [CPUM68K_HAS_DBRA,CPUM68K_HAS_RTD,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_BASEDISP,CPUM68K_HAS_MULIMM,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_64BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_64BITDIV,CPUM68K_HAS_INDEXSCALE,CPUM68K_HAS_INDEXSCALE8],
+      { cpu_68040    } [CPUM68K_HAS_DBRA,CPUM68K_HAS_RTD,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_BASEDISP,CPUM68K_HAS_MULIMM,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_64BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_64BITDIV,CPUM68K_HAS_MOVE16,CPUM68K_HAS_INDEXSCALE,CPUM68K_HAS_INDEXSCALE8],
+      { cpu_68060    } [CPUM68K_HAS_DBRA,CPUM68K_HAS_RTD,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_BASEDISP,CPUM68K_HAS_MULIMM,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_MOVE16,CPUM68K_HAS_INDEXSCALE,CPUM68K_HAS_INDEXSCALE8],
+      { cpu_isaa     } [CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU,CPUM68K_HAS_INDEXSCALE],
+      { cpu_isaap    } [CPUM68K_HAS_BRAL,CPUM68K_HAS_BYTEREV,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU,CPUM68K_HAS_INDEXSCALE],
+      { cpu_isab     } [CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_MVSMVZ,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU,CPUM68K_HAS_INDEXSCALE],
+      { cpu_isac     } [CPUM68K_HAS_TAS,CPUM68K_HAS_BYTEREV,CPUM68K_HAS_MVSMVZ,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU,CPUM68K_HAS_INDEXSCALE],
+      { cpu_cfv4e    } [CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_MVSMVZ,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU,CPUM68K_HAS_INDEXSCALE]
     );
 
   { on m68k, Motorola provided a software-library, which provides full '881/2 instruction set