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--- Merging r21676 into '.':
U compiler/arm/aasmcpu.pas
--- Merging r21678 into '.':
U compiler/arm/narminl.pas
U compiler/options.pas
--- Merging r21685 into '.':
U compiler/arm/agarmgas.pas
--- Merging r21686 into '.':
U compiler/arm/narmmat.pas

# revisions: 21676,21678,21685,21686
r21676 | masta | 2012-06-21 22:12:25 +0200 (Thu, 21 Jun 2012) | 8 lines
Changed paths:
M /trunk/compiler/arm/aasmcpu.pas

Fixed postfix check in taicpu.is_same_reg_move

The old version did not check the S-Postfix for MOV, which results in
removing instructions like:

movs r0, r0

which breaks later flag usage.
r21678 | masta | 2012-06-21 22:12:36 +0200 (Thu, 21 Jun 2012) | 11 lines
Changed paths:
M /trunk/compiler/arm/narminl.pas
M /trunk/compiler/options.pas

Support ABS intrinsic on ARM

This code will generate the following sequence on arm:
r1=dst
r0=src

movs r1, r0
rsbmi r1, r0, #0

movs will set the N-flag when the MSB of r0 is set, if it is set, rsb
will calculate dst:=0-src;
r21685 | masta | 2012-06-23 22:36:16 +0200 (Sat, 23 Jun 2012) | 7 lines
Changed paths:
M /trunk/compiler/arm/agarmgas.pas

Fix ARM-Assembler output for RRX-Shifterops

RRX (Rotate Right with eXtend) does a single bit right rotation through
the carry. So it does not take any arguments, neither constant nor
register.

Also remove redundant shiftmode2str and replace usage of it with gas_shiftmode2str.
r21686 | masta | 2012-06-23 22:36:27 +0200 (Sat, 23 Jun 2012) | 12 lines
Changed paths:
M /trunk/compiler/arm/narmmat.pas

Support 64-bit shifts on ARM.

This code generate different versions of assembly depending on the
amount to shift.

Variable Amount: 6 cycles (5 if last shift can be folded)
Constant 1 : 2 cycles
Constant 2-31 : 3 cycles (2 if last shift can foldable)
Constant 32 : 1 cycle (depends on the register allocator)
Constant 33-64 : 2 cycles

This should speed up softfpu on arm a bit.

git-svn-id: branches/fixes_2_6@22524 -

marco 13 years ago
parent
commit
8a17c147fa
5 changed files with 171 additions and 14 deletions
  1. 5 3
      compiler/arm/aasmcpu.pas
  2. 10 8
      compiler/arm/agarmgas.pas
  3. 18 2
      compiler/arm/narminl.pas
  4. 137 0
      compiler/arm/narmmat.pas
  5. 1 1
      compiler/options.pas

+ 5 - 3
compiler/arm/aasmcpu.pas

@@ -567,10 +567,12 @@ implementation
     function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
     function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
       begin
       begin
         { allow the register allocator to remove unnecessary moves }
         { allow the register allocator to remove unnecessary moves }
-        result:=(((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
-                 ((opcode=A_MVF) and (regtype = R_FPUREGISTER) and (oppostfix in [PF_None,PF_D])) or
-                 (((opcode=A_FCPYS) or (opcode=A_FCPYD)) and (regtype = R_MMREGISTER))
+        result:=(
+                  ((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
+                  ((opcode=A_MVF) and (regtype = R_FPUREGISTER)) or
+                  ((opcode in [A_FCPYS, A_FCPYD]) and (regtype = R_MMREGISTER))
                 ) and
                 ) and
+                (oppostfix in [PF_None,PF_D]) and
                 (condition=C_None) and
                 (condition=C_None) and
                 (ops=2) and
                 (ops=2) and
                 (oper[0]^.typ=top_reg) and
                 (oper[0]^.typ=top_reg) and

+ 10 - 8
compiler/arm/agarmgas.pas

@@ -147,7 +147,10 @@ unit agarmgas;
 
 
                      s:=s+gas_regname(index);
                      s:=s+gas_regname(index);
 
 
-                     if shiftmode<>SM_None then
+                     {RRX always rotates by 1 bit and does not take an imm}
+                     if shiftmode = SM_RRX then
+                       s:=s+', rrx'
+                     else if shiftmode <> SM_None then
                        s:=s+', '+gas_shiftmode2str[shiftmode]+' #'+tostr(shiftimm);
                        s:=s+', '+gas_shiftmode2str[shiftmode]+' #'+tostr(shiftimm);
                   end
                   end
                 else if offset<>0 then
                 else if offset<>0 then
@@ -165,10 +168,6 @@ unit agarmgas;
         getreferencestring:=s;
         getreferencestring:=s;
       end;
       end;
 
 
-
-    const
-      shiftmode2str: array[tshiftmode] of string[3] = ('','lsl','lsr','asr','ror','rrx');
-
     function getopstr(const o:toper) : string;
     function getopstr(const o:toper) : string;
       var
       var
         hs : string;
         hs : string;
@@ -180,10 +179,13 @@ unit agarmgas;
             getopstr:=gas_regname(o.reg);
             getopstr:=gas_regname(o.reg);
           top_shifterop:
           top_shifterop:
             begin
             begin
-              if (o.shifterop^.rs<>NR_NO) and (o.shifterop^.shiftimm=0) then
-                getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' '+gas_regname(o.shifterop^.rs)
+              {RRX is special, it only rotates by 1 and does not take any shiftervalue}
+              if o.shifterop^.shiftmode=SM_RRX then
+                getopstr:='rrx'
+              else if (o.shifterop^.rs<>NR_NO) and (o.shifterop^.shiftimm=0) then
+                getopstr:=gas_shiftmode2str[o.shifterop^.shiftmode]+' '+gas_regname(o.shifterop^.rs)
               else if (o.shifterop^.rs=NR_NO) then
               else if (o.shifterop^.rs=NR_NO) then
-                getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' #'+tostr(o.shifterop^.shiftimm)
+                getopstr:=gas_shiftmode2str[o.shifterop^.shiftmode]+' #'+tostr(o.shifterop^.shiftimm)
               else internalerror(200308282);
               else internalerror(200308282);
             end;
             end;
           top_const:
           top_const:

+ 18 - 2
compiler/arm/narminl.pas

@@ -49,6 +49,7 @@ interface
         procedure second_sin_real; override;
         procedure second_sin_real; override;
         }
         }
         procedure second_prefetch; override;
         procedure second_prefetch; override;
+        procedure second_abs_long; override;
       private
       private
         procedure load_fpu_location(out singleprec: boolean);
         procedure load_fpu_location(out singleprec: boolean);
       end;
       end;
@@ -59,14 +60,14 @@ implementation
     uses
     uses
       globtype,systems,
       globtype,systems,
       cutils,verbose,globals,fmodule,
       cutils,verbose,globals,fmodule,
-      cpuinfo,
+      cpuinfo, defutil,
       symconst,symdef,
       symconst,symdef,
       aasmbase,aasmtai,aasmdata,aasmcpu,
       aasmbase,aasmtai,aasmdata,aasmcpu,
       cgbase,cgutils,
       cgbase,cgutils,
       pass_1,pass_2,
       pass_1,pass_2,
       cpubase,paramgr,
       cpubase,paramgr,
       nbas,ncon,ncal,ncnv,nld,
       nbas,ncon,ncal,ncnv,nld,
-      tgobj,ncgutil,cgobj,cg64f32,rgobj,rgcpu,cgcpu;
+      tgobj,ncgutil,cgobj,cg64f32,rgobj,rgcpu,cgcpu, hlcgobj;
 
 
 {*****************************************************************************
 {*****************************************************************************
                               tarminlinenode
                               tarminlinenode
@@ -331,6 +332,21 @@ implementation
           end;
           end;
       end;
       end;
 
 
+    procedure tarminlinenode.second_abs_long;
+      var
+        hregister : tregister;
+        opsize : tcgsize;
+        hp : taicpu;
+      begin
+        secondpass(left);
+        opsize:=def_cgsize(left.resultdef);
+        hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
+        hregister:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+        location:=left.location;
+        location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+        current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_MOV,location.register,left.location.register), PF_S));
+        current_asmdata.CurrAsmList.concat(setcondition(taicpu.op_reg_reg_const(A_RSB,location.register,location.register, 0), C_MI));
+      end;
 
 
 begin
 begin
   cinlinenode:=tarminlinenode;
   cinlinenode:=tarminlinenode;

+ 137 - 0
compiler/arm/narmmat.pas

@@ -42,6 +42,10 @@ interface
         procedure second_float;override;
         procedure second_float;override;
       end;
       end;
 
 
+      tarmshlshrnode = class(tcgshlshrnode)
+         procedure second_64bit;override;
+         function first_shlshr64bitint: tnode; override;
+      end;
 
 
 implementation
 implementation
 
 
@@ -291,9 +295,142 @@ implementation
         end;
         end;
       end;
       end;
 
 
+    function tarmshlshrnode.first_shlshr64bitint: tnode;
+      begin
+        result := nil;
+      end;
+
+    procedure tarmshlshrnode.second_64bit;
+      var
+        hreg64hi,hreg64lo,shiftreg:Tregister;
+        v : TConstExprInt;
+        l1,l2,l3:Tasmlabel;
+        so: tshifterop;
+
+      procedure emit_instr(p: tai);
+        begin
+          current_asmdata.CurrAsmList.concat(p);
+        end;
+
+      {Reg1 gets shifted and moved into reg2, and is set to zero afterwards}
+      procedure shift_more_than_32(reg1, reg2: TRegister; shiftval: Byte ; sm: TShiftMode);
+        begin
+          shifterop_reset(so); so.shiftimm:=shiftval - 32; so.shiftmode:=sm;
+          emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so));
+          emit_instr(taicpu.op_reg_const(A_MOV, reg1, 0));
+        end;
+
+      procedure shift_less_than_32(reg1, reg2: TRegister; shiftval: Byte; shiftright: boolean);
+        begin
+          shifterop_reset(so); so.shiftimm:=shiftval;
+          if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
+          emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
+
+          if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
+          so.shiftimm:=32-shiftval;
+          emit_instr(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg1, reg1, reg2, so));
+
+          if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
+          so.shiftimm:=shiftval;
+          emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so));
+        end;
+
+      procedure shift_by_variable(reg1, reg2, shiftval: TRegister; shiftright: boolean);
+        var
+          shiftval2:TRegister;
+        begin
+          shifterop_reset(so);
+          shiftval2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
+          {Do we shift more than 32 bits?}
+          emit_instr(setoppostfix(taicpu.op_reg_reg_const(A_RSB, shiftval2, shiftval, 32), PF_S));
+
+          {This part cares for 32 bits and more}
+          emit_instr(setcondition(taicpu.op_reg_reg_const(A_SUB, shiftval2, shiftval, 32), C_MI));
+          if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
+          so.rs:=shiftval2;
+          emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so), C_MI));
+
+          {Less than 32 bits}
+          so.rs:=shiftval;
+          emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so), C_PL));
+          if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
+          so.rs:=shiftval2;
+          emit_instr(setcondition(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg2, reg2, reg1, so), C_PL));
+
+          {Final adjustments}
+          if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
+          so.rs:=shiftval;
+          emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
+        end;
+
+      begin
+        location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
+
+        { load left operator in a register }
+        hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
+        hreg64hi:=left.location.register64.reghi;
+        hreg64lo:=left.location.register64.reglo;
+        location.register64.reghi:=hreg64hi;
+        location.register64.reglo:=hreg64lo;
+
+        { shifting by a constant directly coded: }
+        if (right.nodetype=ordconstn) then
+          begin
+            v:=Tordconstnode(right).value and 63;
+            {Single bit shift}
+            if v = 1 then
+              if nodetype=shln then
+                begin
+                  {Shift left by one by 2 simple 32bit additions}
+                  emit_instr(setoppostfix(taicpu.op_reg_reg_reg(A_ADD, hreg64lo, hreg64lo, hreg64lo), PF_S));
+                  emit_instr(taicpu.op_reg_reg_reg(A_ADC, hreg64hi, hreg64hi, hreg64hi));
+                end
+              else
+                begin
+                  {Shift right by first shifting hi by one and then using RRX (rotate right extended), which rotates through the carry}
+                  shifterop_reset(so); so.shiftmode:=SM_LSR; so.shiftimm:=1;
+                  emit_instr(setoppostfix(taicpu.op_reg_reg_shifterop(A_MOV, hreg64hi, hreg64hi, so), PF_S));
+                  so.shiftmode:=SM_RRX; so.shiftimm:=0; {RRX does NOT have a shift amount}
+                  emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, hreg64lo, hreg64lo, so));
+                end
+            {A 32bit shift just replaces a register and clears the other}
+            else if v = 32 then
+              begin
+                if nodetype=shln then
+                  emit_instr(taicpu.op_reg_const(A_MOV, hreg64hi, 0))
+                else
+                  emit_instr(taicpu.op_reg_const(A_MOV, hreg64lo, 0));
+                location.register64.reghi:=hreg64lo;
+                location.register64.reglo:=hreg64hi;
+              end
+            {Shift LESS than 32}
+            else if v < 32 then
+              if nodetype=shln then
+                shift_less_than_32(hreg64hi, hreg64lo, v.uvalue, false)
+              else
+                shift_less_than_32(hreg64lo, hreg64hi, v.uvalue, true)
+            {More than 32}
+            else
+              if nodetype=shln then
+                shift_more_than_32(hreg64lo, hreg64hi, v.uvalue, SM_LSL)
+              else
+                shift_more_than_32(hreg64hi, hreg64lo, v.uvalue, SM_LSR)
+          end
+        else
+          begin
+            { force right operators in a register }
+            hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,resultdef,false);
+            if nodetype = shln then
+              shift_by_variable(hreg64lo,hreg64hi,right.location.register, false)
+            else
+              shift_by_variable(hreg64hi,hreg64lo,right.location.register, true);
+          end;
+      end;
+
 
 
 begin
 begin
   cmoddivnode:=tarmmoddivnode;
   cmoddivnode:=tarmmoddivnode;
   cnotnode:=tarmnotnode;
   cnotnode:=tarmnotnode;
   cunaryminusnode:=tarmunaryminusnode;
   cunaryminusnode:=tarmunaryminusnode;
+  cshlshrnode:=tarmshlshrnode;
 end.
 end.

+ 1 - 1
compiler/options.pas

@@ -2658,7 +2658,7 @@ begin
   def_system_macro('FPC_HAS_OPERATOR_ENUMERATOR');
   def_system_macro('FPC_HAS_OPERATOR_ENUMERATOR');
   def_system_macro('FPC_HAS_CONSTREF');
   def_system_macro('FPC_HAS_CONSTREF');
   def_system_macro('FPC_STATICRIPFIXED');
   def_system_macro('FPC_STATICRIPFIXED');
-{$if defined(x86) or defined(powerpc) or defined(powerpc64)}
+{$if defined(x86) or defined(powerpc) or defined(powerpc64) or defined(cpuarm)}
   def_system_macro('FPC_HAS_INTERNAL_ABS_LONG');
   def_system_macro('FPC_HAS_INTERNAL_ABS_LONG');
 {$endif}
 {$endif}
   def_system_macro('FPC_HAS_UNICODESTRING');
   def_system_macro('FPC_HAS_UNICODESTRING');