* basic operand matching works

+ skeleton for pass 2 implemented

git-svn-id: trunk@1075 -

compiler/arm/aasmcpu.pas

@@ -102,6 +102,8 @@ uses
       OT_AM5       = $00080000;
       OT_AMMASK    = $000f0000;
 
+      OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
+      OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
       OT_MEMORYAM4 = OT_MEMORY or OT_AM4;
       OT_MEMORYAM5 = OT_MEMORY or OT_AM5;
 
@@ -960,6 +962,8 @@ implementation
               internalerror(2005091001);
             if opcode=A_None then
               internalerror(2005091004);
+            { postfix has been added to opcode }
+            oppostfix:=PF_None;
           end
         else if (opcode=A_STR) and (oppostfix<>PF_None) then
           begin
@@ -969,6 +973,8 @@ implementation
               internalerror(2005091002);
             if opcode=A_None then
               internalerror(2005091003);
+            { postfix has been added to opcode }
+            oppostfix:=PF_None;
           end;
 
         { Get InsEntry }
@@ -985,6 +991,12 @@ implementation
 
     procedure taicpu.Pass2(objdata:TAsmObjectdata);
       begin
+        { error in pass1 ? }
+        if insentry=nil then
+         exit;
+        aktfilepos:=fileinfo;
+        { Generate the instruction }
+        GenCode(objdata);
       end;
 
 
@@ -1055,6 +1067,16 @@ implementation
                         ot:=ot or OT_MEM_OFFS;
                       { if we need to fix a reference, we do it here }
 
+                      { pc relative addressing }
+                      if (ref^.base=NR_NO) and
+                        (ref^.index=NR_NO) and
+                        (ref^.shiftmode=SM_None)
+                        { at least we should check if the destination symbol
+                          is in a text section }
+                        { and
+                        (ref^.symbol^.owner="text") } then
+                        ref^.base:=NR_PC;
+
                       { determine possible address modes }
                       if (ref^.base<>NR_NO) and
                         (
@@ -1201,7 +1223,7 @@ implementation
         { update condition flags
           or floating point single }
       if (oppostfix=PF_S) and
-        not(p^.code[0] in []) then
+        not(p^.code[0] in [#$04]) then
         begin
           Matches:=0;
           exit;
@@ -1218,6 +1240,8 @@ implementation
       { multiple load/store address modes }
       if (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
         not(p^.code[0] in [
+          // ldr,str,ldrb,strb
+          #$17,
           // stm,ldm
           #$26
         ]) then
@@ -1308,11 +1332,7 @@ implementation
 
     function  taicpu.calcsize(p:PInsEntry):shortint;
       begin
-      end;
-
-
-    procedure taicpu.gencode(objdata:TAsmObjectData);
-      begin
+        result:=4;
       end;
 
 
@@ -1371,6 +1391,72 @@ implementation
         inssize:=-1;
       end;
 
+
+    procedure taicpu.gencode(objdata:TAsmObjectData);
+      var
+        bytes : dword;
+        i_field : byte;
+
+      procedure setshifterop(op : byte);
+        begin
+          case oper[op]^.typ of
+            top_const:
+              begin
+                i_field:=1;
+                bytes:=bytes or (oper[op]^.val and $fff);
+              end;
+            top_reg:
+              begin
+                i_field:=0;
+                bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16);
+
+                { does a real shifter op follow? }
+                if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then
+                  begin
+                  end;
+              end;
+          else
+            internalerror(2005091103);
+          end;
+        end;
+
+      begin
+        bytes:=$0;
+        { evaluate and set condition code }
+
+        { condition code allowed? }
+
+        { setup rest of the instruction }
+        case insentry^.code[0] of
+          #$08:
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 26);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 21);
+
+              { set destination }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+
+              { create shifter op }
+              setshifterop(1);
+
+              { set i field }
+              bytes:=bytes or (i_field shl 25);
+
+              { set s if necessary }
+              if oppostfix=PF_S then
+                bytes:=bytes or (1 shl 20);
+            end;
+          #$ff:
+            internalerror(2005091101);
+          else
+            internalerror(2005091102);
+        end;
+        { we're finished, write code }
+        objdata.writebytes(bytes,sizeof(bytes));
+      end;
+
+
 end.
 
 {$ifdef dummy}

compiler/arm/armins.dat

@@ -115,7 +115,7 @@ reg32,reg32,imm          \7\x2\x00                     ARM7
 
 [Bcc]
 mem32                    \1\x0A                        ARM7
-imm32                    \1\x0A                        ARM7
+imm24                    \1\x0A                        ARM7
 
 [BICcc]
 reg32,reg32,reg32        \4\x1\xC0                     ARM7
@@ -191,13 +191,15 @@ memam4,reglist		   \x26\x81			ARM7
 [LDRBTcc]
 
 [LDRBcc]
+reg32,memam2              \x17\x07\x10                            ARM7
 
 [LDRcc]
-reg32,imm32              \x17\x05\x10                   ARM7
-reg32,reg32              \x18\x04\x10                   ARM7
-reg32,reg32,imm32        \x19\x04\x10                   ARM7
-reg32,reg32,reg32        \x20\x06\x10                   ARM7
-reg32,reg32,reg32,imm32  \x21\x06\x10                   ARM7
+reg32,memam2              \x17\x05\x10                   ARM7
+; reg32,imm32              \x17\x05\x10                   ARM7
+; reg32,reg32              \x18\x04\x10                   ARM7
+; reg32,reg32,imm32        \x19\x04\x10                   ARM7
+; reg32,reg32,reg32        \x20\x06\x10                   ARM7
+; reg32,reg32,reg32,imm32  \x21\x06\x10                   ARM7
 
 [LDRHcc]
 reg32,imm32              \x22\x50\xB0               ARM7
@@ -235,7 +237,8 @@ reg32,mem32         \320\301\1\x13\110            ARM7
 reg32,reg32,reg32,reg32  \x15\x00\x20\x90               ARM7
 
 [MOVcc]
-reg32,shifterop              \x8\x1\xA0                   ARM7
+reg32,shifterop              \x8\x0\0xd                   ARM7
+reg32,immshifter             \x8\x0\0xd                  ARM7
 ; reg32,reg32,reg32        \x9\x1\xA0                     ARM7
 ; reg32,reg32,imm          \xA\x1\xA0                     ARM7
 ; reg32,imm                \xB\x3\xA0                     ARM7
@@ -263,7 +266,7 @@ fpureg,fpureg              \xF2                      FPA
 fpureg,immfpu              \xF2                      FPA
 
 [MVNcc]
-reg32,reg32         \x8\x1\xE0                     ARM7
+reg32,reg32         \x8\x0\0xf                     ARM7
 reg32,reg32,reg32   \x9\x1\xE0                     ARM7
 reg32,reg32,imm     \xA\x1\xE0                     ARM7
 reg32,imm           \xB\x3\xE0                     ARM7
@@ -329,13 +332,15 @@ reg32,reg32,reg32,reg32  \x16\x00\xC0\x90		 ARM7
 memam4,reglist		   \x26\x80			ARM7
 
 [STRcc]
-reg32,imm32              \x17\x05\x00                   ARM7
-reg32,reg32              \x18\x04\x00                   ARM7
-reg32,reg32,imm32        \x19\x04\x00                   ARM7
-reg32,reg32,reg32        \x20\x06\x00                   ARM7
-reg32,reg32,reg32,imm32  \x21\x06\x00                   ARM7
+reg32,memam2              \x17\x04\x00                   ARM7
+; reg32,imm32              \x17\x05\x00                   ARM7
+; reg32,reg32              \x18\x04\x00                   ARM7
+; reg32,reg32,imm32        \x19\x04\x00                   ARM7
+; reg32,reg32,reg32        \x20\x06\x00                   ARM7
+; reg32,reg32,reg32,imm32  \x21\x06\x00                   ARM7
 
 [STRBcc]
+reg32,memam2              \x17\x06\x00                           ARM7
 
 [STRBTcc]
 

compiler/arm/armnop.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armins.dat }
-113;
+108;

compiler/arm/armtab.inc

@@ -101,7 +101,7 @@
   (
     opcode  : A_B;
     ops     : 1;
-    optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none);
+    optypes : (ot_immediate24,ot_none,ot_none,ot_none);
     code    : #1#10;
     flags   : if_arm7
   ),
@@ -281,38 +281,17 @@
     flags   : if_arm7
   ),
   (
-    opcode  : A_LDR;
+    opcode  : A_LDRB;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
-    code    : #23#5#16;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
+    code    : #23#7#16;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDR;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
-    code    : #24#4#16;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_LDR;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
-    code    : #25#4#16;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_LDR;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #32#6#16;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_LDR;
-    ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate or ot_bits32);
-    code    : #33#6#16;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
+    code    : #23#5#16;
     flags   : if_arm7
   ),
   (
@@ -427,6 +406,13 @@
     code    : #8#1#160;
     flags   : if_arm7
   ),
+  (
+    opcode  : A_MOV;
+    ops     : 2;
+    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none);
+    code    : #8#1#160;
+    flags   : if_arm7
+  ),
   (
     opcode  : A_MUL;
     ops     : 3;
@@ -619,36 +605,15 @@
   (
     opcode  : A_STR;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
-    code    : #23#5#0;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
+    code    : #23#4#0;
     flags   : if_arm7
   ),
   (
-    opcode  : A_STR;
+    opcode  : A_STRB;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
-    code    : #24#4#0;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_STR;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
-    code    : #25#4#0;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_STR;
-    ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
-    code    : #32#6#0;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_STR;
-    ops     : 4;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate or ot_bits32);
-    code    : #33#6#0;
+    optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
+    code    : #23#6#0;
     flags   : if_arm7
   ),
   (