* tcgtypeconvnode.second_int_to_int: reuse 8 and 16-bit-sized register locations on targets with 32-bit-only registers when casting to larger size (except ShortInt to Word cast). This is possible because upper bits of such registers are always kept valid by code generators (see 'maybeadjustresult' method in cgcpu.pas). Removes a lot of useless register moves.

git-svn-id: trunk@25067 -

compiler/ncgcnv.pas

@@ -115,6 +115,16 @@ interface
                     location.reference.alignment:=newalignment(location.reference.alignment,leftsize-ressize);
                   end;
               end
+            { On targets without 8/16 bit register components, 8/16-bit operations
+              always adjust high bits of result, see 'maybeadjustresult' method in
+              respective cgcpu.pas. Therefore 8/16-bit locations are valid as larger
+              ones (except OS_S8->OS_16 which still needs high 16 bits cleared). }
+            else if (left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) and
+              (tcgsize2size[(reg_cgsize(left.location.register))]=sizeof(aint)) and
+              (ressize>leftsize) and
+              (newsize in [OS_32,OS_S32,OS_16,OS_S16]) and
+              not ((newsize=OS_16) and (def_cgsize(left.resultdef)=OS_S8)) then
+              location.size:=newsize
             else
               hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,resultdef,false);
           end