|
compiler
|
f3a1c749fb
* tcgtypeconvnode.second_int_to_int: reuse 8 and 16-bit-sized register locations on targets with 32-bit-only registers when casting to larger size (except ShortInt to Word cast). This is possible because upper bits of such registers are always kept valid by code generators (see 'maybeadjustresult' method in cgcpu.pas). Removes a lot of useless register moves.
|
12 years ago |
|
ide
|
415444a3a5
Fix compilation failure if DEBUG conditional is set, which needs regexpr package
|
12 years ago |
|
installer
|
c460adf8e8
Regenerate all Makefiles with an up-to-date fpcmake binary
|
12 years ago |
|
packages
|
35f74e86ad
fcl-db: tests: Add test for Master-detail (see rev.25055)
|
12 years ago |
|
rtl
|
9e4cc57768
* MIPS: handle 8 and 16-bit arithmetic shifts internally, by shifting argument left by 24/16 bits, followed with 32-bit arithmetic shift right by appropriately adjusted amount.
|
12 years ago |
|
tests
|
963a488ca2
* handle also LOC_CREGISTER/LOC_CMMREGISTER in tcgvecnode.pass_generate_code, resolves #24705
|
12 years ago |
|
utils
|
72b0e72580
* added a fix for crashes on very short fpdoc projects. x.y.z.count was examined without checking x,y and z existed.
|
12 years ago |
|
.gitattributes
|
58610af9f0
* adapt max_linear_list on x86-64 as well
|
12 years ago |
|
.gitignore
|
04df0d537e
* more finegrained parallelism support for testsuite runs: the tests are no
|
13 years ago |
|
Makefile
|
4ca7e66661
* Fixed cross-installation after r24625.
|
12 years ago |
|
Makefile.fpc
|
4ca7e66661
* Fixed cross-installation after r24625.
|
12 years ago |
|
fpmake.pp
|
df4191acb3
* Handle the location of each package at run-time, not at compilation time
|
12 years ago |
|
fpmake_add1.inc
|
df4191acb3
* Handle the location of each package at run-time, not at compilation time
|
12 years ago |
|
fpmake_proc1.inc
|
df4191acb3
* Handle the location of each package at run-time, not at compilation time
|
12 years ago |
sergei
f3a1c749fb
* tcgtypeconvnode.second_int_to_int: reuse 8 and 16-bit-sized register locations on targets with 32-bit-only registers when casting to larger size (except ShortInt to Word cast). This is possible because upper bits of such registers are always kept valid by code generators (see 'maybeadjustresult' method in cgcpu.pas). Removes a lot of useless register moves.