 florian
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da6c0e919b
+ RiscV: rv32gcb
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5 months ago |
|
florian
|
fecd25bac1
* fix typo
|
5 months ago |
|
florian
|
8e45bb133d
+ RV64GCB CPU type
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5 months ago |
|
florian
|
1202b2612f
+ RiscV: make use of the fl* rd,symbol,rd pseudoinstruction
|
7 months ago |
|
florian
|
64ba751ef1
* make use of LA pseudo-instruction
|
7 months ago |
|
florian
|
0b49fba637
+ more RiscV extensions
|
9 months ago |
|
florian
|
d4816d12f7
* Risc-V 32 has also a GC variant
|
1 year ago |
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florian
|
1ecc880fc8
+ cpu type RV64GC
|
1 year ago |
 Interferon
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8382c6f586
Added generic WCH32Vx RISC-V processor types using memory size suffixes
|
2 years ago |
 Pierre Muller
|
87e4931489
Fix fullcycle compilation error due to -Sew option
|
2 years ago |
|
Pierre Muller
|
0d256f517f
Set defualt riscv32 linux abi to abi_riscv_ipl32
|
2 years ago |
|
florian
|
0e05e908d5
riscv32-freertos:
|
2 years ago |
|
florian
|
bedd4edc72
+ first work for esp32-c3 support
|
2 years ago |
|
florian
|
a16f35dcb1
+ support RV32E Extension
|
3 years ago |
|
florian
|
e047e7db91
+ RiscV: initial support of pic generation
|
4 years ago |
|
florian
|
6f3fccddd1
* RiscV32: properly read references with record offsets and base register
|
4 years ago |
|
florian
|
5cd4e5a016
* pass lp64d to GNU AS for abi_riscv_hf to get the right ABI set
|
4 years ago |
 nickysn
|
3d81dd0b00
* ReplaceForbiddenAsmSymbolChars renamed ApplyAsmSymbolRestrictions, because now it also applies the
|
5 years ago |
|
nickysn
|
a8fe46c0f5
+ introduced labelmaxlen in tasminfo and added code in ReplaceForbiddenAsmSymbolChars that limits the
|
5 years ago |
 Jeppe Johansen
|
2678522db5
- RISC-V: Add controller types for common RV32 MCUs.
|
5 years ago |
 svenbarth
|
114c27fb4e
* increase support for multilib binutils for RISC V by passing the ABI to the assembler
|
5 years ago |
|
Jeppe Johansen
|
a1a17447ff
- Fix bug in 64bit softfloat double negation.
|
6 years ago |
 Jonas Maebe
|
281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
|
6 years ago |
|
Jeppe Johansen
|
29ea4ed07d
Add rounding mode operands.
|
7 years ago |
|
Jeppe Johansen
|
f781c8942e
Write real atomic operations, and add memory barrier operations.
|
7 years ago |
|
Jeppe Johansen
|
6352328f3a
Update packages with information about RiscV.
|
7 years ago |
|
Jeppe Johansen
|
ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
|
7 years ago |
