Commit History

Author SHA1 Message Date
  nickysn 9309e2c42e * replace 'add/adc/sub/sbc/and/or/xor/cp orgreg' with 'add/adc/sub/sbc/and/or/xor/cp spilltemp' in 5 years ago
  nickysn e43834c5d0 * replace 'inc/dec orgreg' with 'inc/dec spilltemp' in trgcpu.do_spill_replace 5 years ago
  nickysn 9d545342f8 * replace 'add/adc/sub/sbc/and/or/xor/cp A,orgreg' with 'add/adc/sub/sbc/and/or/xor/cp A,spilltemp' in trgcpu.do_spill_replace 5 years ago
  nickysn a58bab4318 + replace 'ld orgreg,const' with 'ld spilltemp,const' in trgcpu.do_spill_replace 5 years ago
  nickysn fe3f4a7447 * fixes in trgcpu.do_spill_replace 5 years ago
  nickysn 8ceee70912 * range check for spilltemp.offset in [-128..127], not [0..63] in trgcpu.do_spill_replace for Z80 5 years ago
  nickysn 8291d24b7f * fix comment 5 years ago
  nickysn 65efc495af + add edges to disallow the use of the 8-bit subregisters of IX, IY and SP 5 years ago
  florian e370e9ba15 * register names fixed 8 years ago
  florian ea52a23179 + skeleton for Z80 support 8 years ago