| .. |
|
aasmcpu.pas
|
20dbda751a
* fixed sparc compilation after addr_lo/hi changes
|
18 years ago |
|
aoptcpu.pas
|
790a4fe2d3
* log and id tags removed
|
20 years ago |
|
aoptcpub.pas
|
2f5ce095ce
* RefsHaveIndexReg -> cpurefshaveindexreg
|
13 years ago |
|
aoptcpud.pas
|
790a4fe2d3
* log and id tags removed
|
20 years ago |
|
cgcpu.pas
|
05489d6e05
* SPARC: fixed g_intf_wrapper for non-virtual methods once again, my initial assumption was not correct: a wrapper does not necessarily reference methods from the class that implements the interface, it may be methods from parent classes, which can be located arbitrarily far away in address space.
|
11 years ago |
|
cpubase.pas
|
eaba90dda7
* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches.
|
11 years ago |
|
cpuelf.pas
|
0aa7204707
+ Added codes of dynamic relocations to TElfTarget; since most targets use similar dynamic relocation model differing only in code values, this will allow to do majority of handling in the base class.
|
12 years ago |
|
cpugas.pas
|
176d8434e4
* SPARC: completely rewrote PIC-related code, got it twice shorter in source lines and much less instructions in generated code.
|
11 years ago |
|
cpuinfo.pas
|
e190f76dd9
* removed spaces from sparc cpu name strings so they can be much easier used
|
13 years ago |
|
cpunode.pas
|
b270a1922b
* reverts r18960, should solve sparc trouble
|
14 years ago |
|
cpupara.pas
|
d70a880f33
* SPARC: properly justify parameters on stack with size less than 4, fixes failure on tests/cg/tcalext5.pp
|
11 years ago |
|
cpupi.pas
|
176d8434e4
* SPARC: completely rewrote PIC-related code, got it twice shorter in source lines and much less instructions in generated code.
|
11 years ago |
|
cputarg.pas
|
7587145320
Add possibility to test sparc elf generator with -dTEST_AGSPARC_ELF
|
13 years ago |
|
hlcgcpu.pas
|
72e9cfee24
* create/destroy also the high level code generator for all architectures,
|
14 years ago |
|
itcpugas.pas
|
790a4fe2d3
* log and id tags removed
|
20 years ago |
|
ncpuadd.pas
|
34cde7a07a
* SPARC, tsparcaddnode.second_cmp64bit: don't copy LOC_CREGISTER locations, and handle comparison with constants without loading them into register (if possible).
|
11 years ago |
|
ncpucall.pas
|
51825b6f2e
compiler: change ret_in_param to accept tabstractprocdef instead of tproccalloption to allow check more options (required for record constructor implementation)
|
12 years ago |
|
ncpucnv.pas
|
58cc531dd9
* SPARC: convert from int64/qword to float using genmath helpers. Removes dependency on softfloat code.
|
11 years ago |
|
ncpuinln.pas
|
6b8aed593f
* remove registers{int/mmx/fpu} from firstpass
|
18 years ago |
|
ncpumat.pas
|
6469d41e2a
* SPARC: removed 32 bit shift code, and adjusted 64-bit shifts to take advantage of 3-address instructions (a port of r26142 for MIPS)
|
11 years ago |
|
ncpuset.pas
|
c766c50907
* Proper fix for SPARC cycling with -dCHECK_PIC, pi_needs_got additionally must be set in following cases:
|
12 years ago |
|
opcode.inc
|
9a486d73ba
+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.
|
11 years ago |
|
racpu.pas
|
18eb495d0f
* give a regular error message instead of an internal error on x86
|
18 years ago |
|
racpugas.pas
|
eaba90dda7
* SPARC: since peephole optimizer recognizes only one conditional branching instruction, generate all branches using A_Bxx opcode, and change it to A_FBxx if necessary when writing assembler. This enables optimization of floating-point branches.
|
11 years ago |
|
rgcpu.pas
|
f302fcdc98
+ TSubRegisterSet definition forgotten to commit in r15952
|
15 years ago |
|
rspcon.inc
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
rspdwrf.inc
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
rspnor.inc
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
rspnum.inc
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
rsprni.inc
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
rspsri.inc
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
rspstab.inc
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
rspstd.inc
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
rspsup.inc
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
spreg.dat
|
c3da1aa542
Reenabled D0-D30 registers
|
13 years ago |
|
strinst.inc
|
9a486d73ba
+ SPARC: support FNEGd/FNEGq internal instructions, and use them to implement floating-point negation more efficiently.
|
11 years ago |
sergei
05489d6e05
* SPARC: fixed g_intf_wrapper for non-virtual methods once again, my initial assumption was not correct: a wrapper does not necessarily reference methods from the class that implements the interface, it may be methods from parent classes, which can be located arbitrarily far away in address space.