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a64att.inc
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fb7cdbefb3
+ some opcodes added
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%!s(int64=3) %!d(string=hai) anos |
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a64atts.inc
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fb7cdbefb3
+ some opcodes added
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%!s(int64=3) %!d(string=hai) anos |
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a64ins.dat
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fb7cdbefb3
+ some opcodes added
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%!s(int64=3) %!d(string=hai) anos |
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a64nop.inc
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0197b84b7f
+ instruction table generator for arm64
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%!s(int64=13) %!d(string=hai) anos |
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a64op.inc
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fb7cdbefb3
+ some opcodes added
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%!s(int64=3) %!d(string=hai) anos |
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a64reg.dat
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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a64tab.inc
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585e4a9a14
* corrected cosmetic ARM/AArch64 copy/paste leftovers (patch by
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%!s(int64=10) %!d(string=hai) anos |
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aasmcpu.pas
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23e514621d
* a64: Corrected supported shifter/extender mnemonics for arithmetic/logical instructions
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hai 1 ano |
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agcpugas.pas
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5a123d33ba
Add -Awin64-as option for aarch64 compiler for win64 target
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%!s(int64=2) %!d(string=hai) anos |
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aoptcpu.pas
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72081c803e
* a64: SkipAligns calls removed.
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hai 1 ano |
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aoptcpub.pas
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281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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%!s(int64=6) %!d(string=hai) anos |
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aoptcpud.pas
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e1af3ecc5d
+ assembler optimizer unit skeleton
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%!s(int64=13) %!d(string=hai) anos |
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cgcpu.pas
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dfb8794d4d
* compilation after merge fixed
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%!s(int64=2) %!d(string=hai) anos |
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cpubase.pas
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23e514621d
* a64: Corrected supported shifter/extender mnemonics for arithmetic/logical instructions
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hai 1 ano |
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cpuinfo.pas
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27fb9086aa
* cleanup: cs_opt_loopunroll is a generic optimization for a long time already
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%!s(int64=3) %!d(string=hai) anos |
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cpunode.pas
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53e5a4a03a
Adding aaarch64-embedded target
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%!s(int64=3) %!d(string=hai) anos |
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cpupara.pas
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657f3c52bf
* according to Jonas iOS doesn't zero extend results in the callee either, so check removed
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%!s(int64=2) %!d(string=hai) anos |
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cpupi.pas
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2b59000d56
+ implement compiler support for SEH on Win64
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%!s(int64=5) %!d(string=hai) anos |
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cputarg.pas
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53e5a4a03a
Adding aaarch64-embedded target
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%!s(int64=3) %!d(string=hai) anos |
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hlcgcpu.pas
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7c9fb4b4af
* AArch64: fix storing a 32 bit value in the lower 32 bits of a 64 bit
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%!s(int64=4) %!d(string=hai) anos |
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itcpugas.pas
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046184dfe9
+ ARM64 GAS instruction table unit
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%!s(int64=13) %!d(string=hai) anos |
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naarch64util.pas
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86c097086a
Additional copyright header
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%!s(int64=3) %!d(string=hai) anos |
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ncpuadd.pas
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afe2e80673
* a64: Node parser now attempts to directly create BIC, ORN and EON instructions
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hai 1 ano |
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ncpucnv.pas
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4357caaad8
* Removed unused local vars.
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%!s(int64=6) %!d(string=hai) anos |
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ncpucon.pas
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a019536cd5
* avoid that -0.0 is handled by the eor optimization
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%!s(int64=6) %!d(string=hai) anos |
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ncpuflw.pas
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637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
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%!s(int64=4) %!d(string=hai) anos |
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ncpuinl.pas
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e443936e12
+ in_min/max_dword/longint support for aarch64
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%!s(int64=3) %!d(string=hai) anos |
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ncpumat.pas
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5ef44c550a
Avoid range/overflow error after commit #49290
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%!s(int64=4) %!d(string=hai) anos |
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ncpumem.pas
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4686f61002
* keep track of the temp position separately from the offset in references,
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%!s(int64=7) %!d(string=hai) anos |
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ncpuset.pas
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7f4b94e408
* generate jump tables into the same section as the code as otherwise we'll get bogus relocations (in case of clang.exe) or a future support for armasm64.exe will reject the relative symbols outright
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%!s(int64=5) %!d(string=hai) anos |
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ra64con.inc
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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ra64dwa.inc
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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ra64nor.inc
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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ra64num.inc
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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ra64rni.inc
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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ra64sri.inc
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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ra64sta.inc
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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ra64std.inc
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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ra64sup.inc
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7cefe8a822
Adding AArch64 CurrentEL register
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%!s(int64=3) %!d(string=hai) anos |
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racpu.pas
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9376f5a43a
* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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%!s(int64=4) %!d(string=hai) anos |
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racpugas.pas
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9813eb9048
AArch64 asm reader: add support for fpcmp(e) conditions
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%!s(int64=3) %!d(string=hai) anos |
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rgcpu.pas
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bb977b398d
* AArch64: fix spilling integer registers to stack offsets that cannot be
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%!s(int64=4) %!d(string=hai) anos |
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symcpu.pas
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7dd1d6aa77
o fixes handling of iso i/o parameters/program parameters:
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%!s(int64=10) %!d(string=hai) anos |
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tripletcpu.pas
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eb7ba1690e
* mark all external assemblers using an LLVM tool using af_llvm
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%!s(int64=5) %!d(string=hai) anos |
J. Gareth "Curious Kit" Moreton
72081c803e
* a64: SkipAligns calls removed.