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aoptcpu.pas
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39f7172ee8
* do no generated debug comment in assembler output of RiscV if not requested
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1 year ago |
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aoptcpub.pas
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9b0ff05ee8
- get rid of MaxOps, it is redundant with max_operands
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6 years ago |
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aoptcpuc.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
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aoptcpud.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
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cgcpu.pas
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5bb4049737
* remove accidently committed debug statement
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7 months ago |
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cpuinfo.pas
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0b49fba637
+ more RiscV extensions
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9 months ago |
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cpunode.pas
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971d97c179
+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0
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7 months ago |
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cpupara.pas
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b7608b045b
* RiscV: push_addr_param unified
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8 months ago |
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cpupi.pas
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281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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6 years ago |
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cputarg.pas
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d1fb44044f
* unified RiscV32 and RiscV64 GAS readers
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4 years ago |
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hlcgcpu.pas
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d4c9e1f260
Replace outdated cgop2string function by tcgsize2str function from cgbase unit to fix EXTDEBUG cycle on powerpc64le-linux
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5 years ago |
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nrv64add.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
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nrv64cal.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
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nrv64cnv.pas
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f3b7e3281a
* fix int to real for non-register locations
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7 years ago |
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nrv64ld.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
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nrv64mat.pas
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c3110dfaa9
+ RiscV: make use of the fneg.* instruction
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7 months ago |
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rrv64con.inc
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8d0bdf2f16
+ RiscV: vector registers
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8 months ago |
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rrv64dwa.inc
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8d0bdf2f16
+ RiscV: vector registers
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8 months ago |
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rrv64nor.inc
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8d0bdf2f16
+ RiscV: vector registers
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8 months ago |
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rrv64num.inc
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8d0bdf2f16
+ RiscV: vector registers
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8 months ago |
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rrv64rni.inc
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8d0bdf2f16
+ RiscV: vector registers
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8 months ago |
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rrv64sri.inc
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8d0bdf2f16
+ RiscV: vector registers
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8 months ago |
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rrv64sta.inc
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8d0bdf2f16
+ RiscV: vector registers
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8 months ago |
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rrv64std.inc
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8d0bdf2f16
+ RiscV: vector registers
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8 months ago |
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rrv64sup.inc
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8d0bdf2f16
+ RiscV: vector registers
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8 months ago |
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symcpu.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
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tripletcpu.pas
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52147baa04
* correct tripletcpustr, resolves #40301
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2 years ago |
florian
5bb4049737
* remove accidently committed debug statement