cgcpu.pas 65 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_load_reg_cgpara(list : TAsmList; size : tcgsize;r : tregister; const cgpara : tcgpara);override;
  40. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  41. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister); override;
  44. { move instructions }
  45. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  46. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  47. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  48. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  49. { fpu move instructions }
  50. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  51. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  52. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  53. { comparison operations }
  54. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  55. l : tasmlabel);override;
  56. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  57. procedure a_jmp_name(list : TAsmList;const s : string); override;
  58. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  59. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  60. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  61. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  62. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  63. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  64. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  65. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  66. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  67. procedure g_save_registers(list : TAsmList);override;
  68. procedure g_restore_registers(list : TAsmList);override;
  69. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  70. procedure fixref(list : TAsmList;var ref : treference);
  71. function normalize_ref(list : TAsmList;ref : treference;
  72. tmpreg : tregister) : treference;
  73. procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
  74. procedure g_stackpointer_alloc(list : TAsmList;size : longint);override;
  75. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  76. procedure a_adjust_sp(list: TAsmList; value: longint);
  77. function GetLoad(const ref : treference) : tasmop;
  78. function GetStore(const ref: treference): tasmop;
  79. procedure a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister); override;
  80. protected
  81. procedure a_op_reg_reg_internal(list: TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  82. procedure a_op_const_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg, reghi: TRegister);
  83. end;
  84. tcg64favr = class(tcg64f32)
  85. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  86. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  87. end;
  88. procedure create_codegen;
  89. const
  90. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  91. A_NONE,A_MUL,A_MULS,A_NEG,A_COM,A_OR,
  92. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  93. implementation
  94. uses
  95. globals,verbose,systems,cutils,
  96. fmodule,
  97. symconst,symsym,symtable,
  98. tgobj,rgobj,
  99. procinfo,cpupi,
  100. paramgr;
  101. procedure tcgavr.init_register_allocators;
  102. begin
  103. inherited init_register_allocators;
  104. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  105. [RS_R8,RS_R9,
  106. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17,RS_R18,RS_R19,
  107. RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  108. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7],first_int_imreg,[]);
  109. { rg[R_ADDRESSREGISTER]:=trgintcpu.create(R_ADDRESSREGISTER,R_SUBWHOLE,
  110. [RS_R26,RS_R30],first_int_imreg,[]); }
  111. end;
  112. procedure tcgavr.done_register_allocators;
  113. begin
  114. rg[R_INTREGISTER].free;
  115. // rg[R_ADDRESSREGISTER].free;
  116. inherited done_register_allocators;
  117. end;
  118. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  119. var
  120. tmp1,tmp2,tmp3 : TRegister;
  121. begin
  122. case size of
  123. OS_8,OS_S8:
  124. Result:=inherited getintregister(list, size);
  125. OS_16,OS_S16:
  126. begin
  127. Result:=inherited getintregister(list, OS_8);
  128. { ensure that the high register can be retrieved by
  129. GetNextReg
  130. }
  131. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  132. internalerror(2011021331);
  133. end;
  134. OS_32,OS_S32:
  135. begin
  136. Result:=inherited getintregister(list, OS_8);
  137. tmp1:=inherited getintregister(list, OS_8);
  138. { ensure that the high register can be retrieved by
  139. GetNextReg
  140. }
  141. if tmp1<>GetNextReg(Result) then
  142. internalerror(2011021332);
  143. tmp2:=inherited getintregister(list, OS_8);
  144. { ensure that the upper register can be retrieved by
  145. GetNextReg
  146. }
  147. if tmp2<>GetNextReg(tmp1) then
  148. internalerror(2011021333);
  149. tmp3:=inherited getintregister(list, OS_8);
  150. { ensure that the upper register can be retrieved by
  151. GetNextReg
  152. }
  153. if tmp3<>GetNextReg(tmp2) then
  154. internalerror(2011021334);
  155. end;
  156. else
  157. internalerror(2011021330);
  158. end;
  159. end;
  160. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  161. begin
  162. Result:=getintregister(list,OS_ADDR);
  163. end;
  164. procedure tcgavr.a_load_reg_cgpara(list : TAsmList;size : tcgsize;r : tregister;const cgpara : tcgpara);
  165. procedure load_para_loc(r : TRegister;paraloc : PCGParaLocation);
  166. var
  167. ref : treference;
  168. begin
  169. paramanager.allocparaloc(list,paraloc);
  170. case paraloc^.loc of
  171. LOC_REGISTER,LOC_CREGISTER:
  172. a_load_reg_reg(list,paraloc^.size,paraloc^.size,r,paraloc^.register);
  173. LOC_REFERENCE,LOC_CREFERENCE:
  174. begin
  175. reference_reset_base(ref,paraloc^.reference.index,paraloc^.reference.offset,2);
  176. a_load_reg_ref(list,paraloc^.size,paraloc^.size,r,ref);
  177. end;
  178. else
  179. internalerror(2002071004);
  180. end;
  181. end;
  182. var
  183. i : longint;
  184. hp : PCGParaLocation;
  185. begin
  186. { if use_push(cgpara) then
  187. begin
  188. if tcgsize2size[cgpara.Size] > 2 then
  189. begin
  190. if tcgsize2size[cgpara.Size] <> 4 then
  191. internalerror(2013031101);
  192. if cgpara.location^.Next = nil then
  193. begin
  194. if tcgsize2size[cgpara.location^.size] <> 4 then
  195. internalerror(2013031101);
  196. end
  197. else
  198. begin
  199. if tcgsize2size[cgpara.location^.size] <> 2 then
  200. internalerror(2013031101);
  201. if tcgsize2size[cgpara.location^.Next^.size] <> 2 then
  202. internalerror(2013031101);
  203. if cgpara.location^.Next^.Next <> nil then
  204. internalerror(2013031101);
  205. end;
  206. if tcgsize2size[cgpara.size]>cgpara.alignment then
  207. pushsize:=cgpara.size
  208. else
  209. pushsize:=int_cgsize(cgpara.alignment);
  210. pushsize2 := int_cgsize(tcgsize2size[pushsize] - 2);
  211. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize2],makeregsize(list,GetNextReg(r),pushsize2)));
  212. list.concat(taicpu.op_reg(A_PUSH,S_W,makeregsize(list,r,OS_16)));
  213. end
  214. else
  215. begin
  216. cgpara.check_simple_location;
  217. if tcgsize2size[cgpara.location^.size]>cgpara.alignment then
  218. pushsize:=cgpara.location^.size
  219. else
  220. pushsize:=int_cgsize(cgpara.alignment);
  221. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize],makeregsize(list,r,pushsize)));
  222. end;
  223. end
  224. else }
  225. begin
  226. if not(tcgsize2size[cgpara.Size] in [1..4]) then
  227. internalerror(2014011101);
  228. hp:=cgpara.location;
  229. for i:=1 to tcgsize2size[cgpara.Size] do
  230. begin
  231. if not(assigned(hp)) or
  232. (tcgsize2size[hp^.size]<>1) or
  233. (hp^.shiftval<>0) then
  234. internalerror(2014011102);
  235. load_para_loc(r,hp);
  236. hp:=hp^.Next;
  237. r:=GetNextReg(r);
  238. end;
  239. if assigned(hp) then
  240. internalerror(2014011103);
  241. end;
  242. end;
  243. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  244. var
  245. i : longint;
  246. hp : PCGParaLocation;
  247. begin
  248. if not(tcgsize2size[paraloc.Size] in [1..4]) then
  249. internalerror(2014011101);
  250. hp:=paraloc.location;
  251. for i:=1 to tcgsize2size[paraloc.Size] do
  252. begin
  253. if not(assigned(hp)) or
  254. (tcgsize2size[hp^.size]<>1) or
  255. (hp^.shiftval<>0) then
  256. internalerror(2014011105);
  257. case hp^.loc of
  258. LOC_REGISTER,LOC_CREGISTER:
  259. a_load_const_reg(list,hp^.size,(a shr (i-1)) and $ff,hp^.register);
  260. LOC_REFERENCE,LOC_CREFERENCE:
  261. begin
  262. list.concat(taicpu.op_const(A_PUSH,(a shr (i-1)) and $ff));
  263. end;
  264. else
  265. internalerror(2002071004);
  266. end;
  267. hp:=hp^.Next;
  268. end;
  269. if assigned(hp) then
  270. internalerror(2014011104);
  271. end;
  272. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  273. var
  274. tmpref, ref: treference;
  275. location: pcgparalocation;
  276. sizeleft: tcgint;
  277. begin
  278. location := paraloc.location;
  279. tmpref := r;
  280. sizeleft := paraloc.intsize;
  281. while assigned(location) do
  282. begin
  283. paramanager.allocparaloc(list,location);
  284. case location^.loc of
  285. LOC_REGISTER,LOC_CREGISTER:
  286. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  287. LOC_REFERENCE:
  288. begin
  289. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  290. { doubles in softemu mode have a strange order of registers and references }
  291. if location^.size=OS_32 then
  292. g_concatcopy(list,tmpref,ref,4)
  293. else
  294. begin
  295. g_concatcopy(list,tmpref,ref,sizeleft);
  296. if assigned(location^.next) then
  297. internalerror(2005010710);
  298. end;
  299. end;
  300. LOC_VOID:
  301. begin
  302. // nothing to do
  303. end;
  304. else
  305. internalerror(2002081103);
  306. end;
  307. inc(tmpref.offset,tcgsize2size[location^.size]);
  308. dec(sizeleft,tcgsize2size[location^.size]);
  309. location := location^.next;
  310. end;
  311. end;
  312. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  313. var
  314. tmpreg: tregister;
  315. begin
  316. tmpreg:=getaddressregister(list);
  317. a_loadaddr_ref_reg(list,r,tmpreg);
  318. a_load_reg_cgpara(list,OS_ADDR,tmpreg,paraloc);
  319. end;
  320. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  321. begin
  322. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  323. {
  324. the compiler does not properly set this flag anymore in pass 1, and
  325. for now we only need it after pass 2 (I hope) (JM)
  326. if not(pi_do_call in current_procinfo.flags) then
  327. internalerror(2003060703);
  328. }
  329. include(current_procinfo.flags,pi_do_call);
  330. end;
  331. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  332. begin
  333. a_reg_alloc(list,NR_ZLO);
  334. a_reg_alloc(list,NR_ZHI);
  335. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  336. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  337. list.concat(taicpu.op_none(A_ICALL));
  338. a_reg_dealloc(list,NR_ZLO);
  339. a_reg_dealloc(list,NR_ZHI);
  340. include(current_procinfo.flags,pi_do_call);
  341. end;
  342. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  343. begin
  344. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  345. internalerror(2012102403);
  346. a_op_const_reg_internal(list,Op,size,a,reg,NR_NO);
  347. end;
  348. procedure tcgavr.a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister);
  349. begin
  350. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  351. internalerror(2012102401);
  352. a_op_reg_reg_internal(list,Op,size,src,NR_NO,dst,NR_NO);
  353. end;
  354. procedure tcgavr.a_op_reg_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  355. var
  356. countreg,
  357. tmpreg: tregister;
  358. i : integer;
  359. instr : taicpu;
  360. paraloc1,paraloc2,paraloc3 : TCGPara;
  361. l1,l2 : tasmlabel;
  362. pd : tprocdef;
  363. procedure NextSrcDst;
  364. begin
  365. if i=5 then
  366. begin
  367. dst:=dsthi;
  368. src:=srchi;
  369. end
  370. else
  371. begin
  372. dst:=GetNextReg(dst);
  373. src:=GetNextReg(src);
  374. end;
  375. end;
  376. { iterates TmpReg through all registers of dst }
  377. procedure NextTmp;
  378. begin
  379. if i=5 then
  380. tmpreg:=dsthi
  381. else
  382. tmpreg:=GetNextReg(tmpreg);
  383. end;
  384. begin
  385. case op of
  386. OP_ADD:
  387. begin
  388. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  389. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  390. begin
  391. for i:=2 to tcgsize2size[size] do
  392. begin
  393. NextSrcDst;
  394. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  395. end;
  396. end;
  397. end;
  398. OP_SUB:
  399. begin
  400. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  401. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  402. begin
  403. for i:=2 to tcgsize2size[size] do
  404. begin
  405. NextSrcDst;
  406. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  407. end;
  408. end;
  409. end;
  410. OP_NEG:
  411. begin
  412. if src<>dst then
  413. a_load_reg_reg(list,size,size,src,dst);
  414. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  415. begin
  416. tmpreg:=GetNextReg(dst);
  417. for i:=2 to tcgsize2size[size] do
  418. begin
  419. list.concat(taicpu.op_reg(A_COM,tmpreg));
  420. NextTmp;
  421. end;
  422. list.concat(taicpu.op_reg(A_NEG,dst));
  423. tmpreg:=GetNextReg(dst);
  424. for i:=2 to tcgsize2size[size] do
  425. begin
  426. list.concat(taicpu.op_reg_const(A_SBCI,dst,-1));
  427. NextTmp;
  428. end;
  429. end;
  430. end;
  431. OP_NOT:
  432. begin
  433. for i:=1 to tcgsize2size[size] do
  434. begin
  435. if src<>dst then
  436. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  437. list.concat(taicpu.op_reg(A_COM,dst));
  438. NextSrcDst;
  439. end;
  440. end;
  441. OP_MUL,OP_IMUL:
  442. begin
  443. if size in [OS_8,OS_S8] then
  444. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src))
  445. else if size=OS_16 then
  446. begin
  447. pd:=search_system_proc('fpc_mul_word');
  448. paraloc1.init;
  449. paraloc2.init;
  450. paraloc3.init;
  451. paramanager.getintparaloc(pd,1,paraloc1);
  452. paramanager.getintparaloc(pd,2,paraloc2);
  453. paramanager.getintparaloc(pd,3,paraloc3);
  454. a_load_const_cgpara(list,OS_8,0,paraloc3);
  455. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  456. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  457. paramanager.freecgpara(list,paraloc3);
  458. paramanager.freecgpara(list,paraloc2);
  459. paramanager.freecgpara(list,paraloc1);
  460. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  461. a_call_name(list,'FPC_MUL_WORD',false);
  462. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  463. cg.a_reg_alloc(list,NR_FUNCTION_RESULT_REG);
  464. cg.a_load_reg_reg(list,OS_16,OS_16,NR_FUNCTION_RESULT_REG,dst);
  465. paraloc3.done;
  466. paraloc2.done;
  467. paraloc1.done;
  468. end
  469. else
  470. internalerror(2011022002);
  471. end;
  472. OP_DIV,OP_IDIV:
  473. { special stuff, needs separate handling inside code }
  474. { generator }
  475. internalerror(2011022001);
  476. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  477. begin
  478. current_asmdata.getjumplabel(l1);
  479. current_asmdata.getjumplabel(l2);
  480. countreg:=getintregister(list,OS_8);
  481. a_load_reg_reg(list,size,OS_8,src,countreg);
  482. list.concat(taicpu.op_reg_const(A_CP,countreg,0));
  483. a_jmp_flags(list,F_EQ,l2);
  484. cg.a_label(list,l1);
  485. case op of
  486. OP_SHR:
  487. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  488. OP_SHL:
  489. list.concat(taicpu.op_reg(A_LSL,dst));
  490. OP_SAR:
  491. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  492. OP_ROR:
  493. begin
  494. { load carry? }
  495. if not(size in [OS_8,OS_S8]) then
  496. begin
  497. list.concat(taicpu.op_none(A_CLC));
  498. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  499. list.concat(taicpu.op_none(A_SEC));
  500. end;
  501. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  502. end;
  503. OP_ROL:
  504. begin
  505. { load carry? }
  506. if not(size in [OS_8,OS_S8]) then
  507. begin
  508. list.concat(taicpu.op_none(A_CLC));
  509. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1),7));
  510. list.concat(taicpu.op_none(A_SEC));
  511. end;
  512. list.concat(taicpu.op_reg(A_ROL,dst))
  513. end;
  514. else
  515. internalerror(2011030901);
  516. end;
  517. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  518. begin
  519. for i:=2 to tcgsize2size[size] do
  520. begin
  521. case op of
  522. OP_ROR,
  523. OP_SHR:
  524. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  525. OP_ROL,
  526. OP_SHL:
  527. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(dst,dsthi,i-1)));
  528. OP_SAR:
  529. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  530. else
  531. internalerror(2011030902);
  532. end;
  533. end;
  534. end;
  535. a_op_const_reg(list,OP_SUB,OS_8,1,countreg);
  536. a_jmp_flags(list,F_NE,l1);
  537. // keep registers alive
  538. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  539. cg.a_label(list,l2);
  540. end;
  541. OP_AND,OP_OR,OP_XOR:
  542. begin
  543. for i:=1 to tcgsize2size[size] do
  544. begin
  545. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  546. NextSrcDst;
  547. end;
  548. end;
  549. else
  550. internalerror(2011022004);
  551. end;
  552. end;
  553. procedure tcgavr.a_op_const_reg_internal(list: TAsmList; Op: TOpCG;
  554. size: TCGSize; a: tcgint; reg, reghi: TRegister);
  555. var
  556. mask : qword;
  557. shift : byte;
  558. i : byte;
  559. tmpreg : tregister;
  560. tmpreg64 : tregister64;
  561. procedure NextReg;
  562. begin
  563. if i=5 then
  564. reg:=reghi
  565. else
  566. reg:=GetNextReg(reg);
  567. end;
  568. begin
  569. mask:=$ff;
  570. shift:=0;
  571. case op of
  572. OP_OR:
  573. begin
  574. for i:=1 to tcgsize2size[size] do
  575. begin
  576. list.concat(taicpu.op_reg_const(A_ORI,reg,(a and mask) shr shift));
  577. NextReg;
  578. mask:=mask shl 8;
  579. inc(shift,8);
  580. end;
  581. end;
  582. OP_AND:
  583. begin
  584. for i:=1 to tcgsize2size[size] do
  585. begin
  586. list.concat(taicpu.op_reg_const(A_ANDI,reg,(a and mask) shr shift));
  587. NextReg;
  588. mask:=mask shl 8;
  589. inc(shift,8);
  590. end;
  591. end;
  592. OP_SUB:
  593. begin
  594. list.concat(taicpu.op_reg_const(A_SUBI,reg,a));
  595. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  596. begin
  597. for i:=2 to tcgsize2size[size] do
  598. begin
  599. NextReg;
  600. mask:=mask shl 8;
  601. inc(shift,8);
  602. list.concat(taicpu.op_reg_const(A_SBCI,reg,(a and mask) shr shift));
  603. end;
  604. end;
  605. end;
  606. else
  607. begin
  608. if size in [OS_64,OS_S64] then
  609. begin
  610. tmpreg64.reglo:=getintregister(list,OS_32);
  611. tmpreg64.reghi:=getintregister(list,OS_32);
  612. cg64.a_load64_const_reg(list,a,tmpreg64);
  613. cg64.a_op64_reg_reg(list,op,size,tmpreg64,joinreg64(reg,reghi));
  614. end
  615. else
  616. begin
  617. tmpreg:=getintregister(list,size);
  618. a_load_const_reg(list,size,a,tmpreg);
  619. a_op_reg_reg(list,op,size,tmpreg,reg);
  620. end;
  621. end;
  622. end;
  623. end;
  624. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  625. var
  626. mask : qword;
  627. shift : byte;
  628. i : byte;
  629. begin
  630. mask:=$ff;
  631. shift:=0;
  632. for i:=1 to tcgsize2size[size] do
  633. begin
  634. if ((qword(a) and mask) shr shift)=0 then
  635. emit_mov(list,reg,NR_R1)
  636. else
  637. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  638. mask:=mask shl 8;
  639. inc(shift,8);
  640. reg:=GetNextReg(reg);
  641. end;
  642. end;
  643. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  644. procedure maybegetcpuregister(list:tasmlist;reg : tregister);
  645. begin
  646. { allocate the register only, if a cpu register is passed }
  647. if getsupreg(reg)<first_int_imreg then
  648. getcpuregister(list,reg);
  649. end;
  650. var
  651. tmpref : treference;
  652. l : tasmlabel;
  653. begin
  654. Result:=ref;
  655. if ref.addressmode<>AM_UNCHANGED then
  656. internalerror(2011021701);
  657. { Be sure to have a base register }
  658. if (ref.base=NR_NO) then
  659. begin
  660. { only symbol+offset? }
  661. if ref.index=NR_NO then
  662. exit;
  663. ref.base:=ref.index;
  664. ref.index:=NR_NO;
  665. end;
  666. if assigned(ref.symbol) or (ref.offset<>0) then
  667. begin
  668. reference_reset(tmpref,0);
  669. tmpref.symbol:=ref.symbol;
  670. tmpref.offset:=ref.offset;
  671. tmpref.refaddr:=addr_lo8;
  672. maybegetcpuregister(list,tmpreg);
  673. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  674. tmpref.refaddr:=addr_hi8;
  675. maybegetcpuregister(list,GetNextReg(tmpreg));
  676. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  677. if (ref.base<>NR_NO) then
  678. begin
  679. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  680. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  681. end;
  682. if (ref.index<>NR_NO) then
  683. begin
  684. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  685. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  686. end;
  687. ref.symbol:=nil;
  688. ref.offset:=0;
  689. ref.base:=tmpreg;
  690. ref.index:=NR_NO;
  691. end
  692. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  693. begin
  694. maybegetcpuregister(list,tmpreg);
  695. emit_mov(list,tmpreg,ref.index);
  696. maybegetcpuregister(list,GetNextReg(tmpreg));
  697. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  698. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  699. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  700. ref.base:=tmpreg;
  701. ref.index:=NR_NO;
  702. end
  703. else if (ref.base<>NR_NO) then
  704. begin
  705. maybegetcpuregister(list,tmpreg);
  706. emit_mov(list,tmpreg,ref.base);
  707. maybegetcpuregister(list,GetNextReg(tmpreg));
  708. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  709. ref.base:=tmpreg;
  710. ref.index:=NR_NO;
  711. end
  712. else if (ref.index<>NR_NO) then
  713. begin
  714. maybegetcpuregister(list,tmpreg);
  715. emit_mov(list,tmpreg,ref.index);
  716. maybegetcpuregister(list,GetNextReg(tmpreg));
  717. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  718. ref.base:=tmpreg;
  719. ref.index:=NR_NO;
  720. end;
  721. Result:=ref;
  722. end;
  723. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  724. var
  725. href : treference;
  726. conv_done: boolean;
  727. tmpreg : tregister;
  728. i : integer;
  729. QuickRef : Boolean;
  730. begin
  731. QuickRef:=false;
  732. if not((Ref.addressmode=AM_UNCHANGED) and
  733. (Ref.symbol=nil) and
  734. ((Ref.base=NR_R28) or
  735. (Ref.base=NR_R29)) and
  736. (Ref.Index=NR_No) and
  737. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  738. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  739. href:=normalize_ref(list,Ref,NR_R30)
  740. else
  741. begin
  742. QuickRef:=true;
  743. href:=Ref;
  744. end;
  745. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  746. internalerror(2011021307);
  747. conv_done:=false;
  748. if tosize<>fromsize then
  749. begin
  750. conv_done:=true;
  751. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  752. fromsize:=tosize;
  753. case fromsize of
  754. OS_8:
  755. begin
  756. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  757. href.addressmode:=AM_POSTINCREMENT;
  758. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  759. for i:=2 to tcgsize2size[tosize] do
  760. begin
  761. if QuickRef then
  762. inc(href.offset);
  763. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  764. href.addressmode:=AM_POSTINCREMENT
  765. else
  766. href.addressmode:=AM_UNCHANGED;
  767. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  768. end;
  769. end;
  770. OS_S8:
  771. begin
  772. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  773. href.addressmode:=AM_POSTINCREMENT;
  774. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  775. if tcgsize2size[tosize]>1 then
  776. begin
  777. tmpreg:=getintregister(list,OS_8);
  778. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  779. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  780. list.concat(taicpu.op_reg(A_COM,tmpreg));
  781. for i:=2 to tcgsize2size[tosize] do
  782. begin
  783. if QuickRef then
  784. inc(href.offset);
  785. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  786. href.addressmode:=AM_POSTINCREMENT
  787. else
  788. href.addressmode:=AM_UNCHANGED;
  789. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  790. end;
  791. end;
  792. end;
  793. OS_16:
  794. begin
  795. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  796. href.addressmode:=AM_POSTINCREMENT;
  797. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  798. if QuickRef then
  799. inc(href.offset)
  800. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  801. href.addressmode:=AM_POSTINCREMENT
  802. else
  803. href.addressmode:=AM_UNCHANGED;
  804. reg:=GetNextReg(reg);
  805. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  806. for i:=3 to tcgsize2size[tosize] do
  807. begin
  808. if QuickRef then
  809. inc(href.offset);
  810. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  811. href.addressmode:=AM_POSTINCREMENT
  812. else
  813. href.addressmode:=AM_UNCHANGED;
  814. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  815. end;
  816. end;
  817. OS_S16:
  818. begin
  819. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  820. href.addressmode:=AM_POSTINCREMENT;
  821. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  822. if QuickRef then
  823. inc(href.offset)
  824. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  825. href.addressmode:=AM_POSTINCREMENT
  826. else
  827. href.addressmode:=AM_UNCHANGED;
  828. reg:=GetNextReg(reg);
  829. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  830. if tcgsize2size[tosize]>2 then
  831. begin
  832. tmpreg:=getintregister(list,OS_8);
  833. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  834. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  835. list.concat(taicpu.op_reg(A_COM,tmpreg));
  836. for i:=3 to tcgsize2size[tosize] do
  837. begin
  838. if QuickRef then
  839. inc(href.offset);
  840. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  841. href.addressmode:=AM_POSTINCREMENT
  842. else
  843. href.addressmode:=AM_UNCHANGED;
  844. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  845. end;
  846. end;
  847. end;
  848. else
  849. conv_done:=false;
  850. end;
  851. end;
  852. if not conv_done then
  853. begin
  854. for i:=1 to tcgsize2size[fromsize] do
  855. begin
  856. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  857. href.addressmode:=AM_POSTINCREMENT
  858. else
  859. href.addressmode:=AM_UNCHANGED;
  860. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  861. if QuickRef then
  862. inc(href.offset);
  863. reg:=GetNextReg(reg);
  864. end;
  865. end;
  866. if not(QuickRef) then
  867. begin
  868. ungetcpuregister(list,href.base);
  869. ungetcpuregister(list,GetNextReg(href.base));
  870. end;
  871. end;
  872. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  873. const Ref : treference;reg : tregister);
  874. var
  875. href : treference;
  876. conv_done: boolean;
  877. tmpreg : tregister;
  878. i : integer;
  879. QuickRef : boolean;
  880. begin
  881. QuickRef:=false;
  882. if not((Ref.addressmode=AM_UNCHANGED) and
  883. (Ref.symbol=nil) and
  884. ((Ref.base=NR_R28) or
  885. (Ref.base=NR_R29)) and
  886. (Ref.Index=NR_No) and
  887. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  888. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  889. href:=normalize_ref(list,Ref,NR_R30)
  890. else
  891. begin
  892. QuickRef:=true;
  893. href:=Ref;
  894. end;
  895. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  896. internalerror(2011021307);
  897. conv_done:=false;
  898. if tosize<>fromsize then
  899. begin
  900. conv_done:=true;
  901. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  902. fromsize:=tosize;
  903. case fromsize of
  904. OS_8:
  905. begin
  906. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  907. for i:=2 to tcgsize2size[tosize] do
  908. begin
  909. reg:=GetNextReg(reg);
  910. list.concat(taicpu.op_reg(A_CLR,reg));
  911. end;
  912. end;
  913. OS_S8:
  914. begin
  915. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  916. tmpreg:=reg;
  917. if tcgsize2size[tosize]>1 then
  918. begin
  919. reg:=GetNextReg(reg);
  920. list.concat(taicpu.op_reg(A_CLR,reg));
  921. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  922. list.concat(taicpu.op_reg(A_COM,reg));
  923. tmpreg:=reg;
  924. for i:=3 to tcgsize2size[tosize] do
  925. begin
  926. reg:=GetNextReg(reg);
  927. emit_mov(list,reg,tmpreg);
  928. end;
  929. end;
  930. end;
  931. OS_16:
  932. begin
  933. if not(QuickRef) then
  934. href.addressmode:=AM_POSTINCREMENT;
  935. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  936. if QuickRef then
  937. inc(href.offset);
  938. href.addressmode:=AM_UNCHANGED;
  939. reg:=GetNextReg(reg);
  940. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  941. for i:=3 to tcgsize2size[tosize] do
  942. begin
  943. reg:=GetNextReg(reg);
  944. list.concat(taicpu.op_reg(A_CLR,reg));
  945. end;
  946. end;
  947. OS_S16:
  948. begin
  949. if not(QuickRef) then
  950. href.addressmode:=AM_POSTINCREMENT;
  951. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  952. if QuickRef then
  953. inc(href.offset);
  954. href.addressmode:=AM_UNCHANGED;
  955. reg:=GetNextReg(reg);
  956. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  957. tmpreg:=reg;
  958. reg:=GetNextReg(reg);
  959. list.concat(taicpu.op_reg(A_CLR,reg));
  960. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  961. list.concat(taicpu.op_reg(A_COM,reg));
  962. tmpreg:=reg;
  963. for i:=4 to tcgsize2size[tosize] do
  964. begin
  965. reg:=GetNextReg(reg);
  966. emit_mov(list,reg,tmpreg);
  967. end;
  968. end;
  969. else
  970. conv_done:=false;
  971. end;
  972. end;
  973. if not conv_done then
  974. begin
  975. for i:=1 to tcgsize2size[fromsize] do
  976. begin
  977. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  978. href.addressmode:=AM_POSTINCREMENT
  979. else
  980. href.addressmode:=AM_UNCHANGED;
  981. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  982. if QuickRef then
  983. inc(href.offset);
  984. reg:=GetNextReg(reg);
  985. end;
  986. end;
  987. if not(QuickRef) then
  988. begin
  989. ungetcpuregister(list,href.base);
  990. ungetcpuregister(list,GetNextReg(href.base));
  991. end;
  992. end;
  993. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  994. var
  995. conv_done: boolean;
  996. tmpreg : tregister;
  997. i : integer;
  998. begin
  999. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1000. internalerror(2011021310);
  1001. conv_done:=false;
  1002. if tosize<>fromsize then
  1003. begin
  1004. conv_done:=true;
  1005. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1006. fromsize:=tosize;
  1007. case fromsize of
  1008. OS_8:
  1009. begin
  1010. emit_mov(list,reg2,reg1);
  1011. for i:=2 to tcgsize2size[tosize] do
  1012. begin
  1013. reg2:=GetNextReg(reg2);
  1014. list.concat(taicpu.op_reg(A_CLR,reg2));
  1015. end;
  1016. end;
  1017. OS_S8:
  1018. begin
  1019. emit_mov(list,reg2,reg1);
  1020. if tcgsize2size[tosize]>1 then
  1021. begin
  1022. reg2:=GetNextReg(reg2);
  1023. list.concat(taicpu.op_reg(A_CLR,reg2));
  1024. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1025. list.concat(taicpu.op_reg(A_COM,reg2));
  1026. tmpreg:=reg2;
  1027. for i:=3 to tcgsize2size[tosize] do
  1028. begin
  1029. reg2:=GetNextReg(reg2);
  1030. emit_mov(list,reg2,tmpreg);
  1031. end;
  1032. end;
  1033. end;
  1034. OS_16:
  1035. begin
  1036. emit_mov(list,reg2,reg1);
  1037. reg1:=GetNextReg(reg1);
  1038. reg2:=GetNextReg(reg2);
  1039. emit_mov(list,reg2,reg1);
  1040. for i:=3 to tcgsize2size[tosize] do
  1041. begin
  1042. reg2:=GetNextReg(reg2);
  1043. list.concat(taicpu.op_reg(A_CLR,reg2));
  1044. end;
  1045. end;
  1046. OS_S16:
  1047. begin
  1048. emit_mov(list,reg2,reg1);
  1049. reg1:=GetNextReg(reg1);
  1050. reg2:=GetNextReg(reg2);
  1051. emit_mov(list,reg2,reg1);
  1052. if tcgsize2size[tosize]>2 then
  1053. begin
  1054. reg2:=GetNextReg(reg2);
  1055. list.concat(taicpu.op_reg(A_CLR,reg2));
  1056. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1057. list.concat(taicpu.op_reg(A_COM,reg2));
  1058. tmpreg:=reg2;
  1059. for i:=4 to tcgsize2size[tosize] do
  1060. begin
  1061. reg2:=GetNextReg(reg2);
  1062. emit_mov(list,reg2,tmpreg);
  1063. end;
  1064. end;
  1065. end;
  1066. else
  1067. conv_done:=false;
  1068. end;
  1069. end;
  1070. if not conv_done and (reg1<>reg2) then
  1071. begin
  1072. for i:=1 to tcgsize2size[fromsize] do
  1073. begin
  1074. emit_mov(list,reg2,reg1);
  1075. reg1:=GetNextReg(reg1);
  1076. reg2:=GetNextReg(reg2);
  1077. end;
  1078. end;
  1079. end;
  1080. procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1081. begin
  1082. internalerror(2012010702);
  1083. end;
  1084. procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1085. begin
  1086. internalerror(2012010703);
  1087. end;
  1088. procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1089. begin
  1090. internalerror(2012010704);
  1091. end;
  1092. { comparison operations }
  1093. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  1094. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  1095. var
  1096. swapped : boolean;
  1097. tmpreg : tregister;
  1098. i : byte;
  1099. begin
  1100. if a=0 then
  1101. begin
  1102. swapped:=false;
  1103. { swap parameters? }
  1104. case cmp_op of
  1105. OC_GT:
  1106. begin
  1107. swapped:=true;
  1108. cmp_op:=OC_LT;
  1109. end;
  1110. OC_LTE:
  1111. begin
  1112. swapped:=true;
  1113. cmp_op:=OC_GTE;
  1114. end;
  1115. OC_BE:
  1116. begin
  1117. swapped:=true;
  1118. cmp_op:=OC_AE;
  1119. end;
  1120. OC_A:
  1121. begin
  1122. swapped:=true;
  1123. cmp_op:=OC_B;
  1124. end;
  1125. end;
  1126. if swapped then
  1127. list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
  1128. else
  1129. list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
  1130. for i:=2 to tcgsize2size[size] do
  1131. begin
  1132. reg:=GetNextReg(reg);
  1133. if swapped then
  1134. list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
  1135. else
  1136. list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
  1137. end;
  1138. a_jmp_cond(list,cmp_op,l);
  1139. end
  1140. else
  1141. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1142. end;
  1143. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1144. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1145. var
  1146. swapped : boolean;
  1147. tmpreg : tregister;
  1148. i : byte;
  1149. begin
  1150. swapped:=false;
  1151. { swap parameters? }
  1152. case cmp_op of
  1153. OC_GT:
  1154. begin
  1155. swapped:=true;
  1156. cmp_op:=OC_LT;
  1157. end;
  1158. OC_LTE:
  1159. begin
  1160. swapped:=true;
  1161. cmp_op:=OC_GTE;
  1162. end;
  1163. OC_BE:
  1164. begin
  1165. swapped:=true;
  1166. cmp_op:=OC_AE;
  1167. end;
  1168. OC_A:
  1169. begin
  1170. swapped:=true;
  1171. cmp_op:=OC_B;
  1172. end;
  1173. end;
  1174. if swapped then
  1175. begin
  1176. tmpreg:=reg1;
  1177. reg1:=reg2;
  1178. reg2:=tmpreg;
  1179. end;
  1180. list.concat(taicpu.op_reg_reg(A_CP,reg1,reg2));
  1181. for i:=2 to tcgsize2size[size] do
  1182. begin
  1183. reg1:=GetNextReg(reg1);
  1184. reg2:=GetNextReg(reg2);
  1185. list.concat(taicpu.op_reg_reg(A_CPC,reg1,reg2));
  1186. end;
  1187. a_jmp_cond(list,cmp_op,l);
  1188. end;
  1189. procedure tcgavr.a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister);
  1190. begin
  1191. Comment(V_Error,'tcgarm.a_bit_scan_reg_reg method not implemented');
  1192. end;
  1193. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1194. var
  1195. ai : taicpu;
  1196. begin
  1197. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s));
  1198. ai.is_jmp:=true;
  1199. list.concat(ai);
  1200. end;
  1201. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1202. var
  1203. ai : taicpu;
  1204. begin
  1205. ai:=taicpu.op_sym(A_JMP,l);
  1206. ai.is_jmp:=true;
  1207. list.concat(ai);
  1208. end;
  1209. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1210. var
  1211. ai : taicpu;
  1212. begin
  1213. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1214. ai.is_jmp:=true;
  1215. list.concat(ai);
  1216. end;
  1217. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1218. var
  1219. l : TAsmLabel;
  1220. tmpflags : TResFlags;
  1221. begin
  1222. current_asmdata.getjumplabel(l);
  1223. {
  1224. if flags_to_cond(f) then
  1225. begin
  1226. tmpflags:=f;
  1227. inverse_flags(tmpflags);
  1228. list.concat(taicpu.op_reg(A_CLR,reg));
  1229. a_jmp_flags(list,tmpflags,l);
  1230. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1231. end
  1232. else
  1233. }
  1234. begin
  1235. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1236. a_jmp_flags(list,f,l);
  1237. list.concat(taicpu.op_reg(A_CLR,reg));
  1238. end;
  1239. cg.a_label(list,l);
  1240. end;
  1241. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1242. var
  1243. i : integer;
  1244. begin
  1245. case value of
  1246. 0:
  1247. ;
  1248. -14..-1:
  1249. begin
  1250. if ((-value) mod 2)<>0 then
  1251. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1252. for i:=1 to (-value) div 2 do
  1253. list.concat(taicpu.op_const(A_RCALL,0));
  1254. end;
  1255. 1..7:
  1256. begin
  1257. for i:=1 to value do
  1258. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1259. end;
  1260. else
  1261. begin
  1262. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1263. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1264. // get SREG
  1265. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1266. // block interrupts
  1267. list.concat(taicpu.op_none(A_CLI));
  1268. // write high SP
  1269. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1270. // release interrupts
  1271. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1272. // write low SP
  1273. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1274. end;
  1275. end;
  1276. end;
  1277. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1278. begin
  1279. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1280. result:=A_LDS
  1281. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1282. result:=A_LDD
  1283. else
  1284. result:=A_LD;
  1285. end;
  1286. function tcgavr.GetStore(const ref: treference) : tasmop;
  1287. begin
  1288. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1289. result:=A_STS
  1290. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1291. result:=A_STD
  1292. else
  1293. result:=A_ST;
  1294. end;
  1295. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1296. var
  1297. regs : tcpuregisterset;
  1298. reg : tsuperregister;
  1299. begin
  1300. if not(nostackframe) then
  1301. begin
  1302. { save int registers }
  1303. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1304. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1305. regs:=regs+[RS_R28,RS_R29];
  1306. for reg:=RS_R31 downto RS_R0 do
  1307. if reg in regs then
  1308. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1309. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1310. begin
  1311. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1312. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1313. end
  1314. else
  1315. { the framepointer cannot be omitted on avr because sp
  1316. is not a register but part of the i/o map
  1317. }
  1318. internalerror(2011021901);
  1319. a_adjust_sp(list,-localsize);
  1320. end;
  1321. end;
  1322. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1323. var
  1324. regs : tcpuregisterset;
  1325. reg : TSuperRegister;
  1326. LocalSize : longint;
  1327. begin
  1328. if not(nostackframe) then
  1329. begin
  1330. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1331. begin
  1332. LocalSize:=current_procinfo.calc_stackframe_size;
  1333. a_adjust_sp(list,LocalSize);
  1334. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1335. for reg:=RS_R0 to RS_R31 do
  1336. if reg in regs then
  1337. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1338. end
  1339. else
  1340. { the framepointer cannot be omitted on avr because sp
  1341. is not a register but part of the i/o map
  1342. }
  1343. internalerror(2011021902);
  1344. end;
  1345. list.concat(taicpu.op_none(A_RET));
  1346. end;
  1347. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1348. var
  1349. tmpref : treference;
  1350. begin
  1351. if ref.addressmode<>AM_UNCHANGED then
  1352. internalerror(2011021701);
  1353. if assigned(ref.symbol) or (ref.offset<>0) then
  1354. begin
  1355. reference_reset(tmpref,0);
  1356. tmpref.symbol:=ref.symbol;
  1357. tmpref.offset:=ref.offset;
  1358. tmpref.refaddr:=addr_lo8;
  1359. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1360. tmpref.refaddr:=addr_hi8;
  1361. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1362. if (ref.base<>NR_NO) then
  1363. begin
  1364. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1365. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1366. end;
  1367. if (ref.index<>NR_NO) then
  1368. begin
  1369. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1370. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1371. end;
  1372. end
  1373. else if (ref.base<>NR_NO)then
  1374. begin
  1375. emit_mov(list,r,ref.base);
  1376. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1377. if (ref.index<>NR_NO) then
  1378. begin
  1379. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1380. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1381. end;
  1382. end
  1383. else if (ref.index<>NR_NO) then
  1384. begin
  1385. emit_mov(list,r,ref.index);
  1386. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1387. end;
  1388. end;
  1389. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1390. begin
  1391. internalerror(2011021320);
  1392. end;
  1393. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  1394. var
  1395. paraloc1,paraloc2,paraloc3 : TCGPara;
  1396. pd : tprocdef;
  1397. begin
  1398. pd:=search_system_proc('MOVE');
  1399. paraloc1.init;
  1400. paraloc2.init;
  1401. paraloc3.init;
  1402. paramanager.getintparaloc(pd,1,paraloc1);
  1403. paramanager.getintparaloc(pd,2,paraloc2);
  1404. paramanager.getintparaloc(pd,3,paraloc3);
  1405. a_load_const_cgpara(list,OS_SINT,len,paraloc3);
  1406. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1407. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1408. paramanager.freecgpara(list,paraloc3);
  1409. paramanager.freecgpara(list,paraloc2);
  1410. paramanager.freecgpara(list,paraloc1);
  1411. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1412. a_call_name_static(list,'FPC_MOVE');
  1413. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1414. paraloc3.done;
  1415. paraloc2.done;
  1416. paraloc1.done;
  1417. end;
  1418. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  1419. var
  1420. countreg,tmpreg : tregister;
  1421. srcref,dstref : treference;
  1422. copysize,countregsize : tcgsize;
  1423. l : TAsmLabel;
  1424. i : longint;
  1425. SrcQuickRef, DestQuickRef : Boolean;
  1426. begin
  1427. if len>16 then
  1428. begin
  1429. current_asmdata.getjumplabel(l);
  1430. reference_reset(srcref,0);
  1431. reference_reset(dstref,0);
  1432. srcref.base:=NR_R30;
  1433. srcref.addressmode:=AM_POSTINCREMENT;
  1434. dstref.base:=NR_R26;
  1435. dstref.addressmode:=AM_POSTINCREMENT;
  1436. copysize:=OS_8;
  1437. if len<256 then
  1438. countregsize:=OS_8
  1439. else if len<65536 then
  1440. countregsize:=OS_16
  1441. else
  1442. internalerror(2011022007);
  1443. countreg:=getintregister(list,countregsize);
  1444. a_load_const_reg(list,countregsize,len,countreg);
  1445. a_loadaddr_ref_reg(list,source,NR_R30);
  1446. tmpreg:=getaddressregister(list);
  1447. a_loadaddr_ref_reg(list,dest,tmpreg);
  1448. { X is used for spilling code so we can load it
  1449. only by a push/pop sequence, this can be
  1450. optimized later on by the peephole optimizer
  1451. }
  1452. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1453. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1454. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1455. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1456. cg.a_label(list,l);
  1457. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1458. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1459. a_op_const_reg(list,OP_SUB,countregsize,1,countreg);
  1460. a_jmp_flags(list,F_NE,l);
  1461. // keep registers alive
  1462. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1463. end
  1464. else
  1465. begin
  1466. SrcQuickRef:=false;
  1467. DestQuickRef:=false;
  1468. if not((source.addressmode=AM_UNCHANGED) and
  1469. (source.symbol=nil) and
  1470. ((source.base=NR_R28) or
  1471. (source.base=NR_R29)) and
  1472. (source.Index=NR_NO) and
  1473. (source.Offset in [0..64-len])) and
  1474. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1475. srcref:=normalize_ref(list,source,NR_R30)
  1476. else
  1477. begin
  1478. SrcQuickRef:=true;
  1479. srcref:=source;
  1480. end;
  1481. if not((dest.addressmode=AM_UNCHANGED) and
  1482. (dest.symbol=nil) and
  1483. ((dest.base=NR_R28) or
  1484. (dest.base=NR_R29)) and
  1485. (dest.Index=NR_No) and
  1486. (dest.Offset in [0..64-len])) and
  1487. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1488. begin
  1489. if not(SrcQuickRef) then
  1490. begin
  1491. tmpreg:=getaddressregister(list);
  1492. dstref:=normalize_ref(list,dest,tmpreg);
  1493. { X is used for spilling code so we can load it
  1494. only by a push/pop sequence, this can be
  1495. optimized later on by the peephole optimizer
  1496. }
  1497. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1498. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1499. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1500. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1501. dstref.base:=NR_R26;
  1502. end
  1503. else
  1504. dstref:=normalize_ref(list,dest,NR_R30);
  1505. end
  1506. else
  1507. begin
  1508. DestQuickRef:=true;
  1509. dstref:=dest;
  1510. end;
  1511. for i:=1 to len do
  1512. begin
  1513. if not(SrcQuickRef) and (i<len) then
  1514. srcref.addressmode:=AM_POSTINCREMENT
  1515. else
  1516. srcref.addressmode:=AM_UNCHANGED;
  1517. if not(DestQuickRef) and (i<len) then
  1518. dstref.addressmode:=AM_POSTINCREMENT
  1519. else
  1520. dstref.addressmode:=AM_UNCHANGED;
  1521. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1522. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1523. if SrcQuickRef then
  1524. inc(srcref.offset);
  1525. if DestQuickRef then
  1526. inc(dstref.offset);
  1527. end;
  1528. if not(SrcQuickRef) then
  1529. begin
  1530. ungetcpuregister(list,srcref.base);
  1531. ungetcpuregister(list,GetNextReg(srcref.base));
  1532. end;
  1533. end;
  1534. end;
  1535. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1536. var
  1537. hl : tasmlabel;
  1538. ai : taicpu;
  1539. cond : TAsmCond;
  1540. begin
  1541. if not(cs_check_overflow in current_settings.localswitches) then
  1542. exit;
  1543. current_asmdata.getjumplabel(hl);
  1544. if not ((def.typ=pointerdef) or
  1545. ((def.typ=orddef) and
  1546. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  1547. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  1548. cond:=C_VC
  1549. else
  1550. cond:=C_CC;
  1551. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1552. ai.SetCondition(cond);
  1553. ai.is_jmp:=true;
  1554. list.concat(ai);
  1555. a_call_name(list,'FPC_OVERFLOW',false);
  1556. a_label(list,hl);
  1557. end;
  1558. procedure tcgavr.g_save_registers(list: TAsmList);
  1559. begin
  1560. { this is done by the entry code }
  1561. end;
  1562. procedure tcgavr.g_restore_registers(list: TAsmList);
  1563. begin
  1564. { this is done by the exit code }
  1565. end;
  1566. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1567. var
  1568. ai1,ai2 : taicpu;
  1569. hl : TAsmLabel;
  1570. begin
  1571. ai1:=Taicpu.Op_sym(A_BRxx,l);
  1572. ai1.is_jmp:=true;
  1573. hl:=nil;
  1574. case cond of
  1575. OC_EQ:
  1576. ai1.SetCondition(C_EQ);
  1577. OC_GT:
  1578. begin
  1579. { emulate GT }
  1580. current_asmdata.getjumplabel(hl);
  1581. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1582. ai2.SetCondition(C_EQ);
  1583. ai2.is_jmp:=true;
  1584. list.concat(ai2);
  1585. ai1.SetCondition(C_GE);
  1586. end;
  1587. OC_LT:
  1588. ai1.SetCondition(C_LT);
  1589. OC_GTE:
  1590. ai1.SetCondition(C_GE);
  1591. OC_LTE:
  1592. begin
  1593. { emulate LTE }
  1594. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1595. ai2.SetCondition(C_EQ);
  1596. ai2.is_jmp:=true;
  1597. list.concat(ai2);
  1598. ai1.SetCondition(C_LT);
  1599. end;
  1600. OC_NE:
  1601. ai1.SetCondition(C_NE);
  1602. OC_BE:
  1603. begin
  1604. { emulate BE }
  1605. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1606. ai2.SetCondition(C_EQ);
  1607. ai2.is_jmp:=true;
  1608. list.concat(ai2);
  1609. ai1.SetCondition(C_LO);
  1610. end;
  1611. OC_B:
  1612. ai1.SetCondition(C_LO);
  1613. OC_AE:
  1614. ai1.SetCondition(C_SH);
  1615. OC_A:
  1616. begin
  1617. { emulate A (unsigned GT) }
  1618. current_asmdata.getjumplabel(hl);
  1619. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1620. ai2.SetCondition(C_EQ);
  1621. ai2.is_jmp:=true;
  1622. list.concat(ai2);
  1623. ai1.SetCondition(C_SH);
  1624. end;
  1625. else
  1626. internalerror(2011082501);
  1627. end;
  1628. list.concat(ai1);
  1629. if assigned(hl) then
  1630. a_label(list,hl);
  1631. end;
  1632. procedure tcgavr.g_stackpointer_alloc(list: TAsmList; size: longint);
  1633. begin
  1634. internalerror(201201071);
  1635. end;
  1636. procedure tcgavr.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
  1637. begin
  1638. internalerror(2011021324);
  1639. end;
  1640. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1641. var
  1642. instr: taicpu;
  1643. begin
  1644. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1645. list.Concat(instr);
  1646. { Notify the register allocator that we have written a move instruction so
  1647. it can try to eliminate it. }
  1648. add_move_instruction(instr);
  1649. end;
  1650. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1651. begin
  1652. if not(size in [OS_S64,OS_64]) then
  1653. internalerror(2012102402);
  1654. tcgavr(cg).a_op_reg_reg_internal(list,Op,size,regsrc.reglo,regsrc.reghi,regdst.reglo,regdst.reghi);
  1655. end;
  1656. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1657. begin
  1658. tcgavr(cg).a_op_const_reg_internal(list,Op,size,value,reg.reglo,reg.reghi);
  1659. end;
  1660. procedure create_codegen;
  1661. begin
  1662. cg:=tcgavr.create;
  1663. cg64:=tcg64favr.create;
  1664. end;
  1665. end.