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aasmcpu.pas
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be9bfbecc5
typo fixed
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11 months ago |
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aoptcpu.pas
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75a9c5b500
Also avoid invalid typecast for RegLoadedWithNewValue method for mips, sparcgen and xtensa
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4 years ago |
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aoptcpub.pas
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9b0ff05ee8
- get rid of MaxOps, it is redundant with max_operands
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6 years ago |
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aoptcpud.pas
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0c8546f94c
* more MIPS code of David Zhang integrated
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16 years ago |
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cgcpu.pas
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f49da05633
* unified g_concatcopy_move
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1 year ago |
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cpubase.pas
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8bd1f19639
* few MIPS64 fixes
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3 years ago |
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cpuelf.pas
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637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
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4 years ago |
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cpugas.pas
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e8c6274915
Add -msoft-float or -mhard-float option to GNU assembler calls
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11 months ago |
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cpuinfo.pas
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7b02331168
+ added fpu_libgcc to MIPS
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11 months ago |
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cpunode.pas
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a0efde8167
* automatically generate necessary indirect symbols when a new assembler
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9 years ago |
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cpupara.pas
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180c23b395
* MIPS code gen: don't use FPU registers for function parameters in case SoftFPU
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11 months ago |
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cpupi.pas
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034c361804
resolveReadAfterWrite moved to aasmcpu.pas
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11 months ago |
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cputarg.pas
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17c0765655
Indentation
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11 months ago |
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hlcgcpu.pas
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e9d8bcf484
hlcgcpu.pas: uses unit systems + t_ps1.pas: correct Message3
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11 months ago |
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itcpugas.pas
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281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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6 years ago |
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mipsreg.dat
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f870b0f8fc
Fix stabs number for FPU register, which start at 38 instead of 32
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8 years ago |
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ncpuadd.pas
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b2e553d3c4
* mips64el compiler can be compiled
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3 years ago |
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ncpucall.pas
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4c68ea1000
* use pocalls_cdecl and cstylearrayofconst more consistently instead of
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8 years ago |
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ncpucnv.pas
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b077d17cdd
* MIPS: don't generate FPU code for int to real conversion when FPU emulation is enabled
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11 months ago |
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ncpuinln.pas
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bf7bf44727
* MIPS: don't generate FPU code for abs(real), sqr(real) and sqrt(real) in case
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11 months ago |
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ncpuld.pas
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281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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6 years ago |
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ncpumat.pas
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85c7368759
* handle also simulated flags in tmipselnotnode.second_boolean, resolves #39877
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3 years ago |
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ncpuset.pas
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07bd4ba517
* let all the case code generation work with tconstexprint instead of aint,
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6 years ago |
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opcode.inc
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2f5cbbacb7
DynArrays works
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11 months ago |
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racpugas.pas
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637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
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4 years ago |
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rgcpu.pas
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03f4685455
+ sanity checks in mips and sparc register allocator
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3 years ago |
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rmipscon.inc
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 years ago |
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rmipsdwf.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsgas.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsgri.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsgss.inc
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f58fcdf401
+ basic mips stuff
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20 years ago |
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rmipsnor.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsnum.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsrni.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipssri.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipssta.inc
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fd6d3b4971
Regenerated after change in mipsreg.dat
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8 years ago |
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rmipsstd.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipssup.inc
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 years ago |
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strinst.inc
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2f5cbbacb7
DynArrays works
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11 months ago |
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symcpu.pas
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7dd1d6aa77
o fixes handling of iso i/o parameters/program parameters:
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10 years ago |
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tripletcpu.pas
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eb7ba1690e
* mark all external assemblers using an LLVM tool using af_llvm
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5 years ago |
Pierre Muller
e8c6274915
Add -msoft-float or -mhard-float option to GNU assembler calls